Last year, Micron unveiled plans to construct a cutting-edge DRAM factory in Hiroshima, Japan. However, the project has faced a significant two-year delay, pushing back the initial timeline for mass production of the company's most advanced memory products. Originally slated to begin mass production by the end of 2025, Micron now aims to have the new facility operational by 2027. The complexity of integrating extreme ultraviolet lithography (EUV) equipment, which enables the production of highly advanced chips, has contributed to the delay. The Hiroshima plant will produce next-generation 1-gamma DRAM and high-bandwidth memory (HBM) designed for generative AI applications. Micron expects the HBM market, currently dominated by rivals SK Hynix and Samsung, to experience rapid growth, with the company targeting a 25% market share by 2025.

The project is expected to cost between 600 and 800 billion Japanese yen ($3.8 to $5.1 billion), with Japan's government covering one-third of the cost. Micron has received a subsidy of up to 192 billion yen ($1.2 billion) for construction and equipment, as well as a subsidy to cover half of the necessary funding to produce HBM at the plant, amounting to 25 billion yen ($159 million). Despite the delay, the increased investment in the factory reflects Micron's commitment to advancing its memory technology and capitalizing on the growing demand for HBM. An indication of that is the fact that customers have pre-ordered 100% of the HBM capacity for 2024, not leaving a single HBM die unused.

According to Reuters, NVIDIA is having some major issues with Samsung's HBM3 chips, as NVIDIA hasn't managed to finalise its validations of the chips. Reuters are citing multiple sources that are familiar with the matter and it seems like Samsung is having some serious issues with its HMB3 chips if the sources are correct. Not only do the chips run hot, which itself is a big issue due to NVIDIA already having issues cooling some of its higher-end products, but the power consumption is apparently not where it should be either. Samsung is said to have tried to get its HBM3 and HBM3E parts validated by NVIDIA since sometime in 2023 according to Reuter's sources, which suggests that there have been issues for at least six months, if not longer.

The sources claim there are issues with both the 8- and 12-layer stacks of HMB3E parts from Samsung, suggesting that NVIDIA might only be able to supply parts from Micron and SK Hynix for now, the latter whom has been supplying HBM3 chips to NVIDIA since the middle of 2022 and HBM3E chips since March of this year. It's unclear if this is a production issue at Samsung's DRAM Fabs, a packaging related issue or something else entirely. The Reuter's piece goes on to speculating about Samsung not having had enough time to develop its HBM parts compared its competitors and that it's a rushed product, but Samsung issued a statement to the publication that it's a matter of customising the product for its customer's needs. Samsung also said that it's "the process of optimising its products through close collaboration with customers" without going into which customer(s). Samsung issued a further statement saying that "claims of failing due to heat and power consumption are not true" and that testing was going as expected.

Phison is arguably the most popular brand for SSD controllers in the client segment, but is turning more of attention to the vast enterprise segment. The company had been making first-party enterprise SSDs under its main marquee, but decided that the lineup needed its own brand that enterprise customers could better discern from the controller ASIC main brand. We hence have Pascari and Imagin. Pascari is an entire product family of fully built enterprise SSDs from Phison. The company's existing first-party drives under the main brand will probably migrate to the Pascari catalog. Imagin, on the other hand, is a design service for large cloud and data-center customers, so they could develop bespoke tiered storage solutions at scale.

The Pascari line of enterprise SSDs are designed completely in-house by Phison, feature their latest controllers, firmware, PCB, PMIC, and on-device power-failure protection on select products. The third-party components here are the NAND flash and DRAM chips, which have both been thoroughly evaluated by Phison for the best performance, endurance, and reliability, at their enterprise SSD design facility in Broomfield, Colorado. Phison already had a constellation of industry partners and suppliers to go around with, and the company's drives even power space missions; but the Pascari brand better differentiates the fully-built SSD lineup from the ASIC make. Pascari makes its debut with the X200 series high-performance SSDs for high-access heat data. The drive leverages Phison's latest PCIe Gen 5 controller technology, the most optimized memory components, and availability in all contemporary server storage form-factors.

NEO Semiconductor, a leading developer of innovative technologies for 3D NAND flash and DRAM memory, today announced a performance boosting Floating Body Cell Mechanism for 3D X-DRAM. Andy Hsu, Founder & CEO presented groundbreaking Technology CAD (TCAD) simulation results for NEO's 3D X-DRAM during the 16th IEEE International Memory Workshop (IMW) 2024 in Seoul, Republic of Korea.

Neo Semiconductor reveals a unique performance boosting mechanism called Back-gate Channel-depth Modulation (BCM) for Floating Body Cell that can increase data retention by 40,000X and sensing window by 20X.

SK hynix announced today that it has developed the Zoned UFS, or ZUFS 4.0, a mobile NAND solution product for on-device AI applications. SK hynix said that the ZUFS 4.0, optimized for on-device AI from mobile devices such as smartphones, is the industry's best of its kind. The company expects the latest product to help expand its AI memory leadership to the NAND space, extending its success in the high-performance DRAM represented by HBM.

The ZUFS is a differentiated technology that classifies and stores data generated from smartphones in different zones in accordance with characteristics. Unlike a conventional UFS, the latest product groups and stores data with similar purposes and frequencies in separate zones, boosting the speed of a smartphone's operating system and management efficiency of the storage devices.

The battle is over. Microsoft is finally changing the measuring methodology in its Task Manager from Mega Hertz (MHz) to Mega Transfers per second (MT/s). This comes amid the industry push for more technical correctness in RAM measuring, where the MHz nomenclature does not technically represent the speed at which the memory is actually running. While DRAM manufacturers list both MHz and MT/s, the advertised MHz number is much higher than the effective speed at which the DRAM is running, resulting in confusion and arguments in the industry about choosing the correct labeling of DRAM. A little history lesson teaches us that when single data rate (SDR) RAM was introduced, 100 MHz memory would perform 100 MT/s. However, when double data rate (DDR) memory appeared, it would allow for two memory transfers per clock cycle.

This would introduce some confusion where the MHz speed is often mixed up with MT/s. Hence, Microsoft is trying to repair the damage and list memory speeds in MT/s. Modern DDR5 memory makers are advertising DDR5 kits with "DDR5-4800" or "DDR5-6000," without any suffix like MHz or MT/s. This is because, for example, a DDR5-6000 kit runs at 6,000 MT/s, the effective speed is only 3,000 MHz. The actual clock of the memory is only half of what is advertised. The MT/s terminology would be more accurate and describe memory better. This Task Manager update is in the Windows 11 Insider Preview Build 22635.3570 in the Beta Channel, which will trickle down to stable Windows 11 updates for everyone soon.

TrendForce's latest forecasts reveal contract prices for DRAM in the second quarter are expected to increase by 13-18%, while NAND Flash contract prices have been adjusted to a 15-20% Only eMMC/UFS will be seeing a smaller price increase of about 10%.

Before the 4/03 earthquake, TrendForce had initially predicted that DRAM contract prices would see a seasonal rise of 3-8% and NAND Flash 13-18%, significantly tapering from Q1 as seen from spot price indicators which showed weakening price momentum and reduced transaction volumes. This was primarily due to subdued demand outside of AI applications, particularly with no signs of recovery in demand for notebooks and smartphones. Inventory levels were gradually increasing, especially among PC OEMs. Additionally, with DRAM and NAND Flash prices having risen for 2-3 consecutive quarters, the willingness of buyers to accept further substantial price increases had diminished.

Thanks to recent developments in the AI field, and following in the wake of the world's recovery from COVID-19, the transition of factories to partial or full automation proceeds with unstoppable momentum. And the best place to learn about the latest technologies that aim to make this transition as painless as possible is at Automate 2024. This is North America's largest robotics and automation event, and it will be held in Chicago, Illinois from May 6 to 9.

Automate attracts professionals from around the world, and Apacer is no exception. Apacer team will be on hand to discuss the latest technological developments created by our experienced R&D team. Many of these developments were specifically created to reduce the pain points commonly experienced by fully automated facilities. Take CoreSnapshot, for example. This backup and recovery technology can restore a crashed system to full operation in just a few seconds, reducing downtime and associated maintenance costs. Apacer recently updated CoreSnapshot, creating CoreRescue ASR and CoreRescue USR. The name of CoreRescue ASR refers to Auto Self Recovery. This technology will harness AI to learn the system booting process and analyze how long a boot should take. If this average boot time is significantly longer than usual, the system will trigger the self-recovery process and revert to an earlier, uncorrupted version of the drive's content. CoreRescue USR offers similar functionality, except the self-recovery process is triggered by connecting a small USB stick drive.

SK hynix participated in the first-ever Compute Express Link Consortium Developers Conference (CXL DevCon) held in Santa Clara, California from April 30-May 1. Organized by a group of more than 240 global semiconductor companies known as the CXL Consortium, CXL DevCon 2024 welcomed a majority of the consortium's members to showcase their latest technologies and research results.

CXL is a technology that unifies the interfaces of different devices in a system such as semiconductor memory, storage, and logic chips. As it can increase system bandwidth and processing capacity, CXL is receiving attention as a key technology for the AI era in which high performance and capacity are essential. Under the slogan "Memory, The Power of AI," SK hynix showcased a range of CXL products at the conference that are set to strengthen the company's leadership in AI memory technology.

Micron Technology, Inc. (Nasdaq: MU), today announced it is leading the industry by validating and shipping its high-capacity monolithic 32Gb DRAM die-based 128 GB DDR5 RDIMM memory in speeds up to 5,600 MT/s on all leading server platforms. Powered by Micron's industry-leading 1β (1-beta) technology, the 128 GB DDR5 RDIMM memory delivers more than 45% improved bit density, up to 22% improved energy efficiency and up to 16% lower latency over competitive 3DS through-silicon via (TSV) products.

Micron's collaboration with industry leaders and customers has yielded broad adoption of these new high-performance, large-capacity modules across high-volume server CPUs. These high-speed memory modules were engineered to meet the performance needs of a wide range of mission-critical applications in data centers, including artificial intelligence (AI) and machine learning (ML), high-performance computing (HPC), in-memory databases (IMDBs) and efficient processing for multithreaded, multicore count general compute workloads. Micron's 128 GB DDR5 RDIMM memory will be supported by a robust ecosystem including AMD, Hewlett Packard Enterprise (HPE), Intel, Supermicro, along with many others.

A few months ago, we covered proof of overclocking an off-the-shelf 2.5-inch SATA III NAND Flash SSD thanks to Gabriel Ferraz, Computer Engineer and TechPowerUp's SSD database maintainer. Now, he is back with another equally interesting project of modifying a Quad-Level Cell (QLC) SATA III SSD into a Single-Level Cell (SLC) SATA III SSD. Using the Crucial BX500 512 GB SSD, he aimed at transforming the QLC drive into a more endurant and higher-performance SLC. Silicon Motion SM2259XT2 powers the drive of choice with a single-core ARC 32-bit CPU clocked at 550 MHz and two channels running at 800 MT/s (400 MHz) without a DRAM cache. This particular SSD uses four NAND Flash dies from Micron with NY240 part numbers. Two dies are controlled per channel. These NAND Flash dies were designed to operate at 1,600 MT/s (800 MHz) but are limited to only 525 MT/s in this drive in the real world.

The average endurance of these dies is 1,500 P/E cycles in NANDs FortisFlash and about 900 P/E cycles in Mediagrade. Transforming the same drive in the pSLC is bumping those numbers to 100,000 and 60,000, respectively. However, getting that to work is the tricky part. To achieve this, you have to download MPtools for the Silicon Motion SM2259XT2 controller from the USBdev.ru website and find the correct die used in the SSD. Then, the software is modified carefully, and a case-sensitive configuration file is modified to allow for SLC mode, which forces the die to run as a SLC NAND Flash die. Finally, firmware folder must be reached and files need to be moved arround in a way seen in the video.

SK hynix showcased its next-generation technologies and strengthened key partnerships at the TSMC 2024 Technology Symposium held in Santa Clara, California on April 24. At the event, the company displayed its industry-leading HBM AI memory solutions and highlighted its collaboration with TSMC involving the host's CoWoS advanced packaging technology.

TSMC, a global semiconductor foundry, invites its major partners to this annual conference in the first half of each year so they can share their new products and technologies. Attending the event under the slogan "Memory, the Power of AI," SK hynix received significant attention for presenting the industry's most powerful AI memory solution, HBM3E. The product has recently demonstrated industry-leading performance, achieving input/output (I/O) transfer speed of up to 10 gigabits per second (Gbps) in an AI system during a performance validation evaluation.

Micron Technology, Inc., one of the world's largest semiconductor companies and the only U.S.-based manufacturer of memory, and the Biden-Harris Administration today announced that they have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York.

The CHIPS and Science Act grants of $6.1 billion will support Micron's plans to invest approximately $50 billion in gross capex for U.S. domestic leading-edge memory manufacturing through 2030. These grants and additional state and local incentives will support the construction of one leading-edge memory manufacturing fab to be co-located with the company's existing leading-edge R&D facility in Boise, Idaho and the construction of two leading-edge memory fabs in Clay, New York.

SK hynix Inc. announced today that it recorded 12.43 trillion won in revenues, 2.886 trillion won in operating profit (with an operating margin of 23%), and 1.917 trillion won in net profit (with a net margin of 15%) in the first quarter. With revenues marking an all-time high for a first quarter and the operating profit a second-highest following the records of the first quarter of 2018, SK hynix believes that it has entered the phase of a clear rebound following a prolonged downturn.

The company said that an increase in the sales of AI server products backed by its leadership in AI memory technology including HBM and continued efforts to prioritize profitability led to a 734% on-quarter jump in the operating profit. With the sales ratio of eSSD, a premium product, on the rise and the average selling prices rising, the NAND business has also achieved a meaningful turnaround in the same period.

SMART Modular Technologies, Inc. ("SMART"), a division of SGH (Nasdaq: SGH) and a global leader in memory solutions, solid-state drives, and advanced memory, announces its new family of Add-In Cards (AICs) which implements the Compute Express Link (CXL) standard and also supports industry standard DDR5 DIMMs. These are the first in their class, high-density DIMM AICs to adopt the CXL protocol. The SMART 4-DIMM and 8-DIMM products enable server and data center architects to add up to 4 TB of memory in a familiar, easy-to-deploy form factor.

"The market for CXL memory components for data center applications is expected to grow rapidly. Initial production shipments are expected in late 2024 and will surpass the $2 billion mark by 2026. Ultimately, CXL attach rates in the server market will reach 30% including both expansion and pooling use cases," stated Mike Howard, vice president of DRAM and memory markets at TechInsights, an intelligence source to semiconductor innovation and related markets.

SK hynix Inc. announced today that it plans to expand production capacity of the next-generation DRAM including HBM, a core component of the AI infrastructure, in response to the rapidly increasing demand for AI semiconductors. As the board of directors approves the plan, the company will build the M15X fab in Cheongju, North Chungcheong Province, for a new DRAM production base, and invest about 5.3 trillion won for fab construction.

The company plans to start construction at the end of April with an aim to complete in November 2025 for an early mass production. With a gradual increase in equipment investment planned, the total investment in building the new production base will be more than 20 trillion won in the long-term. As a global leader in AI memory, SK hynix expects the expansion in investment to contribute to revitalizing the domestic economy, while refreshing Korea's reputation as a semiconductor powerhouse.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced publication of the JESD79-5C DDR5 SDRAM standard. This important update to the JEDEC DDR5 SDRAM standard includes features designed to improve reliability and security and enhance performance in a wide range of applications from high-performance servers to emerging technologies such as AI and machine learning. JESD79-5C is now available for download from the JEDEC website.

JESD79-5C introduces an innovative solution to improve DRAM data integrity called Per-Row Activation Counting (PRAC). PRAC precisely counts DRAM activations on a wordline granularity. When PRAC-enabled DRAM detects an excessive number of activations, it alerts the system to pause traffic and to designate time for mitigative measures. These interrelated actions underpin PRAC's ability to provide a fundamentally accurate and predictable approach for addressing data integrity challenges through close coordination between the DRAM and the system.

SK hynix Inc. announced today that it has recently signed a memorandum of understanding with TSMC for collaboration to produce next-generation HBM and enhance logic and HBM integration through advanced packaging technology. The company plans to proceed with the development of HBM4, or the sixth generation of the HBM family, slated to be mass-produced from 2026, through this initiative.

SK hynix said the collaboration between the global leader in the AI memory space and TSMC, a top global logic foundry, will lead to more innovations in HBM technology. The collaboration is also expected to enable breakthroughs in memory performance through trilateral collaboration between product design, foundry, and memory provider. The two companies will first focus on improving the performance of the base die that is mounted at the very bottom of the HBM package. HBM is made by stacking a core DRAM die on top of a base die that features TSV technology, and vertically connecting a fixed number of layers in the DRAM stack to the core die with TSV into an HBM package. The base die located at the bottom is connected to the GPU, which controls the HBM.

Samsung Electronics, a world leader in advanced memory technology, today announced that it has developed the industry's first LPDDR5X DRAM supporting the industry's highest performance of up to 10.7 gigabits-per-second (Gbps). Leveraging 12 nanometer (nm)-class process technology, Samsung has achieved the smallest chip size among existing LPDDRs, solidifying its technological leadership in the low-power DRAM market.

"As demand for low-power, high-performance memory increases, LPDDR DRAM is expected to expand its applications from mainly mobile to other areas that traditionally require higher performance and reliability such as PCs, accelerators, servers and automobiles," said YongCheol Bae, Executive Vice President of Memory Product Planning of the Memory Business at Samsung Electronics. "Samsung will continue to innovate and deliver optimized products for the upcoming on-device AI era through close collaboration with customers." With the surge in AI applications, on-device AI, which enables direct processing on devices, is becoming increasingly crucial, underscoring the need for low-power, high-performance LPDDR memory.

Montage Technology, a leading data processing and interconnect IC company, today announced that it has taken the lead in the trial production of 1st-generation DDR5 Clock Driver (CKD) chips for next-generation client memory. This new product aims to enhance the speed and stability of memory data access to match the ever-increasing CPU operating speed and performance.

Previously, clock driver functionality was integrated into the Registering Clock Driver (RCD) chips used on server RDIMM or LRDIMM modules, not deployed to the PCs. In the DDR5 era, as data rates climb 6400 MT/s and above, the clock driver has emerged as an indispensable component for client memory.

Following in the wake of an earthquake that struck on April 3rd, TrendForce undertook an in-depth analysis of its effects on the DRAM industry, uncovering a sector that has shown remarkable resilience and faced minimal interruptions. Despite some damage and the necessity for inspections or disposal of wafers among suppliers, the facilities' strong earthquake preparedness of the facilities has kept the overall impact to a minimum.

Leading DRAM producers, including Micron, Nanya, PSMC, and Winbond had all returned to full operational status by April 8th. In particular, Micron's progression to cutting-edge processes—specifically the 1alpha and 1beta nm technologies—is anticipated to significantly alter the landscape of DRAM bit production. In contrast, other Taiwanese DRAM manufacturers are still working with 38 and 25 nm processes, contributing less to total output. TrendForce estimates that the earthquake's effect on DRAM production for the second quarter will be limited to a manageable 1%.

Micron Technology, Inc., today announced it is sampling the automotive-grade Micron 4150AT SSD, the world's first quad-port SSD, capable of interfacing with up to four systems on chips (SoCs) to centralize storage for software-defined intelligent vehicles. The Micron 4150AT SSD combines market-leading features such as single-root input/output virtualization (SR-IOV), a PCIe Generation 4 interface and ruggedized automotive design. With these features, the automotive-grade SSD provides the ecosystem with data center-level flexibility and power.

"As storage requirements race to keep up with rich in-vehicle experiences featuring AI and advanced algorithms for higher levels of autonomous safety, this era demands a new paradigm for automotive storage to match," said Michael Basca, Micron vice president of embedded products and systems. "Building on our collaboration with the innovators redefining next-generation automotive architectures, Micron has reimagined storage from the ground up to deliver the world's first quad-port SSD - the Micron 4150AT - which provides the industry flexibility and horsepower to roll out the transformative technologies on the horizon."

SK hynix Inc., the world's leading producer of High-Bandwidth Memory (HBM) chips, announced today that it will invest an estimated $3.87 billion in West Lafayette, Indiana to build an advanced packaging fabrication and R&D facility for AI products. The project, the first of its kind in the United States, is expected to drive innovation in the nation's AI supply chain, while bringing more than a thousand new jobs to the region.

The company held an investment agreement ceremony with officials from Indiana State, Purdue University, and the U.S. government at Purdue University in West Lafayette on the 3rd and officially announced the plan. At the event, officials from each party including Governor of Indiana Eric Holcomb, Senator Todd Young, Director of the White House Office of Science and Technology Policy Arati Prabhakar, Assistant Secretary of Commerce Arun Venkataraman, Secretary of Commerce State of Indiana David Rosenberg, Purdue University President Mung Chiang, Chairman of Purdue Research Foundation Mitch Daniels, Mayor of city of West Lafayette Erin Easter, Ambassador of the Republic of Korea to the United States Hyundong Cho, Consul General of the Republic of Korea in Chicago Junghan Kim, SK vice chairman Jeong Joon Yu, SK hynix CEO Kwak Noh-Jung and SK hynix Head of Package & Test Choi Woojin, participated.

Phison Electronics, a leading provider of NAND controllers and NAND storage solutions, today announced a pivotal strategic collaboration with industry giant MediaTek to push forward innovations in generative artificial intelligence (Generative AI) computing and services, and meet demand for fine-tuning AI model computations across industries. Under the collaboration, Phison's cutting-edge AI computing service, aiDAPTIV+, will pair with MediaTek's premier generative AI service platform, MediaTek DaVinci, heralding a new epoch for AI computing and application services and accelerating the adoption of generative AI in everyday life.

MediaTek DaVinci is an advanced, open platform for generative AI services, built on the Generative AI Service Framework (GAISF). MediaTek DaVinci enables developers to build a variety of plugins for enterprise applications, fostering a vibrant ecosystem and enhancing the user experience. Phison's aiDAPTIV+ features a pioneering SSD-integrated AI computing architecture that breaks down large AI models for concurrent operation with SSDs. This approach significantly reduces infrastructure costs and boosts computational efficiency, enabling the training of substantial AI models with limited GPU and DRAM resources. aiDAPTIV+ has already demonstrated its effectiveness in the Industry 4.0 sector and is poised to accelerate AI transformation across various sectors, bolstering business competitiveness. Additionally, aiDAPTIV+ consumes less power than traditional AI server setups for the same AI model fine-tuning tasks and this aligns with the current trend of minimizing energy consumption and carbon footprint.

TrendForce's latest report reveals that despite DRAM suppliers' efforts to trim inventories, they have yet to reach healthy ranges. As they continue to improve their lose situations by boosting capacity utilization rates, the overall demand outlook for this year remains tepid. Additionally, significant price increases by suppliers since 4Q23 are expected to further diminish the momentum for inventory restocking. As a result, DRAM contract prices for the second quarter are projected to see a modest increase of 3-8%.

The shift toward DDR5-compatible CPUs is set to drive an increase in PC DRAM demand in the second quarter. As manufacturers move toward more advanced, cost-efficient production processes for DDR5, their profitability is expected to rise significantly. This anticipation of higher DRAM prices in 1H24 has led to suppliers to aim for price increases in Q2, targeting a 3-8% hike in PC DRAM contract prices. Notably, even though DDR5 prices have already seen a notable rise in Q1—exceeding the average increase for other products—the expected emergence of AI PC demand may lead to a slight moderation in DDR5 price increases in Q2.