Connectivity and I/O

The Platform I/O tile is built on the TSMC 6 nm process, and has all the SoC interfaces, platform connectivity. Interestingly, the processor's memory controllers are on the Compute tile that contains the CPU cores, iGPU, and NPU. This memory controller exclusively only supports LPDDR5X, since it only has to drive the on-package memory. Since it has to deal with four bandwidth hungry IP blocks, namely the CPU cores, the iGPU, the NPU, and the Platform I/O tile, the memory controller is cushioned by an 8 MB memory-side cache.


The Platform I/O tile packs many new generation components, including an integrated WLAN controller with Wi-Fi 7 + Bluetooth 5.4, support for 5.8 Gbps WLAN bandwidth, and a Thunderbolt 4 controller with support for up to three 40 Gbps Thunderbolt 4 ports.

The Platform I/O tile is also where the PCI-Express root complex is located. Lunar Lake only puts out 8 PCIe lanes, four of these are Gen 5, and the other four are Gen 4.

The idea behind just 8 PCIe lanes stems from the kind of device the Core Ultra 200V family targets—thin and lights, with no possibility of a discrete GPU. Here, the four Gen 5 lanes would drive a contemporary Gen 5 NVMe SSD, and the other four Gen 4 lanes left for other platform connectivity.

Besides the up to 3 Thunderbolt 4 40 Gbps ports, Lunar Lake supports 5 Gbps and 10 Gbps USB 3.2, and USB 2.0 connectivity. Again, there aren't too many ports, you don't need them on a device of this type. Use an expansion dock or a Thunderbolt-based eGPU if you have to.