Timing and Frequency Scaling

Part of my testing routine involves testing memory samples using a variety of common timings and voltages, in order to judge the flexibility of the modules to match system overclocks. I test 1.65 V DIMMs using three different voltage levels: 1.5 V, the standard JEDEC voltage, 1.65 V, for common voltage scaling, and 1.75 V, for a max OC overvoltage setting. I set the timings for the memory and measure the maximum frequency with each voltage, and then adjust the timings and test again. I employ several tests to measure the performance differences, including AIDA64's built-in memory benchmark, 3DMark 2001, SuperPi v1.55 32M, as well as the RTS game Shogun 2, for some memory-sensitive 3D performance.

Clocking memory on the Intel X79 Express platform can provide some very interesting results, thanks to the introduction of higher memory frequency dividers as well as BCLK dividers, which allow for higher memory clocking than on any previous Intel platform. On Intel Socket 1155 products, BCLK scaling is very limited, with 104 MHz being the average maximum BCLK reported by users over the past 12 months since the Intel P67 Express platform launch. Intel's X79 Express platform expands upon its predecessor by adding both 125 MHz and 166 MHz BCLK dividers, which allow the bus to clock a lot higher. Effectively this divider de-couples the PCIe bus from the BCLK, allowing the ratio between BCLK and PCIe to be adjusted, providing for greater flexibility. Naturally, with a 125 MHz BCLK matched with a 100 MHz PCIe clock, the BLCK can be adjusted in a wider range before pushing the PCIe bus outside of the range of stability, as rather than each MHz in BCLK adjustment moving the PCIe bus by the same increment, one MHz of BLCK adjustment now moves the PCIe bus just 0.8 MHz.

It's important to note that different devices on the PCIe bus have different clock tolerances, and therefore onboard devices that use the PCIe bus can greatly affect how far the BCLK can go. Due to the use of parts common to both SKT 1155 and SKT 2011, the 100 MHz BCLK divider on SKT 2011 doesn't really offer greater flexibility than on SKT 1155, so for greater clock scaling, we employ the 125 MHz BCLK divider whenever possible, and also adjust the CPU multiplier to try to match the same CPU speed for all tests, but as the BLCK used can vary according to the maximum stable memory frequency, so can the CPU speed. For our testing we have kept the CPU speed between 4.0 GHz and 4.1 GHz. The numbers provided within each CAS setting are meant as a reference only, although overall the results do reflect performance increases based on memory performance alone.

Of course, because the PCIe bus still plays a role in the final effective BLCK speed, there are times where FSB "holes" are introduced, as our particular CPU, VGA, and board combination has an effective range of 100 MHz to 105 MHz using the 100 MHz divider, and 113 MHz to 134 MHz using the 125 MHz divider. For example, using the 1066 MHz memory divider and a 133 MHz BCLK results in a 1418 MHz effective memory speed. Dropping the BCLK down to 113 MHz with the 1333 MHz memory divider results in 1506 MHz, so there is a 86 MHz hole in the effective memory speed that just cannot be attained no matter what modules are used.




Of course, a few of you may be asking how come I used these timings instead of anything else, like the timings the G.Skill kit used, which had the same memory ICs, and to that, I do have an answer.


The image above shows a screenshot captured from AIDA 64. As you can see, there is information contained within the XMP profile for timings at lowered operating speeds, which gives a very clear pattern as to how the timings change and the DIMM's frequency is scaled up. Not only are there primary timings listed, but also secondary timings, and I do not feel it would be fair to modify things other than how it's suggested here, as clearly Patriot has done some serious testing if they've added all this info to the SPD ROM. I did test the timings used by other kits and did not find them to actually offer any tangible clocking benefit, but I do think it's important to highlight how differences in timings can lead to wholely different results. It's worth noting as well that although I used the EXACT timings offered in the SPD profile, and I did attempt alternates, there were a single point where I did not reach the clocks as listed in AIDA 64, most notably when using CAS 8. Patriot did a very fine job at selecting the timings, and as you can see in the images above, voltage did not really offer anything worth mentioning for frequency gains, and clearly 1.65 V is the optimal voltage to use too. A set voltage of 1.65 V allowed us to reach each milestone set by default memory dividers, such as 1333 MHz, 1600 MHz, 1866 MHz, and 2133 MHz, and it's more timings that dictated what speed and divider the DIMMs were capable of. It's also very obvious that these sticks were not quite as good as the G.SKill kit, looking at the CAS 10 scaling, however, they ARE rated for 133 MHz less, exactly where they should be based on the clock scaling. Patriot has done a great job binning these PX538G2000ELK sticks.