Controller:
This controller features multiples variants:
F1C - Uses NVMe 1.4
F2C - Uses NVMe 1.4
F3C - Uses NVMe 2.0
F3C U - For 4TB SSDs and uses NVMe 2.0
NAND Die:
Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side