According to Reuters, Samsung is gearing up to increase the chip production capacity at its P3 factory in Pyeongtaek in South Korea, despite the fact that there's a general slowdown in the semiconductor industry, in addition to the general economic downturn. Samsung is apparently planning on adding 12-inch wafer capacity for DRAM, while also adding more 4 nm chip capacity. The P3 fab kicked off production of Samsung's most cutting-edge NAND flash chips earlier this year and is the company's largest fab overall. According to Reuters, Samsung is aiming to add at least 10 new EUV machines in 2023.

In related news via The Elec, Samsung has seen costs increase significantly when it comes to materials costs relating to the expansion of the P3 fab. So far, the company has racked up extra costs of over a trillion korean Won, or more than US$786 million, largely due to all of its contractors having raised their prices. The report also mentioned that some parts of the expansion of the P3 fab has been delayed by as much as a year, which isn't good news for Samsung and it likely means that the company will see further increases in costs before the expansions are finished.

At its 2023 International CES event, NVIDIA is expected to launch not just its desktop GeForce RTX 4070 and RTX 4070 Ti graphics cards, but more importantly, also its GeForce RTX 40-series Laptop GPU series powering next-generation gaming notebooks based on the upcoming 13th Gen Core "Raptor Lake" processors. NVIDIA seems to be making a very tight rope-walk between power-management and generational performance increase in this power- and thermal-constrained form-factor. Wccftech scored a major scoop on the specs of various RTX 40-series Laptop GPUs.

The GeForce RTX 40-series "Ada" Laptop GPU lineup will be led by the RTX 4090 Laptop GPU, based on the 4 nm "AD103" silicon (same one that powers the desktop RTX 4080). It will be equipped with 16 GB of memory, a yet-unknown core-configuration, GPU Boost frequencies of up to 2.04 GHz, and typical power draw ranging between 150 W to 175 W, which can peak up to 200 W thanks to the 25 W dynamic boost range (power permissible by the platform if the other components such as CPU aren't drawing their peak power).

Here are some of the first pictures of a GIGABYTE GeForce RTX 4070 Ti custom-design graphics cards, the RTX 4070 Ti AERO. GIGABYTE targets the AERO brand of graphics cards, motherboards, and notebooks, at creators who like to game, hence the product design that's a lot less flashy than the company's AORUS or Gaming OC brands of graphics cards. An interesting aspect of this card is that it features a 16-pin ATX 12VHPWR connector, and includes an NVIDIA-supplied power adapter that converts two 8-pin PCIe power connectors to one 12VHPWR. We know this adapter is different from the 2x 8-pin to 12-pin adapter NVIDIA included with the RTX 3080 Founders Edition, looking at the four sensor pins.

The connector has keying for 300 W, and so the typical board power of the RTX 4070 Ti will be at or below 300 W. The GeForce RTX 4070 Ti is essentially a re-branding of what would have been the RTX 4080 12 GB, had NVIDIA not decided to "unlaunch" it. The SKU maxes out the 4 nm "AD104" silicon, featuring 7,680 CUDA cores across 60 streaming multiprocessors (SM), 240 Tensor cores, 60 RT cores, 240 TMUs, and 80 ROPs. The chip features a 192-bit GDDR6X memory interface, which was at the heart of the RTX 4080 12 GB naming controversy.

A report by Moore's Law is Dead claims that NVIDIA is preparing to launch a new TITAN RTX halo product, based on a maxed-out 4 nm "AD102" silicon. Where does this put the RTX 4090 Ti? Somewhere in between the RTX 4090 and the TITAN RTX Ada, as NVIDIA gave itself plenty of segmentation headroom with the AD102 silicon, by using just 128 out of 144 SM physically present on the silicon, besides the same 21 Gbps GDDR6X memory as the previous-generation. NVIDIA's options with the new TITAN RTX include enabling all 144 SM (18,432 CUDA cores), and using faster 24 Gbps memory, giving the silicon (1152 GB/s memory bandwidth), a stock power-limit closer to the 600 W design limit of the 12VHPWR power connector (RTX 4090 stock typical board power is 450 W).

Moore's Law is Dead also posted what they claim to be the first real-world pictures of the upcoming TITAN RTX Ada. The card is an unabashed 4-slot enlargement of the dual-axial flow-through RTX 4090 Founders Edition, with the cooler capable of higher thermal loads. TITAN RTX cards are marketed as first-party Founders Edition cards only, and not through NVIDIA's AIC board partners as custom-designs. A maxed out AD102, with higher clock speeds, higher power-limit, and faster memory, should be unassailable for custom-design RTX 4090 cards, if NVIDIA wants to sell this card at the kind of prices its last TITAN RTX product sold at—USD $2,500.

It turns out that NVIDIA has not one, but two new GeForce RTX 40-series "Ada" SKUs on the anvil this January. One of these is the RTX 4070 Ti, which we know well to be a rebranding of the RTX 4080 12 GB in the face of backlash that forced NVIDIA to "unlaunch" it. The other as it turns out, is the RTX 4070, with an interesting set of specifications. Based on the same 4 nm AD104 silicon as the RTX 4070 Ti, the new RTX 4070 is significantly cut down. NVIDIA enabled 46 out of 60 streaming multiprocessors (SM) physically present on the silicon, which yield 5,888 CUDA cores—the same count as the previous-gen RTX 3070, when compared to the 7,680 that the maxed-out RTX 4070 Ti enjoys.

The GeForce RTX 4070, besides 5,888 CUDA cores, gets 46 RT cores, 184 Tensor cores, 184 TMUs, and a reduced ROP count of 64, compared to 80 of the RTX 4070 Ti. The memory configuration remains the same as the RTX 4070 Ti, with 12 GB of 21 Gbps GDDR6X memory across the chip's 192-bit memory interface, working out to 504 GB/s of memory bandwidth. An interesting aspect of this SKU is its board power, rated at 250 W, compared to the 285 W of the RTX 4070 Ti, and the 220 W of its 8 nm predecessor, the RTX 3070.

According to TrendForce's research, the total revenue of the global top 10 foundries rose by 6% QoQ to US$35.21 billion for 3Q22 as the release of the new iPhone series during the second half of the year generated significant stock-up activities across Apple's supply chain. However, the global economy shows weak performances, and factors such as China's policy on containing COVID-19 outbreaks and high inflation continue to impact consumer confidence. As a result, peak-season demand in the second half of the year has been underwhelming, and inventory consumption is proceeding slower than anticipated. This situation has led to substantial downward corrections to foundry orders as well. For 4Q22, TrendForce forecasts that the total revenue of the global top 10 foundries will register a QoQ decline, thereby terminating the boom of the past two years—when there was an uninterrupted trend of QoQ revenue growth.

Regarding individual foundries' performances in 3Q22, the group of the top five was led by TSMC, followed by Samsung, UMC, GlobalFoundries, and SMIC. Their collective global market share (in revenue terms) came to 89.6%. Most foundries were directly impacted by clients slowing down their stock-up activities or significantly correcting down their orders. Only TSMC was able to make a notable gain due to Apple's strong stock-up demand for the SoCs deployed in this year's new iPhone models. TSMC saw its revenue rise by 11.1% QoQ to US$20.16 billion, and the corresponding market share expanded to 56.1%. The growth was mainly attributed to the ≤7 nm nodes, whose share in the foundry's revenue had kept climbing and reached 54% in the third quarter. Conversely, Samsung actually experienced a slight QoQ drop of 0.1% in foundry revenue even though it had also benefited from the component demand related to the new iPhone series. Partially impacted by the weakening of the Korean won, Samsung's market share fell to 15.5%.

Apple and NVIDIA will be among the first customers of TSMC's swanky new $12 billion semiconductor fab in Arizona, USA. Apple will be the first major player to kick off mass-production in the fab, and will be closely followed by NVIDIA. Both companies plan to produce some of their inventory in Arizona, and ramp proportionately up as the fab grows in capacity.

The plan with TSMC's Arizona fab was to originally make 5 nm and 4 nm EUV chips, with an output of 20,000 wafers a month, but the company now expects to deploy a more advanced node to keep up with what will be considered cutting-edge when the fab goes live (think 2 nm-class); and also double the output to 40,000 wafers a month. The capacity should ensure Apple and NVIDIA make their most cutting-edge chips on the node (away from Asia), so there could be tighter export controls, and build supply-chain resilience in the face of security problems arising in the Taiwan straits.

Here's the first picture of the 4 nm "AD104" silicon powering what would have been the $900 GeForce RTX 4080 12 GB, and upcoming RTX 4070-series graphics cards. The third largest GPU based on the "Ada Lovelace" graphics architecture, the AD104 looks tiny. This is because it has roughly half the die-area of the AD102, estimated to be around 295 mm² (compared to 608 mm² of the AD102), which means its transistor count should be less than half, with older reports pinpointing it to 35.8 billion. The RTX 4080 12 GB was supposed to max out the AD104 silicon, enabling all 60 streaming multiprocessors (SM) physically present.

The AD104 with 60 SM hence has 7,680 CUDA cores, 60 RT cores, 240 Tensor cores, 240 TMUs, and 80 ROPs. NVIDIA has generationally narrowed the memory interface (compared to the GA104 and TU104), down to 192-bit GDDR6X. Its predecessors such as the GA104 feature 256-bit wide memory interfaces. NVIDIA is overcoming the memory bus width "deficit" by giving SKUs based on the silicon higher memory speeds (21 Gbps or more); and architecture-level improvements such as larger on-die caches. NVIDIA is reportedly planning to launch an AD104-based SKU early January 2023. VideoCardz reports that could be the RTX 4070 Ti, a re-branding of the RTX 4080 12 GB.

NVIDIA is reportedly planning to ramp its GeForce "Ada" generation into the high-volume performance segment by Summer 2023, with the introduction of the GeForce RTX 4060. The card is expected to launch somewhere around June, 2023. The card will be based on the 4 nm "AD106" silicon, the 4th chip based on the "Ada Lovelace" graphics architecture. Wolstame. a reliable source with NVIDIA leaks as Lenovo's Legion gaming desktop product manager, predicts that the RTX 4060 performance could end up matching that of the current RTX 3070 at a lower price-point.

This should make it a reasonably fast graphics card for 1440p AAA gaming with high-ultra settings, and ray tracing thrown in. What's interesting is if NVIDIA is expected to extend the DLSS 3 frame-generation feature to even this segment of graphics cards, which means a near-100% frame rate uplift can be had. Other predictions include a board power expected to be in the range of 150-180 W, and a 10% generational price-increase, which would mean that the RTX 4060 would have a launch-price similar to that of the RTX 3060 Ti (USD $399).

AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart from classic multi-chip modules (MCMs). An MCM is a package that consists of multiple independent devices sharing a fiberglass substrate.

An example of an MCM would be a mobile Intel Core processor, in which the CPU die and the PCH die share a substrate. Here, the CPU and the PCH are independent pieces of silicon that can otherwise exist on their own packages (as they do on the desktop platform), but have been paired together on a single substrate to minimize PCB footprint, which is precious on a mobile platform. A chiplet-based device is one where a substrate is made up of multiple dies that cannot otherwise independently exist on their own packages without an impact on inter-die bandwidth or latency. They are essentially what should have been components on a monolithic die, but disintegrated into separate dies built on different semiconductor foundry nodes, with a purely cost-driven motive.

EK, the premium liquid cooling gear manufacturer, just launched the ultimate water cooling solution for the complete Gigabyte GeForce RTX 4080 lineup - Aorus Master, Gaming, Aero, and Eagle series GPUs. The EK-Quantum Vector² Master RTX 4080 D-RGB comes in the form of a water block with a black anodized aluminium backplate as an additional cooling surface.

The all-new Gigabyte GeForce RTX 4080 graphics cards are expected to be significantly more powerful than their 30-series counterparts. And while their efficiency is also improved, these cards still pull over 320 W, which means they will benefit even more from water cooling. This is especially true due to the 4 nm production process, which increases thermal density compared to the previous 8 nm chips.

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today announced two major milestones in the commercialization of its technology for multi-die chiplet integration: the close of its Series A $40M funding round, and the successful tapeout of its technology on an industry standard 5-nanometer (nm) process.

Eliyan's NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of specialized approaches.

MediaTek today launched the Dimensity 9200, its latest 5G chipset powering the next era of flagship smartphones. Boasting extreme performance and intelligent power efficiency, the new SoC brings immersive all-day gaming experiences, ultra-sharp image capturing and support for both mmWave 5G and sub-6 GHz connectivity to consumers around the globe.

"MediaTek's Dimensity 9200 combines ultimate performance with significant power savings, extending battery life and keeping smartphones cool," said JC Hsu, Corporate Vice President and General Manager of MediaTek's wireless communications business unit at MediaTek. "With notably brighter image capturing and improved gaming speeds, along with the latest display enhancements, the Dimensity 9200 will bring new possibilities for next-gen smartphones that come in a variety of stylish and foldable form factors."

EK, the premium liquid cooling gear manufacturer, is launching a specialized water block that fits two distinct GPUs from Gigabyte - Aorus GeForce RTX 4090 Master and Gigabyte GeForce RTX 4090 GAMING. EK-Quantum Vector² Master RTX 4090 D-RGB comes in the form of a water block with a passive backplate. The all-new Aorus RTX 4090 Master and Gigabyte RTX 4090 Gaming cards are expected to be significantly more powerful than their 40-series counterparts. And while their efficiency is also improved, these cards still pull over 450 W, which means they will benefit even more from water cooling, mainly due to the 4 nm production process, which increases thermal density compared to the previous 8 nm chips. To top it off, the Master is a behemoth of a card, and opting for water cooling instead of the factory-mounted air cooler, allows you to shrink it several times in the thickness department.

The EK-Quantum Vector² Master RTX 4090 is a single-package liquid cooling solution consisting of a Vector² series water block and black-anodized aluminium backplate. As with the previous 30-series Vector² water blocks, its aesthetics are dominated by minimalist straight lines and the backplate coming around the side of the GPU to cover the PCB completely.

EK, the premium liquid cooling gear manufacturer, is now introducing the ultimate water cooling solution for ROG Strix and ASUS TUF GeForce RTX 4090 graphics cards. EK-Quantum Vector² Strix/TUF RTX 4090 D-RGB comes in the form of a water block with a passive backplate or a cooling solution with an active backplate that's sandwiching the card between two water blocks for the best possible cooling results.

The all-new RTX 4090 Strix and TUF cards are expected to be significantly more powerful than their 30-series counterparts. And while their efficiency is also improved, these cards still pull over 450 W, which means they will benefit even more from water cooling, mainly due to the 4 nm production process, which increases thermal density compared to the previous 8 nm chips.

Samsung Electronics, a world leader in advanced semiconductor technology, announced today a strengthened business strategy for its Foundry Business with the introduction of cutting-edge technologies at its annual Samsung Foundry Forum event. With significant market growth in high-performance computing (HPC), artificial intelligence (AI), 5/6G connectivity and automotive applications, demand for advanced semiconductors has increased dramatically, making innovation in semiconductor process technology critical to the business success of foundry customers. To that end, Samsung highlighted its commitment to bringing its most advanced process technology, 1.4-nanometer (nm), for mass production in 2027.

During the event, Samsung also outlined steps its Foundry Business is taking in order to meet customers' needs, including: foundry process technology innovation, process technology optimization for each specific applications, stable production capabilities, and customized services for customers. "The technology development goal down to 1.4 nm and foundry platforms specialized for each application, together with stable supply through consistent investment are all part of Samsung's strategies to secure customers' trust and support their success," said Dr. Si-young Choi, president and head of Foundry Business at Samsung Electronics. "Realizing every customer's innovations with our partners has been at the core of our foundry service."

Here's our first look at the "AD103" and "AD104" chips powering the GeForce RTX 4080 16 GB and RTX 4080 12 GB, respectively, thanks to Ryan Smith from Anandtech. These are the second- and third-largest implementations of the GeForce "Ada" graphics architecture, with the "AD102" powering the RTX 4090 being the largest. Both chips are built on the same TSMC 4N (4 nm EUV) silicon fabrication process as the AD102, but are significantly distant from it in specifications. For example, the AD102 has a staggering 80 percent more number-crunching machinery than the AD103, and a 50 percent wider memory interface. The sheer numbers at play here, enable NVIDIA to carve out dozens of SKUs based on the three chips alone, before we're shown the mid-range "AD106" in the future.

The AD103 die measures 378.6 mm², significantly smaller than the 608 mm² of the AD102, and it reflects in a much lower transistor count of 45.9 billion. The chip physically features 80 streaming multiprocessors (SM), which work out to 10,240 CUDA cores, 320 Tensor cores, 80 RT cores, and 320 TMUs. The chip is endowed with a healthy ROP count of 112, and has a 256-bit wide GDDR6X memory interface. The AD104 is smaller still, with a die-size of 294.5 mm², a transistor count of 35.8 billion, 60 SM, 7,680 CUDA cores, 240 Tensor cores, 60 RT cores, 240 TMUs, and 80 ROPs. Ryan Smith says that the RTX 4080 12 GB maxes out the AD104, which means its memory interface is physically just 192-bit wide.

The AD102 silicon on which NVIDIA's new flagship graphics card, the GeForce RTX 4090, is based, is a marvel of semiconductor engineering. Built on the 4 nm EUV (TSMC 4N) silicon fabrication process, the chip has a gargantuan transistor-count of 76.3 billion, a nearly 170% increase over the previous GA102, and a die-size of 608 mm², which is in fact smaller than the 628 mm² die-area of the GA102. This is thanks to TSMC 4N offering nearly thrice the transistor-density of the Samsung 8LPP node on which the GA102 is based.

The AD102 physically features 18,432 CUDA cores, 568 fourth-generation Tensor cores, and 142 third-generation RT cores. The streaming multiprocessors (SM) come with special components that enable the Shader Execution Reordering optimization, which has a significant performance impact on both raster- and ray traced graphics rendering performance. The silicon supports up to 24 GB of GDDR6X or up to 48 GB of GDDR6+ECC memory (the latter will be seen in the RTX Ada professional-visualization card), across a 384-bit wide memory bus. There are 568 TMUs, and a mammoth 192 ROPs on the silicon.

AMD in its Ryzen 7000 series launch event shared its near-future CPU architecture roadmap, in which it confirmed that the "Zen 4" microarchitecture, currently on the 5 nm foundry node, will see an optical-shrink to the 4 nm process in the near future. This doesn't necessarily indicate a new-generation CCD (CPU complex die) on 4 nm, it could even be a monolithic mobile SoC on 4 nm, or perhaps even "Zen 4c" (high core-count, low clock-speed, for cloud-compute); but it doesn't rule out the possibility of a 4 nm CCD that the company can use across both its enterprise and client processors.

The last time AMD hyphenated two foundry nodes for a single generation of the "Zen" architecture, was with the original (first-generation) "Zen," which debuted on the 14 nm node, but was optically shrunk and refined on the 12 nm node, with the company designating the evolution as "Zen+." The Ryzen 7000-series desktop processors, as well as the upcoming EPYC "Genoa" server processors, will ship with 5 nm CCDs, with AMD ticking it off in its roadmap. Chronologically placed next to it are "Zen 4" with 3D Vertical Cache (3DV Cache), and the "Zen 4c." The company is planning "Zen 4" with 3DV Cache both for its server- and desktop segments. Further down the roadmap, as we approach 2024, we see the company debut the future "Zen 5" architecture on the same 4 nm node, evolving into 3 nm on certain variants.

NVIDIA designed the Grace CPU, a processor in the classical sense, to replace the Intel Xeon or AMD EPYC processors it was having to cram into its pre-built HPC compute servers for serial-processing roles, and mainly because those half-a-dozen GPU HPC processors need to be interconnected by a CPU. The company studied the CPU-level limitations and bottlenecks not just with I/O, but also the machine-architecture, and realized its compute servers need a CPU purpose-built for the role, with an architecture that's heavily optimized for NVIDIA's APIs. This, the NVIDIA Grace CPU was born.

This is NVIDIA's first outing with a CPU with a processing footprint rivaling server processors from Intel and AMD. Built on the TSMC N4 (4 nm EUV) silicon fabrication process, it is a monolithic chip that's deployed standalone with an H100 HPC processor on a single board that NVIDIA calls a "Superchip." A board with a Grace and an H100, makes up a "Grace Hopper" Superchip. A board with two Grace CPUs makes a Grace CPU Superchip. Each Grace CPU contains a 900 GB/s switching fabric, a coherent interface, which has seven times the bandwidth of PCI-Express 5.0 x16. This is key to connecting the companion H100 processor, or neighboring Superchips on the node, with coherent memory access.

Qualcomm Technologies, Inc. today unveiled the latest additions to the company's suite of premium wearable platforms, Snapdragon W5+ Gen 1 and Snapdragon W5 Gen 1. These platforms are designed to advance ultra-low power and breakthrough performance for next generation connected wearables with a focus on extended battery life, premium user experiences, and sleek, innovative designs. By using these platforms, manufacturers can scale, differentiate, and develop products faster in the continuously growing and segmenting wearables industry.

New enhancements to the flagship Snapdragon W5+ platform offer 50% lower power, 2X higher performance, 2X richer features, and 30% smaller size, compared to our previous generation, enabling wearable manufacturers to deliver the differentiated experiences consumers demand. Based on the hybrid architecture, the purpose-built platform is comprised of a 4 nm-based system-on-chip and 22 nm-based highly integrated always-on co-processor. It incorporates a series of platform innovations including new ultra-low power Bluetooth 5.3 architecture, low power islands for Wi-Fi, GNSS, and Audio, and low power states such as Deep Sleep and Hibernate.

According to TrendForce investigations, foundries have seen a wave of order cancellations with the first of these revisions originating from large-size Driver IC and TDDI, which rely on mainstream 0.1X μm and 55 nm processes, respectively. Although products such as MCU and PMIC were previously in short supply, foundries' capacity utilization rate remained roughly at full capacity through their adjustment of product mix. However, a recent wave cancellations have emerged for PMIC, CIS, and certain MCU and SoC orders. Although still dominated by consumer applications, foundries are beginning to feel the strain of the copious order cancellations from customers and capacity utilization rate has officially declined.

Looking at trends in 2H22, TrendForce indicates, in addition to no relief from the sustained downgrade of driver IC demand, inventory adjustment has begun for smartphones, PCs, and TV-related peripheral components such as SoCs, CIS, and PMICs, and companies are beginning to curtail their wafer input plans with foundries. This phenomenon of order cancellations is occurring simultaneously in 8-inch and 12-inch fabs at nodes including 0.1X μm, 90/55 nm, and 40/28 nm. Not even the advanced 7/6 nm processes are immune.

MediaTek today announced the Dimensity 9000+, an enhancement to the company's top-of-the-line 5G smartphone chipset. This new high-end offering delivers a boost in performance over the Dimensity 9000 to make the next generation of flagship smartphones even more powerful and efficient.

The new Dimensity 9000+ system-on-chip (SoC) integrates Arm's v9 CPU architecture with a 4 nm octa-core process, combining one ultra-Cortex-X2 core operating at up to 3.20 GHz (compared to 3.05 GHz with the Dimensity 9000) with three super Cortex-A710 cores and four efficiency Cortex-A510 cores. The advanced CPU architecture and Arm Mali-G710 MC10 graphics processor built into the new chipset provide more than a 5% boost in CPU performance and more than 10% improvement in GPU performance.

According to TrendForce research, although demand for consumer electronics remains weak, structural growth demand in the semiconductor industry including for servers, high-performance computing, automotive, and industrial equipment has not flagged, becoming a key driver for medium and long term foundry growth. At the same time, due to robust wafer production at higher pricing in 1Q22, quarterly output value hit a new high for the 11th consecutive quarter, reaching US$31.96 billion, 8.2% QoQ, marginally less than the previous quarter. In terms of ranking, the biggest change is Nexchip surpassed Tower at the ninth position.

TSMC's across the board wafer hikes in 4Q21 on batches primarily produced in 1Q22 coupled with sustained strong demand for high-performance computing and better foreign currency exchange rates pushed TSMC's 1Q22 revenue to $17.53 billion, up 11.3% QoQ. Quarterly revenue growth by node was generally around 10% and the 7/6 nm and 16/12 nm processes posted the highest growth rate due to small expansions in production. The only instance of revenue decline came at the 5/4 nm process due to Apple's iPhone 13 entering the off season for production stocking.

AMD in its 2022 Financial Analyst Day presentation announced the codename for the second generation of Ryzen desktop processors for Socket AM5, which is "Granite Ridge." A successor to the Ryzen 7000 "Raphael," the next-generation "Granite Ridge" processor will incorporate the "Zen 5" CPU microarchitecture, with its CPU complex dies (CCDs) built on the 4 nm silicon fabrication node. "Zen 5" will feature several core-level designs as detailed in our older article, including a redesigned front-end with greater parallelism, which should indicate a much large execution stage. The architecture could also incorporate AI/ML performance enhancements as AMD taps into Xilinx IP to add more fixed-function hardware backing the AI/ML capabilities of its processors.

The "Zen 5" microarchitecture makes its client debut with Ryzen "Granite Ridge," and server debut with EPYC "Turin." It's being speculated that AMD could give "Turin" a round of CPU core-count increases, while retaining the same SP5 infrastructure; which means we could see either smaller CCDs, or higher core-count per CCD with "Zen 5." Much like "Raphael," the next-gen "Granite Ridge" will be a series of high core-count desktop processors that will feature a functional iGPU that's good enough for desktop/productivity, though not gaming. AMD confirmed that it doesn't see "Raphael" as an APU, and that its definition of an "APU" is a processor with a large iGPU that's capable of gaming. The company's next such APU will be "Phoenix Point."