Excelero, a Tel Aviv-based provider of high-performance software-defined storage, is now a part of NVIDIA. The company's team of engineers—including its seasoned co-founders with decades of experience in HPC, storage and networking—bring deep expertise in the block storage that large businesses use in storage-area networks.

Now their mission is to help expand support for block storage in our enterprise software stack such as clusters for high performance computing. Block storage also has an important role to play inside the DOCA software framework that runs on our DPUs.

Marvell (NASDAQ: MRVL) today announced the industry's first 800 Gbps or 8x 100 Gbps multimode platform solution, that enables data center infrastructure to achieve dramatically higher speeds for short-reach optical modules and Active Optical Cable (AOC) applications. As artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications continue to drive greater bandwidth requirements, cloud-optimized solutions are needed that can bring lower power, latency and cost to short-range data center interconnections. The new 800G platform, which includes Marvell's PAM4 DSP with a multimode transimpedance amplifier (TIA) and Driver, enables faster data center speeds scaling to 800 Gbps, using conventional cost-effective vertical-cavity surface-emitting laser (VCSEL) technology while accelerating time-to-market with plug-and-play deployment.

Today's data centers are packed with equipment utilizing optical modules or AOCs connected by multimode optical fiber optimized for communication over short distances within data centers. This 100G per lane multimode fiber provides cost-effective, low-power, short-reach connectivity. To support multi-gigabit transmissions, multimode architectures often use VCSEL transmitters, which offer the cost benefits of reliability, power efficiency and easy deployment.

GIGABYTE Technology, today introduced two new liquid cooled HPC and AI training servers, G262-ZL0 and G492-ZL2, that can push the NVIDIA HGX A100 accelerators and AMD EPYC 7003 processors to the limit with enterprise-grade liquid cooling. To prevent overheating and server downtime in a compute dense data center, GIGABYTE worked with CoolIT Systems to develop a thermal solution that uses direct-liquid cooling to balance optimal performance, high availability, and efficient cooling.

For innovators and researchers in HPC, AI, and data analytics that demand a high level of CPU and GPU compute the new servers are built for the top-tier AMD EPYC 7003 processor and GPU baseboard, NVIDIA HGX A100 80 GB accelerator. Combining components well-designed for performance and efficiency enables much faster insights and results, which users appreciate while reaping the benefits of the value and lower TCO.

During the International Solid-State Circuits Conference (ISSCC) 2022, Intel gave us a more significant look at its upcoming Ponte Vecchio HPC accelerator and how it operates. So far, Intel convinced us that the company created Ponte Vecchio out of 47 tiles glued together in one package. However, the ISSCC presentation shows that the accelerator is structured rather interestingly. There are 63 tiles in total, where 16 are reserved for compute, eight are used for RAMBO cache, two are Foveros base tiles, two represent Xe-Link tiles, eight are HBM2E tiles, and EMIB connection takes up 11 tiles. This totals for about 47 tiles. However, an additional 16 thermal tiles used in Ponte Vecchio regulate the massive TDP output of this accelerator.

What is interesting is that Intel gave away details of the RAMBO cache. This novel SRAM technology uses four banks of 3.75 MB groups total of 15 MB per tile. They are connected to the fabric at 1.3 TB/s connection per chip. In contrast, compute tiles are connected at 2.6 TB/s speeds to the chip fabric. With eight RAMBO cache tiles, we get an additional 120 MB SRAM present. The base tile is a 646 mm² die manufactured in Intel 7 semiconductor process and contains 17 layers. It includes a memory controller, the Fully Integrated Voltage Regulators (FIVR), power management, 16-lane PCIe 5.0 connection, and CXL interface. The entire area of Ponte Vecchio is rather impressive, as 47 active tiles take up 2,330 mm², whereas when we include thermal dies, the total area jumps to 3,100 mm². And, of course, the entire package is much larger at 4,844 mm², connected to the system with 4,468 pins.

At Intel's 2022 Investor Meeting, Chief Executive Officer Pat Gelsinger and Intel's business leaders outlined key elements of the company's strategy and path for long-term growth. Intel's long-term plans will capitalize on transformative growth during an era of unprecedented demand for semiconductors. Among the presentations, Intel announced product roadmaps across its major business units and key execution milestones, including: Accelerated Computing Systems and Graphics, Intel Foundry Services, Software and Advanced Technology, Network and Edge, Technology Development, More: For more from Intel's Investor Meeting 2022, including the presentations and news, please visit the Intel Newsroom and Intel.com's Investor Meeting site.

congatec welcomes the publication of the COM-HPC Carrier Board Design Guide by the PCI Industrial Computer Manufacturers Group (PICMG) with the launch of a fully specification compliant ecosystem for engineers of COM-HPC Client and Server module based designs. From now on, engineers can dive right in and start to develop fully compliant designs by picking their appropriate Computer-on-Module, add a COM-HPC Server or COM-HPC Client evaluation carrier and appropriate cooling solution, install their application and run programming, debugging and test routines on this new high-performance embedded computing standard.

The congatec COM-HPC ecosystem is fully compliant to the entire range of new PICMG COM-HPC specifications, namely the COM-HPC Module Base Specification, the brand new Carrier Board Design Guide, the Embedded EEPROM specification and the Platform Management Interface specification. Supported by all leading embedded computing vendors, including congatec, this set of PICMG standards offers engineers the benefits of best in class design security.

AMD (NASDAQ: AMD) today announced that AMD EPYC processors will power the new C2D virtual machine offering from Google Cloud, bringing customers strong performance and compute power for high-performance (HPC) memory-bound workloads in areas like electronic design automation (EDA) and computational fluid dynamics (CFD). This announcement continues the momentum for AMD EPYC processors, marking the third family of instances powered by 3rd Gen EPYC processors at Google Cloud, joining the T2D and N2D instances.

With the help of AMD EPYC processors and its high core density, the C2D VMs will provide the largest VM sizes within compute optimized family at Google Cloud. As well, because of the EPYC processor's performance for compute focused workloads, Google Cloud showcased the C2D VMs can provide up to 30 percent better performance for targeted workloads compared to previous generation EPYC based VMs at a comparable size.

The European High Performance Computing Joint Undertaking (EuroHPC JU) has launched 3 new research and innovation projects. The projects aim to bring the EU and its partners in the EuroHPC JU closer to developing independent microprocessor and HPC technology and advance a sovereign European HPC ecosystem. The European Processor Initiative (EPI SGA2), The European PILOT and the European Pilot for Exascale (EUPEX) are interlinked projects and an important milestone towards a more autonomous European supply chain for digital technologies and specifically HPC.

With joint investments of €140 million from the European Union (EU) and the EuroHPC JU Participating States, the three projects will carry out research and innovation activities to contribute to the overarching goal of securing European autonomy and sovereignty in HPC components and technologies, especially in anticipation of the European exascale supercomputers.

Lenovo today unveiled Lenovo TruScale High Performance Computing as a Service (HPCaaS), delivering the power of supercomputing to organizations of all sizes through a cloud-like experience. The new high performance computing (HPC) as-a-service (aaS) offering expands Lenovo's everything as-a-service TruScale portfolio and enables HPC customers to access greater supercomputing resources, driving a faster time to answer for researchers working on solving humanity's greatest challenges.

Cloud-based HPC is the fastest growing segment of high-performance computing, and on-demand resource consumption provides more efficient and scalable computing resources to meet workload requirements. The typical HPC cluster runs at nearly full capacity, with rapidly increasing demands for compute and storage cycles and little room for additional workloads. Lenovo TruScale HPCaaS delivers additional capacity that allows research institutions to better compete for grants while gaining faster insights. The technology provides rack-to-cloud level solutions that are critical to drive innovation across multiple sectors, including academia, pharma, manufacturing and healthcare.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of the next version of its High Bandwidth Memory (HBM) DRAM standard: JESD238 HBM3, available for download from the JEDEC website. HBM3 is an innovative approach to raising the data processing rate used in applications where higher bandwidth, lower power consumption and capacity per area are essential to a solution's market success, including graphics processing and high-performance computing and servers.

Tachyum today announced that it was selected by the Slovak Republic to participate in the latest submission for the Important Projects of Common European Interest (IPCEI), to develop Prodigy 2 for HPC/AI. Prodigy 2 for HPC/AI will enable 1 AI Zettaflop and more than 10 DP Exaflops computers to support superhuman brain-scale computing by 2024 for under €1B. As part of this selection, Tachyum could receive a 49 million Euro grant to accelerate a second-generation of its Tachyum Prodigy processor for HPC/AI in a 3-nanometer process.

The IPCEI program can make a very important contribution to sustainable economic growth, jobs, competitiveness and resilience for industry and the economy in the European Union. IPCEI will strengthen the EU's open strategic autonomy by enabling breakthrough innovation and infrastructure projects through cross-border cooperation and with positive spill-over effects on the internal market and society as a whole.

Intel is reportedly looking to disrupt the cryptocurrency mining hardware business with fixed-function ASICs that either outperform GPUs, or end up with lower enough performance/Watt or performance/Dollar to take make GPUs unviable as a mining hardware option. The company is planning to unveil its first such product, codenamed "Bonanza Mine," an ASIC purpose-built for Bitcoin mining.

Since it's an ASIC, "Bonanza Mine" doesn't appear to be a re-purposed Xe-HPC processor, or even an FPGA that's been programmed to mine Bitcoin. It's a purpose-built piece of silicon. Intel will unveil "Bonanza Mine" at the 2022 ISSCC Conference. It describes the chip as being an "ultra low-voltage energy-efficient Bitcoin mining ASIC," putting power-guzzling GPUs on notice. If Intel can clinch Bitcoin with "Bonanza Lake," designing ASICs for other cryptocurrencies is straightforward. With demand from crypto-miners slashed, graphics cards will see a tremendous fall in value, forcing scalpers to cut prices.

Infortrend Technology, Inc. (TWSE: 2495), the industry-leading enterprise storage provider, satisfies requirements of high throughput and fast response time for high-performance computing (HPC), media post-production, and medical PACS applications ­— with EonStor CS NVMe SSD storage delivering 13 GB/s throughput in a 3-node cluster, and performance linearly increases in a scale-out mode.

Today's HPC applications perform computationally intensive operations with billions of files across multiple resources of different nature at PB scale. Storage for HPC, therefore, must be able to simultaneously support multiple random and sequential IO workloads of different sizes. Otherwise, it can extensively delay the HPC application output and the company's success. EonStor CS NVMe SSD storage, CS 4014U, effectively eliminates these concerns and guarantees fast response time, satisfying various types of IO profiles.\

congatec - a leading vendor of embedded and edge computing technology - introduces the 12th Generation Intel Core mobile and desktop processors (formerly code named Alder Lake) on 10 new COM-HPC and COM Express Computer-on-Modules. Featuring the latest high performance cores from Intel, the new modules in COM-HPC Size A and C as well as COM Express Type 6 form factors offer major performance gains and improvements for the world of embedded and edge computing systems. Most impressive is the fact that engineers can now leverage Intel's innovative performance hybrid architecture. Offering of up to 14 cores/20 threads on BGA and 16 cores/24 threads on desktop variants (LGA mounted), 12th Gen Intel Core processors provide a quantum leap [1] in multitasking and scalability levels. Next-gen IoT and edge applications benefit from up to 6 or 8 (BGA/LGA) optimized Performance-cores (P-cores) plus up to 8 low power Efficient-cores (E-cores) and DDR5 memory support to accelerate multithreaded applications and execute background tasks more efficiently.

Intel is reportedly disabling the rudimentary AVX-512 instruction-set support on its 12th Gen Core "Alder Lake" processors using a firmware/ME update, reports Igor's Lab. Intel does not advertise AVX-512 for Alder Lake, even though the instruction-set was much publicized for a couple of its past-generation client-segment chips, namely 11th Gen Rocket Lake, and 10th Gen Cascade Lake-X HEDT processors. The company will likely make AVX-512 a feature that sets apart its next-gen HEDT processors derived from Sapphire Rapids, its upcoming enterprise microarchitecture.

AVX-512 is technically not advertised for Alder Lake, but software that calls for these instructions can utilize them on certain 12th Gen Core processors, when paired with older versions of the Intel ME firmware. The ME version Intel releases to OEMs and motherboard vendors alongside its upcoming 65 W Core desktop processors, and the Alder Lake-P mobile processors, will prevent AVX-512 from being exposed to the software. Intel's reason to deprecate what little client-relevant AVX-512 instructions it had for Core processors, could have do with energy efficiency, as much as lukewarm reception from client software developers. The instruction is more relevant to the HPC and cloud-computing markets.Many Thanks to TheoneandonlyMrK for the tip.

Leading global memory provider TEAMGROUP has been actively expanding in the industrial control field for many years. With the arrival of the new DDR5 generation, the company today announced the DDR5 ECC DIMM and DDR5 R-DIMM Industrial Server Memory modules. In recent years, there has been a steady growth in AI and HPC data applications, driving memory specifications toward higher capacities and greater performance. To meet this rising demand, TEAMGROUP has created multiple solutions with its latest innovations of DDR5 industrial server memory.

Its next-gen server memory modules can reach speeds of 6,400 MT/s, come with a maximum capacity of up to 128 GB, and operate at 1.1 V, resulting in lower overall power consumption. The memory also features two innovations in its power supply architecture and channel architecture. The new power supply architecture shifts power management from the motherboard to the DIMM itself, enhancing signal integrity and resistance to interference. The channel architecture is updated with two independent sub-channels per memory module (DIMM) to significantly improve memory access efficiency and meet the elevated demands of smart platform applications.

Innodisk has announced its all-new EGPL-T101 M.2 2280 10GbE LAN module, the first 10GbE LAN designed in M.2 form factor, features flexible integration and excellent compatibility with existing network infrastructure for crucial backward compatibility. Looking into the booming markets and scenarios ranging from surveillance to gaming, networking, and industrial uses, the growing demand for high-speed LAN solutions is promising. Additionally, interference issues are also occurring more often as the size of the PCIe form factor cannot fit in the smaller design of IPC platforms nowadays. Being the leading global provider of industrial embedded flash and memory, Innodisk is introducing the first M.2 10GbE LAN module designed to meet the demand for increased speed and reduced size, high-speed LAN solutions.

Innodisk's EGPL-T101 is the first M.2 2280-to-single 10GbE Base-T Ethernet module which is also the smallest 10GbE expansion solution available today and ten times faster than standard Ethernet. By supporting PCI Express Gen 3x2, the EGPL-T101 module can provide sufficient bandwidth for one 10GbE LAN port suitable for server and industrial applications' high-speed network demands.

The National Renewable Energy Laboratory (NREL) has selected Hewlett Packard Enterprise (HPE) to build its third-generation, high performance computing (HPC) system, called Kestrel. Named for a falcon with keen eyesight and intelligence, Kestrel's moniker is apropos for its mission—to rapidly advance the U.S. Department of Energy's (DOE's) energy research and development (R&D) efforts to deliver transformative energy solutions to the entire United States.

Installation of the new system will begin in the fall of 2022 in NREL's Energy Systems Integration Facility (ESIF) data center. Kestrel will complement the laboratory's current supercomputer, Eagle, during the transition. When completed—in early 2023—Kestrel will accelerate energy efficiency and renewable energy research at a pace and scale more than five times greater than Eagle, with approximately 44 petaflops of computing power.

Xilinx, Inc., the leader in adaptive computing, today at the SC21 supercomputing conference introduced the Alveo U55C data center accelerator card and a new standards-based, API-driven clustering solution for deploying FPGAs at massive scale. The Alveo U55C accelerator brings superior performance-per-watt to high performance computing (HPC) and database workloads and easily scales through the Xilinx HPC clustering solution.

Purpose-built for HPC and big data workloads, the new Alveo U55C card is the company's most powerful Alveo accelerator card ever, offering the highest compute density and HBM capacity in the Alveo accelerator portfolio. Together with the new Xilinx RoCE v2-based clustering solution, a broad spectrum of customers with large-scale compute workloads can now implement powerful FPGA-based HPC clustering using their existing data center infrastructure and network.

The 58th annual edition of the TOP500 saw little change in the Top10. The Microsoft Azure system called Voyager-EUS2 was the only machine to shake up the top spots, claiming No. 10. Based on an AMD EPYC processor with 48 cores and 2.45GHz working together with an NVIDIA A100 GPU and 80 GB of memory, Voyager-EUS2 also utilizes a Mellanox HDR Infiniband for data transfer.

While there were no other changes to the positions of the systems in the Top10, Perlmutter at NERSC improved its performance to 70.9 Pflop/s. Housed at the Lawrence Berkeley National Laboratory, Perlmutter's increased performance couldn't move it from its previously held No. 5 spot.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it has developed Hybrid-Substrate Cube (H-Cube) technology, its latest 2.5D packaging solution specialized for semiconductors for HPC, AI, data center, and network products that require high-performance and large-area packaging technology.

"H-Cube solution, which is jointly developed with Samsung Electro-mechanics (SEMCO) and Amkor Technology, is suited to high-performance semiconductors that need to integrate a large number of silicon dies," said Moonsoo Kang, senior vice president and Head of Foundry Market Strategy Team at Samsung Electronics. "By expanding and enriching the foundry ecosystem, we will provide various package solutions to find a breakthrough in the challenges our customers are facing."

NVIDIA today announced NVIDIA Quantum-2, the next generation of its InfiniBand networking platform, which offers the extreme performance, broad accessibility and strong security needed by cloud computing providers and supercomputing centers.

The most advanced end-to-end networking platform ever built, NVIDIA Quantum-2 is a 400 Gbps InfiniBand networking platform that consists of the NVIDIA Quantum-2 switch, the ConnectX-7 network adapter, the BlueField-3 data processing unit (DPU) and all the software that supports the new architecture.

AMD today announced the new AMD Instinct MI200 series accelerators, the first exascale-class GPU accelerators. AMD Instinct MI200 series accelerators includes the world's fastest high performance computing (HPC) and artificial intelligence (AI) accelerator,1 the AMD Instinct MI250X.

Built on AMD CDNA 2 architecture, AMD Instinct MI200 series accelerators deliver leading application performance for a broad set of HPC workloads. The AMD Instinct MI250X accelerator provides up to 4.9X better performance than competitive accelerators for double precision (FP64) HPC applications and surpasses 380 teraflops of peak theoretical half-precision (FP16) for AI workloads to enable disruptive approaches in further accelerating data-driven research.

AMD today announced the debut of its 6 nm CDNA2 (Compute-DNA) architecture in the form of the MI200 family. The new, dual-GPU chiplet accelerator aims to lead AMD into a new era of High Performance Computing (HPC) applications, the high margin territory it needs to compete in for continued, sustainable growth. To that end, AMD has further improved on a matured, compute-oriented architecture born with Graphics Core Next (GCN) - and managed to improve performance while reducing total die size compared to its MI100 family.

SiPearl, the designer of the high computing power and low consumption microprocessor that will be the heart of European supercomputers, has entered into a partnership with Intel in order to offer a common offer dedicated to the first exascale supercomputers in Europe. This partnership will offer their European customers the possibility of combining Rhea, the high computing power and low consumption microprocessor developed by SiPearl, with Intel's Ponte Vecchio accelerator, thus creating a high performance computing node that will promote the deployment of the exascale supercomputing in Europe.

To enable this powerful combination, SiPearl plans to use and optimize for its Rhea microprocessor the open and unified programming interface, oneAPI, created by Intel. Using this single solution across the entire heterogeneous compute node, consisting of Rhea and Ponte Vecchio, will increase developer productivity and application performance.