AMD at its Computex event shed some light on its IP partnership with Samsung. We already knew this was going to be a closer collaboration than most IP licensing deals, as AMD themselves announced this would be a semi-custom solution designed between both companies. AMD CEO Lisa Su described the technology to be embedded in the upcoming Samsung Exynos SoC as being based on RDNA2 - but this likely is just a marketing and clarity perspective on AMD's technology being implemented, since between the design of RDNA2 and the announcement of the Samsung partnership a lot of water has necessarily run under AMD's graphics IP bridge.

Lisa Su did however confirm that two key RDNA2 technologies will find their way into Samsung's Exynos: Variable Rate Shading (VRS) and Raytracing. This isn't he first time VRS has made an appearance on a mobile SoC - it's already been implemented by Qualcomm in the Adreno 660 GPU (part of the Snapdragon 888 SoC design). However, Raytracing does seem to be a first for the SoC market, and Samsung might just edge out competition in its time to market with this technology. more details will certainly be shared as we get closer to the fabled AMD-partnered Exynos release.

Today, we have talked about AMD's upcoming Raphael lineup of processors in the article you can find here. However, it seems like the number of leaks on AMD's plans just keeps getting greater. Thanks to the "itacg" on Weibo, we have learned that AMD's Ryzen 8000 desktop series of processors are reportedly codenamed as Granite Ridge. This new codename denotes the Zen 5 based processors, manufactured on TSMC's 3 nm (N3) node. Another piece of information is that AMD's Ryzen 8000 series APUs are allegedly called Strix Point, and they also use the 3 nm technology, along with a combination of Zen 5 and Zen 4 core design IPs. We are not sure how this exactly works out, so we have to wait to find out more.

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced immediate availability of Cadence IP supporting the PCI Express (PCIe ) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022. Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence's PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs with accelerated time to market.

The Cadence IP for PCIe 5.0 architecture offers a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss. Leveraging Cadence's existing N7/N6 silicon validated offering, the N5 design provides a full 512GT/s (gigatransfers per second) power-optimized solution across the full range of operating conditions with a single clock lane.

AMD in 2020 set out on an ambitious project to develop Wi-Fi modules under its own marquee. This was catalyzed in part by the company's Ryzen PRO line of mobile processors, to better compete with Intel's Core vPro processors, which included Intel's own vPro-ready WLAN modules as part of a package to notebook OEMs. Come 2021, and AMD's module is ready, and is debuting with a handheld game console.

The new AMD RZ608 WLAN module is cutting-edge, in supporting Wi-Fi 6E (802.11ax over 6 GHz) in addition to a plethora of older Wi-Fi standards; and Bluetooth 5.2. 6 months seem like an awfully short amount of time for AMD to whip up a WLAN product portfolio from scratch, especially with the IP tangles involved. The company instead chose to partner with MediaTek, which has access to all the IP needed to develop such a product. The WLAN PHY appears to be a MediaTek design, specifically based on the MT7921K chip. We'll hear a lot more about the RZ608, as it might start showing up in notebooks powered by Ryzen 5000 "Cezanne" processors. It remains to be seen if the chip makes it to desktop platforms, too.

The demands of data center workloads and internet traffic are growing exponentially, and new solutions are needed to keep up with these demands while reducing the current and anticipated growth of power consumption. But the variety of workloads and applications being run today means the traditional one-size-fits all approach to computing is not the answer. The industry demands flexibility; design freedom to achieve the right level of compute for the right application.

As Moore's Law comes to an end, solution providers are seeking specialized processing. Enabling specialized processing has been a focal point since the inception of our Neoverse line of platforms, and we expect these latest additions to accelerate this trend.

Video streaming is looking a bit like magic. The uploader sends a video to one platform in one resolution and encoding format, while the viewer requests a video in a specific resolution and encoding format used by the device the video is streamed on. YouTube knows this best, as it represents the world's largest video platform with over 2 billion users visiting the platform each month. That takes a massive load on the server infrastructure over at Google's data centers that host the service. There is about 500 hours worth of video content uploaded to the platform every minute, and regular hardware isn't being enough anymore to handle everything.

That is why YouTube has developed custom chips, ASICs, that are called VCUs or Video (trans)Coding Units. In Google data centers, there is a large problem with transcoding. Each video needs to adapt to the streaming platform and desired specifications, and doing that on regular hardware is a problem. By using ASIC devices, such as VCUs, Google can keep up with the demand and deliver the best possible quality. Codenamed Argos, the chip can deliver 20-33x improvement in efficiency compared to the regular server platform. In data centers, the VCU is implemented as a regular PCIe card, with two chips under the heatsinks.

OpenFive, a leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the successful tape out of a high-performance SoC on TSMC's N5 process, with integrated IP solutions targeted for cutting edge High Performance Computing (HPC)/AI, networking, and storage solutions.

The SoC features an OpenFive High Bandwidth Memory (HBM3) IP subsystem and D2D I/Os, as well as a SiFive E76 32-bit CPU core. The HBM3 interface supports 7.2 Gbps speeds allowing high throughput memories to feed domain-specific accelerators in compute-intensive applications including HPC, AI, Networking, and Storage. OpenFive's low-power, low-latency, and highly scalable D2D interface technology allows for expanding compute performance by connecting multiple dice together using an organic substrate or a silicon interposer in a 2.5D package.

NVIDIA today announced its first data center CPU, an Arm-based processor that will deliver 10x the performance of today's fastest servers on the most complex AI and high performance computing workloads.

The result of more than 10,000 engineering years of work, the NVIDIA Grace CPU is designed to address the computing requirements for the world's most advanced applications—including natural language processing, recommender systems and AI supercomputing—that analyze enormous datasets requiring both ultra-fast compute performance and massive memory. It combines energy-efficient Arm CPU cores with an innovative low-power memory subsystem to deliver high performance with great efficiency.

Amazon Games today announced it has opened a new game development studio in Montreal, Canada. The Montreal studio, which joins Amazon Games development studios in Seattle, Orange County, and San Diego, will focus on creating original AAA games. Amazon Games is actively hiring to build out the talented team, with a variety of roles opening.

The studio's founding members include industry veterans Luc Bouchard (head of production), Xavier Marquis (creative director), Alexandre Remy (head of product), and Romain Rimokh (content director), who most recently worked as the core team behind the tactical shooter Rainbow Six Siege, which now has more than 70 million players since its launch. The studio's first project will be an online multiplayer title based on new IP.

Synopsys, Inc. today announced the industry's first complete IP solution for the PCI Express (PCIe ) 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip (SoC) designs. Built on Synopsys' widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. Synopsys' complete IP solution addresses evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1 GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

Silver Rain Games, an interactive entertainment development studio co-founded by BAFTA-nominated actor and producer Abubakar Salim has signed a major deal with Electronic Arts Inc. (NASDAQ:EA) EA Originals Label, which is dedicated to elevating bold independent studios. EA Originals will provide funding for the up-and coming studio's unannounced IP, as well as guidance and support in the team's journey to bring a fresh perspective to games and to the industry.

Silver Rain, which is based in the U.K., was co-founded in December 2019 by Salim, best known for his role on HBO's hit show Raised by Wolves, alongside Melissa Phillips, who will lead as Head of Studio, who previously worked as the BAFTA Games Programme manager on BAFTA Games programs and events. The company was launched with the intent to generate thought-provoking and innovative games and content across different mediums of entertainment. Since its inception late last year, the studio has quickly grown to approximately 20 staff members, who all currently work remotely.

In September of last year, NVIDIA has officially announced that the current industry rumor about its big acquisition was true. The company has announced that it is acquiring Arm Limited from the Softbank Group. Paying as much as $40 billion for the purchase, NVIDIA is gaining access to the complete company, along with its extensive portfolio of IP and knowledge. That means that NVIDIA is not essentially a holder of the Arm ISA, which is the most dominant ISA within mobile processors. Such a deal, however, is a bit hard to process without some troubles popping up along the way. As Arm held a neutral position as IP provider, NVIDIA is expected to remain as such, and the company even promised to stay true to that.

However, not everything is going as planned. Before completing the acquisition process, NVIDIA must first comply with regulators from all around the world, including the US, UK, EU, and China. If any objections raise within those regions, they are to be interrogated. Today, Google, Microsoft, and Qualcomm have objected that NVIDIA's Arm acquisition is hurting the market and are urging antitrust officials to intervene. Mentioned companies believe that NVIDIA's move is hurting the market and the company could limit its competitors from accessing the IP, thus breaking Arm's neutral position as an IP provider. NVIDIA has made statements that Arm will remain in such a position, however, the skepticism of the mentioned companies is slowing the merger. Now all that remains is to see how the conflicted companies solve their worries.

Valve has recently been ordered to pay 4 million USD in damages after they knowingly infringed on patents owned by Ironburg Inventions with the Steam Controller rear grip button design. Ironburg Inventions is the IP-holding arm of controller manufacturer SCUF who was acquired by Corsair in late 2019. Valve was warned by Ironburg Inventions in 2014 that their Steam Controller infringed on their patent relating to rear-side control surfaces. Valve ignored the warning and went on to produce 1.6 million units before discontinuing the device in 2019. The Jury awarded Ironburg Inventions 4 million USD in damages and found that Valve willfully infringed on Ironberg's patents which opens them up to further litigation. Corsair has published a statement on the case which can be found below.

AMD is always in development mode and just when they launch a new product, the company is always gearing up for the next-generation of devices. Just a few months ago, back in November, AMD has launched its Zen 3 core, and today we get to hear about the next steps that the company is taking to stay competitive and grow its product portfolio. In the AnandTech interview with Dr. Lisa Su, and The Street interview with Rick Bergman, the EVP of AMD's Computing and Graphics Business Group, we have gathered information about AMD's plans for Zen 4 core development and RDNA 3 performance target.

Starting with Zen 4, AMD plans to migrate to the AM5 platform, bringing the new DDR5 and USB 4.0 protocols. The current aim of Zen 4 is to be extremely competitive among competing products and to bring many IPC improvements. Just like Zen 3 used many small advances in cache structures, branch prediction, and pipelines, Zen 4 is aiming to achieve a similar thing with its debut. The state of x86 architecture offers little room for improvement, however, when the advancement is done in many places it adds up quite well, as we could see with 19% IPC improvement of Zen 3 over the previous generation Zen 2 core. As the new core will use TSMC's advanced 5 nm process, there is a possibility to have even more cores found inside CCX/CCD complexes. We are expecting to see Zen 4 sometime close to the end of 2021.

Samsung today at its Exynos 2100 launch event announced that its labor with AMD to integrate the company's RDNA graphics architecture onto Exynos chips has born fruit. It's unclear today on which set of technology this integration is bound to - whether RDNA, RDNA 2, or a combination of both - and actual products will only hit shelves by the end of 2021 and beginning of 2022.

Samsung has announced that the design-in for AMD's RDNA platform into the company's flagship Exynos products for the 2021-2022 timeframe have been successful, and that the first iteration of the design will see the light of day on the upcoming Exynos 2100. The collaboration has reportedly resulted in very good performance values obtained from their IP merger in May 2020. It seems we have a few months to look towards to before we see a Galaxy phone with an RDNA-powered engraving, though.

AMD today announced several senior leadership promotions in support of the company's long-term growth goals. "Our high-performance products and long-term roadmaps have placed AMD on a significant growth trajectory," said Dr. Lisa Su, AMD president and CEO. "Aligning and expanding our senior leadership team around our highest-priority growth opportunities will continue the momentum we have built across our business in 2021 and beyond."AMD announced two executive vice president promotions:

• Darren Grasby to executive vice president and Chief Sales Officer, responsible for driving adoption of AMD products and delivering a world-class customer experience.
• Devinder Kumar to executive vice president and Chief Financial Officer, responsible for continued strengthening of the company's financial profile.

Intel is familiar with chip manufacturing problems since the company started the development of a 10 nm silicon semiconductor node. The latest node is coming years late with many IPs getting held back thanks to the inability of the company to produce it. All of Intel's chip production was historically happening at Intel's facilities, however, given the fact that the demand for 14 nm products is exceeding production capability, the company was forced to turn to external foundries like TSMC to compensate for its lack of capacity. TSMC has a contract with Intel to produce silicon for things like chipsets, which is offloading a lot of capacity for the company. Today, thanks to the exclusive information obtained by Reuters, we have information that a certain New York hedge fund, Third Point LLC, is advising the company about the future of its manufacturing.

The hedge fund is reportedly accounting for about one billion USD worth of assets in Intel, thus making it a huge and one influencing shareholder. The Third Point Chief Executive Daniel Loeb wrote a letter to Intel Chairman Omar Ishrak to take immediate action to boost the company's state as a major provider of processors for PCs and data centers. The company has noted that Intel needs to outsource more of its chip production to satisfy the market needs, so it can stay competitive with the industry. The poor performance of Intel has reflected on the company shares, which have declined about 21% this year. This has awoken the shareholders and now we see that they are demanding more aggressiveness from the company and a plan to outsource more of the chip production to partner foundries like TSMC and Samsung. It remains to be seen how Intel responds and what changes are to take place.

Tachyum Inc. today announced that it is signing early adopter customers for the software emulation system for its Prodigy Universal Processor, customers may begin the process of native software development (i.e. using Prodigy Instruction Set Architecture) and porting applications to run on Prodigy. Prodigy software emulation systems will be available at the end of January 2021.

Customers and partners can use Prodigy's software emulation for evaluation, development and debug, and with it, they can begin to transition existing applications that demand high performance and low power to run optimally on Prodigy processors. Pre-built systems include a Prodigy emulator, native Linux, toolchains, compilers, user mode applications, x86, ARM and RISC-V emulators. Software updates will be issued as needed.

QNAP Systems, Inc., a leading computing, networking and storage solution innovator, today announced the desktop smart edge PoE Switch - QGD-3014-16PT. With sixteen 30-watt Gigabit PoE ports, two 2.5GbE host management ports, Intel Celeron J4125 quad-core 2.0 GHz processor, and four 3.5-inch SATA drive bays, the QGD-3014-16PT supports QVR Pro, HBS 3 and QuWAN SD-WAN to integrate surveillance deployment, video storage computing, and multi-site remote management to offer SMBs innovative intelligent IP surveillance infrastructure and remote backup solutions.
"Expanding multi-site surveillance networks can be costly and involve large amounts of equipment with low transmission efficiency between multiple remote devices - not to mention the complexities involved in deployment and management. " said Daniel Hsieh, QNAP Product Manager, adding, "the QGD-3014-16PT desktop Smart Edge PoE Switch integrates PoE, surveillance capabilities, and data backup management to simplify these requirements and increase the transmission and backup efficiency of surveillance videos."

Today, Amazon Web Services, Inc. (AWS), an Amazon.com, Inc. company, announced that Arm, a global leader in semiconductor design and silicon intellectual property development and licensing, will leverage AWS for its cloud use, including the vast majority of its electronic design automation (EDA) workloads. Arm is migrating EDA workloads to AWS, leveraging AWS Graviton2-based instances (powered by Arm Neoverse cores), and leading the way for transformation of the semiconductor industry, which has traditionally used on-premises data centers for the computationally intensive work of verifying semiconductor designs.

To carry out verification more efficiently, Arm uses the cloud to run simulations of real-world compute scenarios, taking advantage of AWS's virtually unlimited storage and high-performance computing infrastructure to scale the number of simulations it can run in parallel. Since beginning its AWS cloud migration, Arm has realized a 6x improvement in performance time for EDA workflows on AWS. In addition, by running telemetry (the collection and integration of data from remote sources) and analysis on AWS, Arm is generating more powerful engineering, business, and operational insights that help increase workflow efficiency and optimize costs and resources across the company. Arm ultimately plans to reduce its global datacenter footprint by at least 45% and its on-premises compute by 80% as it completes its migration to AWS.

Researchers at the University of California, Berkeley in 2010 have started an interesting project. They created a goal to develop a new RISC-like Instruction Set Architecture that is simple and efficient while being open-source and royalty-free. Born out of that research was RISC-V ISA, the fifth iteration of Reduced Instruction Set Computing (RISC) ideology. Over the years, the RISC-V ISA has become more common, and today, many companies are using it to design their processors and release new designs every day. One of those companies is Micro Magic Inc., a provider of silicon design tools, IP, and design services. The company has developed a RISC-V processor that is rather interesting.

Apart from the RISC-V ISA, the processor has an interesting feature. It runs at the whopping 5 GHz frequency, a clock speed unseen on the RISC-V chips before, at the power consumption of a mere one (yes that is 1) Watt. The chip ran at just 1.1 Volts, which means that a very low current needs to be supplied to the chip so it can achieve the 5 GHz mark. If you are wondering about performance, well the numbers show that at 5 GHz, the CPU can produce a score of 13000 CoreMarks. However, that is not the company's highest-performance RISC-V core. In yesterday's PR, Micro Magic published that their top-end design can achieve 110000 CoreMarks/Watt, so we are waiting to hear more details about it.

During its Q3 earnings call, Samsung Electronics has provided everyone with an update on its foundry and node production development. In the past year or so, Samsung's foundry has been a producer of a 7 nm LPP (Low Power Performance) node as its smallest node. That is now changed as Samsung has started the production of the 5 nm LPE (Low Power Early) semiconductor manufacturing node. In the past, we have reported that the company struggled with yields of its 5 nm process, however, that seems to be ironed out and now the node is in full production. To contribute to the statement that the new node is doing well, we also recently reported that Samsung will be the sole manufacturer of Qualcomm Snapdragon 875 5G SoC.

The new 5 nm semiconductor node is a marginal improvement over the past 7 nm node. It features a 10% performance improvement that is taking the same power and chip complexity or a 20% power reduction of the same processor clocks and design. When it comes to density, the company advertises the node with x1.33 times increase in transistor density compared to the previous node. The 5LPE node is manufactured using the Extreme Ultra-Violet (EUV) methodology and its FinFET transistors feature new characteristics like Smart Difusion Break isolation, flexible contact placement, and single-fin devices for low power applications. The node is design-rule compatible with the previous 7 nm LPP node, so the existing IP can be used and manufactured on this new process. That means that this is not a brand new process but rather an enhancement. First products are set to arrive with the next generation of smartphone SoCs, like the aforementioned Qualcomm Snapdragon 875.

Taiwanese corporation United Micro Electronics (UMC) has pled guilty on charges of trade theft. The charges, originally pressed in November 2018 by US authorities, placed UMC and China's Fujian Jinhua in hot waters under suspicion of stealing trade secrets from US-based Micron technologies, one of the world's foremost players in memory semiconductor technologies. UMC's guilty plea serves as a way for the company to avoid heavier penalties, and includes a provision for the company's assistance in investigating Fujian Jinhua's actions in regards to this IP theft.

The whole story revolves around UMC's hiring of three Micron employees from Micron's subsidiary in Taiwan, Micron Memory Taiwan (MMT), back around September 2015. At least two of these employees migrated Micron trade secrets to UMC, which then inked a deal with china's Fujian Jinhua for the development of 32nm DRAM and "32Snm" DRAM technologies that Fujian Jinhua could then deploy for the manufacture of memory products - a deal which had Fujian Jinhua paying $300 million for equipment purchase plus $400 million for technology development to UMC. This all fell in line with the Chinese government's Made in China 2025 plan, which aims to bring the country to semiconductor independence from the western world. UMC says that the company itself didn't partake in the underhanded IP delivery to Fujian Jinhua, claiming instead that rogue employees did so of their own volition. The company further states that it only pleads guilty because according to the US Trade Secrets Act, the company still bears legal responsibilities for employee acts, whether or not top management is involved.

Today, Intel has decided to surprise us and give an update to its upcoming CPU lineup for desktop. With the 11th generation, Core CPUs codenamed Rocket Lake-S, Intel is preparing to launch the new lineup in the first quarter of 2021. This means that we are just a few months away from this launch. When it comes to the architecture of these new processors, they are going to be based on a special Cypress Cove design. Gone are the days of Skylake-based designs that were present from the 6th to 10th generation processors. The Cypress Cove, as Intel calls it, is an Ice Lake adaptation. Contrary to the previous rumors, it is not an adaptation of Tiger Lake Willow Cove, but rather Ice Lake Sunny Cove.

The CPU instruction per cycle (IPC) is said to grow in double-digits, meaning that the desktop users are finally going to see an improvement that is not only frequency-based. While we do not know the numbers yet, we can expect them to be better than the current 10th gen parts. For the first time on the Intel platform for desktops, we will see the adoption of PCIe 4.0 chipset, which will allow for much faster SSD speeds and support the latest GPUs, specifically, there will be 20 PCIe 4.0 lanes coming from the CPU only. The CPU will be paired with 12th generation Xe graphics, like the one found in Tiger Lake CPUs. Other technologies such as Deep Learning Boost and VNNI, Quick Sync Video, and better overclocking tuning will be present as well. Interesting thing to note here is that the 10C/20T Core i9-10900K has a PL1 headroom of 125 W, and 250 W in PL2. However, the 8C/16T Rocket Lake-S CPU also features 125 W headroom in PL1, and 250 W in PL2. This indicates that the new Cypress Cove design runs hotter than the previous generation.

Apple has established itself as a master of silicon integrated circuit design and has proven over the years that its processors deliver the best results, generation after generation. If we take a look at the performance numbers of the latest A14 Bionic, you can conclude that its performance is now rivaling some of the x86_64 chips. So you would wonder, what is inside this SoC that makes it so fast? That is exactly what ICmasters, a semiconductor reverse engineering and IP services company, has questioned and decided to find out. For starters, we know that Apple manufactures the new SoCs on TSMC's N5 5 nm node. The Taiwanese company promises to pack 171.3 million transistors per square millimeter, so how does it compare to an actual product?

ICmasters have used electron microscopy to see what the chip is made out of and to measure the transistor density. According to this source, Apple has a chip with a die size of 88 mm², which packs 11.8 billion N5 transistors. The density metric, however, doesn't correspond to that of TSMC. Instead of 171.3 million transistors per mm², the ICmasters measured 134.09 million transistors per mm². This is quite a difference, however, it is worth noting that each design will have it different due to different logic and cache layout.