Monday, July 29th 2019

AMD Readies Larger 7nm "Navi 12" Silicon to Power Radeon RX 5800 Series?
AMD is developing a larger GPU based on its new "Navi" architecture to power a new high-end graphics card family, likely the Radeon RX 5800 series. The codename "Navi 12" is doing rounds on social media through familiar accounts that have high credibility with pre-launch news and rumors. The "Navi 10" silicon was designed to compete with NVIDIA's "TU106," as its "XT" and "Pro" variants outperform NVIDIA's original RTX 2060 and RTX 2070, forcing it to develop the RTX 20 Super series, by moving up specifications a notch.
Refreshing its $500 price-point was particularly costly for NVIDIA, as it was forced to tap into the 13.6 billion-transistor "TU104" silicon to carve out the RTX 2070 Super; while for the RTX 2060 Super, it had to spend 33 percent more on the memory chips. With the "Navi 12" silicon, AMD is probably looking to take a swing at NVIDIA's "TU104" silicon, which has been maxed out by the RTX 2080 Super, disrupting the company's $500-700 lineup once again, with its XT and Pro variants. There's also a remote possibility of "Navi 12" being an even bigger chip, targeting the "TU102."
Source:
KOMACHI_ENSAKA (Twitter)
Refreshing its $500 price-point was particularly costly for NVIDIA, as it was forced to tap into the 13.6 billion-transistor "TU104" silicon to carve out the RTX 2070 Super; while for the RTX 2060 Super, it had to spend 33 percent more on the memory chips. With the "Navi 12" silicon, AMD is probably looking to take a swing at NVIDIA's "TU104" silicon, which has been maxed out by the RTX 2080 Super, disrupting the company's $500-700 lineup once again, with its XT and Pro variants. There's also a remote possibility of "Navi 12" being an even bigger chip, targeting the "TU102."
132 Comments on AMD Readies Larger 7nm "Navi 12" Silicon to Power Radeon RX 5800 Series?
BTW. I'm Vega 64 owner and I don't feel bad with Navi release. It is not Vega chip with a boost. Although, I'm sure there are people here that will disagree. For them GCN and RDNA are the same.
Radeon 7 woops the 5700 XT across the board.
RTX 2070 Super woops 5700 XT now means 5800/5800 XT are going after RTX 2080 and 2080 Super performance levels.
Leaving RTX 2080Ti for Navi 20
Not everyone wants to spend well over $2000 on a non-upgradeable RTX gaming laptop that can't even match a $500 desktop GPU.
CU scaling is not enough without scaling towards 6 prim units and 96 ROPS. Hint; Titan RTX has six GPCs, 96 ROPS and 6 MB L2 cache.
RX 5700 XT has 40 CU, four prim units, 64 ROPS and 4 MB L2 cache. TU106 has four GPCs, 64 ROPS and 4 MB L2 cache, hence similar to NAVI 10 XT. Largest Polaris baseline IP is Xbox One X's 44 CU scaling with 384 bit bus.
That could leave to 350W on thrid party cards with more headroom for overclocking.
RTX 2080 Ti is a 250W TDP card and its performance is 34% higher tha RX 5700XT
RX 5700XT is a 225W TDP card, and if we put some maths (134%) to get a higher TDP
we end up with more than 300W, even if perfomance could be linear, wich isn't,
RX 5800 has to become a 300W TDP card to compete with RTX 2080 Ti.
The table below shows the consumption peak, which is rarely given in real life,
and is only for academic purposes.
Would that be possible?
The fixed function geometry hardware is all gone. Vertex, geometry, and tessellation stages are all combined into the primitive shader and those stages are emulated in older games for compatibility (which AMD says is still faster than previous Vega's dedicated hardware ... oof!). I believe the geometry processor can support any number of primitive units through virtualization of work queues, a bit like the HWS does for ACEs. Not much has been divulged though, so take that with a boulder of salt.
So, with a theoretical maximum of 8 shader engines with 10 CUs each, that's a total of 80 CUs/5120SPs or double Navi 10's 40/2560SPs.
That's obviously overkill, so that would probably only replace Vega 20 (if paired with HBM3) for compute and compete with Nvidia's top end Quadros, maybe in 2020 or later.
But, I think it's very possible we could see 72CU and lower configurations with only 6 shader engines, much like TU102 and TU104 have 6 GPCs with varying SMs per GPC. TU102 has 12 SMs per GPC (72 max), while TU104 has 8 (48 max), both in full die configuration. TU102-300 in RTX 2080Ti has 4 SMs, one 32-bit MC with 512KB L2, and 8 ROPs disabled. So, it's 68 SMs rather than GPCs. GPCs are the complete processing cluster units.
7870 has two shader engines with two geometry units, 20 CU, 32 ROPS, 512KB L2 cache coupled with 256 bit bus.
R9-290X has four shader engines with four geometry units, 44 CU, 64 ROPS, 1MB L2 cache coupled with 512 bit bus. R9-290X is 2X scaled 7870.
Your argument for " theoretical maximum of 8 shader engines with 10 CUs each" didn't factor in memory controller relationship!
Each NAVI shader engine has two prim units, 20 CU, 32 ROPS, 2MB L2 cache and 128 bit bus.
TU104 has similar geometry power like TU102 with TU106's read/write ROPS and 4MB L2 cache.
AMD's only chance against Nvidia is to move to more shader engines. That way they don't have to push the clocks outside of 7nm's efficiency range (2.1GHz OC destroyed efficiency of RDNA) and they'll gain the same rasterization capabilities as TU102/104. It'll help when AMD themselves move to RT capable hardware, which is expected in RDNA 2.
I'm curious to see what Nvidia does with Ampere. I'm thinking they'll try to at least double ray tracing performance or more. Not sure how much die space that'll take on Samsung's 7nm EUV. All that means is that these higher GPU prices are here to stay. =\
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Hans Mosesmann -- Rosenblatt Securities -- Analyst
Great. And can you give us a sense, if you can, on 7-nanometer high-end Navi and mobile 7-nanometer CPUs, if you can? Thanks.
Lisa Su -- President and Chief Executive Officer
Hans, you asked the good product questions. I would say, they are coming. You should expect that our execution on those are on track, and we have a rich 7-nanometer portfolio beyond the products that we have currently announced in the upcoming quarters. Thank you, Hans.