Friday, June 10th 2022
AMD Announces the "Zen 5" Microarchitecture and EPYC "Turin" Processor on 4nm
AMD in its Financial Analyst Day 2022 presentation, unveiled its next-generation "Zen 5" CPU microarchitecture. The company's latest CPU microarchitecture roadmap also confirms that variants of its "Zen 4" CCDs with 3D Vertical Cache (3DV Cache) are very much in the works, and there will be variants of the EPYC "Genoa" processors with 3DV Cache, besides standard ones.
AMD stated that it completed the design goal of the current "Zen 3" architecture, by building it on both 7 nm and 6 nm nodes (the latter being the client "Rembrandt" processor). The new "Zen 4" architecture will debut on the 5 nm node (TSMC N5), and could see a similar optical shrink to the newer 4 nm node somewhere down the line, although AMD wouldn't specify whether it's on the enterprise segment, or client. The next-gen "Zen 5" architecture will debut on 4 nm, and see an optical shrink to 3 nm on some future product.
The EPYC enterprise processor based on "Zen 5" will be codenamed "Turin." The company didn't detail the processor, but did offer the first teaser about what's in store with "Zen 5." Like every other "Zen" architecture generation before it, "Zen 5" will introduce performance and efficiency enhancements (IPC increase and performance/Watt increase from the transition to a new foundry node). AMD is redesigning the front-end of the CPU core, and re-pipelining it for wide issue, which indicates a much broader execution stage.
AMD also teases AI/ML optimizations—this could indicate fixed-function hardware building on the AI/ML capabilities of "Zen 4." On the "Zen 4," AMD is deploying AVX-512 BLOAT16 and VNNI extensions as part of the CPU core's ISA, without any external fixed-function hardware (like Intel's GNA). In our interview with AMD's Robert Hallock, he didn't rule out the possibility of such hardware in "future developments," given AMD's acquisition of Xilinx.
AMD's roadmap hints at a 2024 debut for "Zen 5" and the EPYC "Turin" processor. We'll come across several other codenames, both from the enterprise and client segments, for products based on "Zen 5," in the coming months.
AMD stated that it completed the design goal of the current "Zen 3" architecture, by building it on both 7 nm and 6 nm nodes (the latter being the client "Rembrandt" processor). The new "Zen 4" architecture will debut on the 5 nm node (TSMC N5), and could see a similar optical shrink to the newer 4 nm node somewhere down the line, although AMD wouldn't specify whether it's on the enterprise segment, or client. The next-gen "Zen 5" architecture will debut on 4 nm, and see an optical shrink to 3 nm on some future product.
AMD also teases AI/ML optimizations—this could indicate fixed-function hardware building on the AI/ML capabilities of "Zen 4." On the "Zen 4," AMD is deploying AVX-512 BLOAT16 and VNNI extensions as part of the CPU core's ISA, without any external fixed-function hardware (like Intel's GNA). In our interview with AMD's Robert Hallock, he didn't rule out the possibility of such hardware in "future developments," given AMD's acquisition of Xilinx.
AMD's roadmap hints at a 2024 debut for "Zen 5" and the EPYC "Turin" processor. We'll come across several other codenames, both from the enterprise and client segments, for products based on "Zen 5," in the coming months.
12 Comments on AMD Announces the "Zen 5" Microarchitecture and EPYC "Turin" Processor on 4nm
When they start to integrate ZenA with ZenBc cores Intel's multithreading advantage will go poof, so gaming performance will dictate even more the narrative/pricing, so Intel must execute otherwise i smell troubles.
Even if there is a delay for Raptor Lake and comes at Q4 instead of August, I don't consider it problem as Alder Lake has better lineup vs Zen3, so there is really no pressing competition to force Intel to launch before Zen4 (as long as it launches very close to Zen4 and there is a 2023 follow-up capable to compete with Zen4 V-cache regarding gaming performance (that's the main uncertainty imo)
So we will have 4nm for Zen4 APU (Phoenix Point) that's good news for the mobile front also (it seems that AMD's intention is Zen5 APU to be 3nm if it finds capacity)
Also another thought based on Genoa-X info is that maybe Zen4 Raphael has only 32MB L3 cache with V-cache version reaching 96MB, this will explain the smaller IPC gain btw.