AMD Ryzen AI MAX 300-series processors, codenamed "Strix Halo," have been on in the news for close to a year now. These mobile processors combine "Zen 5" CPU cores with an oversized iGPU that offers performance rivaling discrete GPUs, with the idea behind these chips being to rival the Apple M3 Pro and M3 Max processors powering MacBook Pros. The "Strix Halo" mobile processor is an MCM that combines one or two "Zen 5" CCDs (some ones featured on "Granite Ridge" desktop processors and "Turin" server processors), with a large SoC die. This die is built either on the 5 nm (TSMC N5) or 4 nm (TSMC N4P) node. It packs a large iGPU based on the RDNA 3.5 graphics architecture, with 40 compute units (CU), and a 50 TOPS-class XDNA 2 NPU carried over from "Strix Point." The memory interface is a 256-bit wide LPDDR5X-8000 for sufficient memory bandwidth for the up to 16 "Zen 5" CPU cores, the 50 TOPS NPU, and the large 40 CU iGPU.

Golden Pig Upgrade leaked what looks like a company slide from a notebook OEM, which reveals the iGPU model names for the various Ryzen AI MAX 300-series SKUs. Leading the pack is the Ryzen AI MAX+ 395. This is a maxed out SKU with a 16-core/32-thread "Zen 5" CPU that uses two CCDs. All 16 cores are full-sized "Zen 5." The CPU has 64 MB of L3 cache (32 MB per CCD), each of the 16 cores has 1 MB of dedicated L2 cache. The iGPU is branded Radeon 8060S, it comes with all 40 CU (2,560 stream processors) enabled, besides 80 AI accelerators, and 40 Ray accelerators. The Ryzen AI MAX 390 is the next processor SKU, it comes with a 12-core/24-thread "Zen 5" CPU. Like the 395, the 390 is a dual-CCD processor, all 12 cores are full-sized "Zen 5." There's 64 MB of L3 cache, and 1 MB of L2 cache per core. The Radeon 8060S graphics solution is the same as the one on the Ryzen AI MAX+ 395, it comes with all 40 CU enabled.

MSI is thrilled to introduce the upcoming AMD Ryzen 7 9800X3D, an innovation built on the Zen 5 architecture and featuring AMD's groundbreaking 3D V-Cache technology. The Ryzen 7 9800X3D is designed for peak performance with improved IPC and superior power efficiency compared to the previous generation, promising an exhilarating leap in computing power.

The Ryzen 7 9800X3D integrates seamlessly with the AM5 socket ecosystem, providing users access to PCIe Gen 5 bandwidth and high-speed DDR5 memory support. Built on a 4 nm process, this processor establishes a new performance, power efficiency, and responsiveness benchmark, ideal for intensive gaming and content creation. MSI's X870(E) motherboards are fully compatible with the Ryzen 7 9800X3D, featuring a robust lineup from MEG X870E GODLIKE to MAG X870 TOMAHAWK WIFI. MSI's X870(E) motherboards and AMD's latest processors unlock peak gaming performance for users.

The American semiconductor landscape reached a significant milestone as TSMC's new Arizona manufacturing facility demonstrated remarkable production efficiency, exceeding its Taiwanese counterparts by 4% in yield rates. This achievement, revealed at a recent industry webinar by the company's US division chief, represents a major step forward in America's push to strengthen domestic chip manufacturing capabilities. Since initiating its 4 nm node production operations this spring, the Phoenix-based facility has demonstrated impressive technical proficiency, achieving production standards that match and surpass TSMC's established Taiwanese facilities. The project, backed by substantial federal support, including $11.6 billion in combined grants and loans plus significant tax incentives, aims to establish three cutting-edge manufacturing plants in Arizona.

The company's global leadership praised the facility's performance, noting its strategic importance in demonstrating TSMC's ability to maintain exceptional manufacturing standards across international locations. This success carries particular weight given the project's earlier hurdles, which included workforce challenges and timeline adjustments that shifted the entire production schedule by approximately one year. This development gains additional significance against industry-wide challenges, particularly as competitors like Intel and Samsung face operational and financial obstacles. The semiconductor giant's plans now extend to potential further expansion, with the Phoenix site capable of hosting up to six manufacturing facilities. Future growth prospects could be enhanced by proposed additional government initiatives supporting domestic chip production.

The second generation of AMD Ryzen Z-series processors for handheld gaming consoles, will be led by the Ryzen Z2 Extreme. There will also be an affordable Ryzen Z2 (non-Extreme). We've known for some time that the Z2 Extreme is based on the 4 nm "Strix Point" monolithic silicon, with some optimization (the highest bins to facilitate the best energy efficiency); but now we have a few more details thanks to a leak by Golden Pig Upgrade. AMD's engineering effort with the Z2 Extreme will be to give the console the most generational performance uplift from the iGPU, rather than the CPU.

The "Strix Point" silicon features a significantly updated iGPU from the previous-generation "Phoenix." It's based on the more efficient RDNA 3.5 graphics architecture, which is better optimized for LPDDR5 memory; and comes with 16 compute units (CU), compared to 12 on the "Phoenix." The Ryzen Z2 Extreme will come with all 16 CU enabled. The CPU is where some interesting changes are planned. The "Strix Point" silicon features a dual-CCX CPU, one of these contains four "Zen 5" CPU cores sharing a 16 MB L3 cache, while the other features eight "Zen 5c" cores sharing an 8 MB L3 cache. For the Ryzen Z2 Extreme, AMD is going with an odd 3+5 core configuration. What this means is that the Ryzen Z2 Extreme will have 3 "Zen 5" cores, and 5 "Zen 5c" cores. The L3 cache on the CCX with "Zen 5" cores has been reduced to 8 MB in size. On paper, this is still an 8-core/16-thread CPU with 16 MB of L3 cache (same as "Phoenix,") but now you know that there's more going on.

GPU chip packages of the "Navi 4x" generation of GPUs could be generationally smaller than their predecessors, according to leaked package dimensions of the "Navi 44" chip put out by Olrak29_. With its next-generation Radeon RX gaming GPUs based on the RDNA 4 graphics architecture, AMD has decided to focus on gaining market-share in the performance and mainstream segments, ceding the enthusiast segment to NVIDIA. As part of its effort, the company is making RDNA 4 efficient at every level—architecture, process, and package.

At the architecture level, RDNA 4 is expected to improve performance, particularly the performance cost of ray tracing, through a more specialized ray tracing hardware stack. At the process level, AMD is expected to switch to a more efficient foundry node, with some reports suggesting the TSMC 4 nm, such as the N4P or N4X. For a mid-range GPU like the "Navi 44," which succeeds the "Navi 23" and "Navi 33," these mean a rather big leap from the 7 nm or 6 nm DUV nodes. The leak suggests a smaller package, measuring 29 mm x 29 mm. In comparison, the "Navi 23" package measures 35 mm x 35 mm. The smaller package could make these GPUs friendlier with gaming notebooks, where mainboard PCB real-estate is at a premium.

Today, AMD (NASDAQ: AMD) announced its third generation commercial AI mobile processors, designed specifically to transform business productivity with Copilot+ features including live captioning and language translation in conference calls and advanced AI image generators. The new Ryzen AI PRO 300 Series processors deliver industry-leading AI compute, with up to three times the AI performance than the previous generation, and offer uncompromising performance for everyday workloads. Enabled with AMD PRO Technologies, the Ryzen AI PRO 300 Series processors offer world-class security and manageability features designed to streamline IT operations and ensure exceptional ROI for businesses.

Ryzen AI PRO 300 Series processors feature new AMD "Zen 5" architecture, delivering outstanding CPU performance, and are the world's best line up of commercial processors for Copilot+ enterprise PCs. Laptops equipped with Ryzen AI PRO 300 Series processors are designed to tackle business' toughest workloads, with the top-of-stack Ryzen AI 9 HX PRO 375 offering up to 40% higher performance and up to 14% faster productivity performance compared to Intel's Core Ultra 7 165U. With the addition of XDNA 2 architecture powering the integrated NPU, AMD Ryzen AI PRO 300 Series processors offer a cutting-edge 50+ NPU TOPS (Trillions of Operations Per Second) of AI processing power, exceeding Microsoft's Copilot+ AI PC requirements and delivering exceptional AI compute and productivity capabilities for the modern business. Built on a 4 nm process and with innovative power management, the new processors deliver extended battery life ideal for sustained performance and productivity on the go.

Samsung Electronics is speeding up its work on 2 nm production facilities, industry sources say. The company has started to install advanced equipment at its "S3" foundry line in Hwaseong to set up a 2 nm production line. This line aims to produce 7,000 wafers each month by the first quarter of next year. Also, Samsung plans to create a 1.4 nm production line at its "S5" foundry in Pyeongtaek Plant 2 by the second quarter of next year. This line has a goal to make 2,000 to 3,000 wafers each month. By the end of next year, Samsung will change all the remaining 3 nm production lines at "S3" to 2 nm.

As we reported earlier, Samsung has pushed back the start date for its Tyler, Texas foundry. The plant set to open by late 2024, won't install equipment until after 2026. Also, Samsung has changed its plans for the Pyeongtaek Fab 4 foundry line. Because of lower demand, it will now make DRAM instead, moreover, at Pyeongtaek Fab 3, which has a 4 nm line, Samsung has cut back production. These changes are part of Samsung's plan to make 2 nm chips next year and 1.4 nm chips by 2027. The company wants to catch up with its rival TSMC, right now, Samsung has 11.5% of the global foundry market in Q2, while TSMC leads with 62.3%. An industry expert stressed how crucial this is saying, "With the delay in 3 nm Exynos production and other issues, getting the 2 nm process right could make or break Samsung Foundry". The struggle for Samsung is real, with the company's top management, led by DS Division Vice Chairman Jeon Young-hyun, having recently issued a public apology for the division's underwhelming performance.

High-resolution die-shots of the AMD "Zen 5" 8-core CCD were released and annotated by Nemez, Fitzchens Fitz, and HighYieldYT. These provide a detailed view of how the silicon and its various components appear, particularly the new "Zen 5" CPU core with its 512-bit FPU. The "Granite Ridge" package looks similar to "Raphael," with up to two 8-core CPU complex dies (CCDs) depending on the processor model, and a centrally located client I/O die (cIOD). This cIOD is carried over from "Raphael," which minimizes product development costs for AMD at least for the uncore portion of the processor. The "Zen 5" CCD is built on the TSMC N4P (4 nm) foundry node.

The "Granite Ridge" package sees the up to two "Zen 5" CCDs snuck up closer to each other than the "Zen 4" CCDs on "Raphael." In the picture above, you can see the pad of the absent CCD behind the solder mask of the fiberglass substrate, close to the present CCD. The CCD contains 8 full-sized "Zen 5" CPU cores, each with 1 MB of L2 cache, and a centrally located 32 MB L3 cache that's shared among all eight cores. The only other components are an SMU (system management unit), and the Infinity Fabric over Package (IFoP) PHYs, which connect the CCD to the cIOD.

Samsung's foundry plans have again hit a major setback. The company notified staff at its Taylor, Texas facility that it was temporarily removing workers from the site because it is still experiencing challenges with 2 nm semiconductor yields, delaying mass production timelines from late 2024 to 2026. The Taylor site had been anticipated as the flagship facility for Samsung's sub-4 nm production, allowing access to potential customers near the facility. While Samsung has moved rapidly in terms of process development, its yields for advanced nodes have outstripped them, the company's yields for sub-3 nm processes hover around 50%, with Gate-All-Around (GAA) technology witnessing yields of only 10-20%, significantly lower than neighboring competitor TSMC's 60-70% for corresponding nodes.

The yield gaps that the company is experiencing have exacerbated the gap in market share, with TSMC capturing 62.3% of the global foundry market share in Q2 versus Samsung's 11.5%. The company is struggling to gain share despite efforts by Chairman Lee Jae-yong - including visits to component suppliers ASML, and Zeiss - and these yields put at risk as much as 9 trillion won in U.S. CHIP Act potential subsidies that are dependent upon operational milestones.

TSMC has reportedly managed to produce yields at its Arizona facility that are on par with yields back home in Taiwan, making its expansion efforts successful. According to Bloomberg, TSMC did a trial production, a multi-month effort, to produce N4 node wafers with low defect rates. With wafers now in TSMC's labs for testing, it is reported that Arizona facility yields have achieved parity with their Taiwanese facilities back home. This indicates that TSMC's efforts to expand in the US are so far considered a success, as advanced chipmaking is a very complex process that is only done by a few makers and in very few locations. With TSMC expanding in the US now and proving that its technology can work on US soil, the company has a green light to start volume production in the first half of 2025.

However, this is only the beginning of TSMC's Arizona expansion. The Taiwanese giant plans to have a second fab operational by 2028 and produce 2 nm and 3 nm chips in the state. Additionally, there will be a third facility for 2 nm and more advanced nodes in Phoenix, bringing the total value of TSMC's US expansion efforts to $65 billion, with $6.6 billion from the CHIPS Act grants and $5 billion in loans from the US government. If upcoming fabs follow the lead of the first facility, US-based production needs will possibly be satisfied.

AMD is readying a major update to its category-defining Ryzen Z-series SoCs, with the new Ryzen Z2. Designed for handheld game consoles, the Ryzen Z-series chips are typically power-optimized variants of its mobile processors designed for ultra-low board footprint, allowing PC OEMs to build handheld game consoles with them. Facing competition from Intel's upcoming Core Ultra 200V "Lunar Lake-MX" SoCs in this segment, AMD is readying the Ryzen Z2 chip. The Z2 is based on the 4 nm "Strix Point" silicon, which gives it a significantly updated iGPU, as well as a higher core-count CPU.

Perhaps the biggest sub-system performance uplift console designers can expect from the Ryzen Z2 is graphics—AMD has given the "Strix Point" a larger iGPU with 16 compute units in place of 12 on "Phoenix," which is a 33% increase in just numerical terms. Then there's also the update to the newer RDNA 3.5 graphics architecture, which incorporates several architecture-level performance and battery-efficiency improvements. It's also better optimized for LPDDR5 memory. With CPU, AMD has given "Strix Point" a heterogeneous multicore setup with four "Zen 5" and eight "Zen 5c" cores. At this point, we don't know if all 12 cores are enabled on the Z2. ASUS is designing its next generation of ROG Ally consoles powered by the Ryzen Z2, and its designers hint that the console should be able to offer over 1 hour of "Black Myth: Wukong" gameplay on a full charge of battery—something current-gen ROG Ally X powered by the Z1 doesn't.

MSI is excited to announce the launch of the latest AMD Ryzen 9000 Series processors, set to debut on the AM5 platform. Powered by advanced 4 nm CPU process technology, the Ryzen 9000 Series promises to revolutionize the computing landscape with unmatched performance, efficiency, and versatility for gamers and content creators. At launch, August 8th, AMD Ryzen 7 9700X, and Ryzen 5 9600X are available while the Ryzen 9 9950X and 9900X will launch on August 15th. These processors will feature up to 16 cores and 32 threads, with a theoretical maximum boost clock speed of 5.7 GHz, 64 MB of L3 cache, and a maximum TDP of 170 W.

AMD Ryzen 9000 Series will also support PCIe 5.0 for the GPU and M.2 while enhancing DDR5 memory speed. Notably, the AMD Ryzen 7 9700X offers approximately 12% better overall performance than the first-gen AMD 3D V-cache CPU. All these processors are compatible with the AM5 socket, and existing AMD 600 Series motherboards and Ryzen 9000 Series processors can seamlessly integrate by updating to the latest BIOS, available on MSI's product support page.

The first die shot of AMD's new 4 nm "Strix Point" mobile processor surfaced, thanks to an enthusiast on Chinese social media. "Strix Point" is a significantly larger die than "Phoenix." It measures 12.06 mm x 18.71 mm (L x W), compared to the 9.06 mm x 15.01 mm of "Phoenix." Much of this die size increase comes from the larger CPU, iGPU, and NPU. The process has been improved from TSMC N4 on "Phoenix" and its derivative "Hawk Point," to the newer TSMC N4P node.

Nemez (GPUsAreMagic) annotated the die shot in great detail. The CPU now has 12 cores spread across two CCX, one of which contains four "Zen 5" cores sharing a 16 MB L3 cache; and the other with eight "Zen 5c" cores sharing an 8 MB L3 cache. The two CCXs connect to the rest of the chip over Infinity Fabric. The rather large iGPU takes up the central region of the die. It is based on the RDNA 3.5 graphics architecture, and features 8 workgroup processors (WGPs), or 16 compute units (CU) worth 1,024 stream processors. Other key components include four render backends worth 16 ROPs, and control logic. The GPU has its own 2 MB of L2 cache that cushions transfers to the Infinity Fabric.

AMD is readying a successor to its Ryzen 7045 series "Dragon Range" mobile processor for gaming notebooks and portable workstations. While we don't know its processor model naming yet, the chip is codenamed "Fire Range." We are learning that it will retain the FL1 package as "Dragon Range," which means it will be pin-compatible. This would significantly reduce development costs for notebook OEMs, as they can simply carry over their mainboard designs from their notebooks based on "Dragon Range."

"Fire Range" is essentially a mobile BGA version of the upcoming Ryzen 9000 "Granite Ridge" desktop processor. The FL1 package measures 40 mm x 40 mm in size, and has substrate for two CCDs and a cIOD, just like the desktop chip. "Fire Range" hence features one or two 4 nm "Zen 5" CCDs, depending on the processor model, and the 6 nm client I/O die. Much like "Dragon Range," the "Fire Range" chip will lack support for LPDDR5, and rely on conventional PC DDR5 memory in the SO-DIMM or CAMM2 form-factors. Besides the CPU core count consisting exclusively of full-sized "Zen 5" cores, the main flex for "Fire Range" over "Strix Point" will be its 28-lane PCIe Gen 5 root-complex, which can wire out the fastest discrete mobile GPUs, as well as drive multiple M.2 NVMe slots with Gen 5 wiring, and other high-bandwidth devices, such as Thunderbolt 4, USB4, or Wi-Fi 7 controllers wired directly to the processor.

AMD "Granite Ridge" is codename for the four new Ryzen 9000 series desktop processors the company plans to launch on July 31, 2024. The processor is built in the Socket AM5 package, and is meant to be backwards compatible with AMD 600-series chipset motherboards, besides the new 800-series chipset ones that will launch alongside. "Granite Ridge" is a chiplet-based processor, much like the Ryzen 7000 "Raphael," Ryzen 5000 "Vermeer," and Ryzen 3000 "Matisse." AMD is carrying over the 6 nm client I/O die over from "Raphael" in an effort to minimize development costs, much in the same way it carried over the 12 nm cIOD for "Vermeer" from "Matisse."

The SoC I/O features of "Granite Ridge" are contemporary, with its awesome 28-lane PCI-Express Gen 5 root complex that allows a PCI-Express 5.0 x16, two CPU-attached M.2 Gen 5 slots, and a Gen 5 x4 chipset bus. There's also a basic integrated graphics solution based on the older RDNA 2 graphics architecture; which should make these processors fit for all use-cases that don't need discrete graphics. The iGPU even has multimedia accelerators, an audio coprocessor, a display controller, and USB 3.2 interfaces from the processor.

Avnet ASIC, a division of Avnet Silica, an Avnet company, today announced that it has launched its new ultra-low-power design services for TSMC's cutting-edge 4 nm and below process technologies. These services are designed to enable customers to achieve exceptional power efficiency and performance in their high-performance applications, such as blockchain and AI edge computing. TSMC is the world's leading silicon foundry and Avnet ASIC division is a leading provider of ASIC and SoC full turnkey solutions.

The new design services leverage a comprehensive approach to address the challenges of operating at extreme low-voltage conditions in the 4 nm and below nodes. This includes recharacterizing standard cells for lower voltages, performing early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.

It appears like 2024 will go down as the second consecutive year without any new GPU generation launch from either NVIDIA or AMD. Kopite7kimi, a reliable source with NVIDIA leaks, says that the GeForce RTX 50-series "Blackwell" generation won't see a debut before the 2025 International CES (January 2025). It was earlier expected that the company would launch at least its top two SKUs—the RTX 5090 and RTX 5080—toward the end of 2024, and ramp the series up from 2025. There is no explanation behind this "delay." Like everyone else, NVIDIA could be rationing its foundry allocation of the 3 nm wafers from TSMC for its high-margin "Blackwell" AI GPUs. The company now makes over five times the revenue from selling AI GPUs than it does from gaming GPUs, so this development should come as little surprise.

Things aren't any different with NVIDIA's rivals in this space, AMD and Intel. AMD's RDNA 4 graphics architecture and the Radeon RX series GPUs based on it, aren't expected to arrive before 2025. AMD is making several architectural upgrades with RDNA 4, particularly to its ray tracing hardware; and the company is expected to build these GPUs on a new foundry node. Meanwhile, Intel's Arc B-series gaming GPUs based on the Xe2 "Battlemage" graphics architecture are expected to arrive in 2025, too, although these chips are rumored to be based on a more mature 4 nm-class foundry node.

AMD is about give the new "Zen 5" microarchitecture a near-simultaneous launch across both its client segments—desktop and mobile. The desktop front is held by the Ryzen 9000 "Granite Ridge" Socket AM5 processors; while Ryzen AI 300 "Strix Point" powers the company's crucial effort to capture Microsoft Copilot+ AI PC market share. We recently did a technical deep-dive on the two. HardwareLuxx.de scored two important bits of specs for both processors in its Q&A interaction with AMD—die sizes and transistor counts.

To begin with, "Strix Point" is a monolithic silicon, which is confirmed to be built on the TSMC N4P foundry node (4 nm). This is a slight upgrade over the N4 node that the company built its previous generation "Phoenix" and "Hawk Point" processors on. The "Strix Point" silicon measures 232.5 mm² in area, which is significantly larger than the 178 mm² of "Hawk Point" and "Phoenix." The added die area comes from there being 12 CPU cores instead of 8, and 16 iGPU compute units instead of 12; and a larger NPU. There are many other factors, such as the larger 24 MB CPU L3 cache; and the sizes of the "Zen 5" and "Zen 5c" cores themselves.

Taiwanese semiconductor giant TSMC is reportedly planning to increase its wafer prices by up to 10% in 2025, according to a Morgan Stanley note cited by investor Eric Jhonsa. The move comes as demand for cutting-edge processors in smartphones, PCs, AI accelerators, and HPC continues to surge. Industry insiders reveal that TSMC's state-of-the-art 4 nm and 5 nm nodes, used for AI and HPC customers such as AMD, NVIDIA, and Intel, could see up to 10% price hikes. This increase would push the cost of 4 nm-class wafers from $18,000 to approximately $20,000, representing a significant 25% rise since early 2021 for some clients and an 11% rise from the last price hike. Talks about price hikes with major smartphone manufacturers like Apple have proven challenging, but there are indications that modest price increases are being accepted across the industry. Morgan Stanley analysts project a 4% average selling price increase for 3 nm wafers in 2025, which are currently priced at $20,000 or more per wafer.

Mature nodes like 16 nm are unlikely to see price increases due to sufficient capacity. However, TSMC is signaling potential shortages in leading-edge capacity to encourage customers to secure their allocations. Adding to the industry's challenges, advanced chip-on-wafer-on-substrate (CoWoS) packaging prices are expected to rise by 20% over the next two years, following previous increases in 2022 and 2023. TSMC aims to boost its gross margin to 53-54% by 2025, anticipating that customers will absorb these additional costs. The impact of these price hikes on end-user products remains uncertain. Competing foundries like Intel and Samsung may seize this opportunity to offer more competitive pricing, potentially prompting some chip designers to consider alternative manufacturing options. Additionally, TSMC's customers could reportedly be unable to secure their capacity allocation without "appreciating TSMC's value."

Apparently the AMD "Strix Halo" processor is real, and it's large. The chip is designed to square off against the likes of the Apple M3 Pro and M3 Max, in letting ultraportable notebooks have powerful graphics performance. A chiplet-based processor, not unlike the desktop socketed "Raphael," and mobile BGA "Dragon Range," the "Strix Halo" processor consists of one or two CCDs containing CPU cores, wired to a large die, that's technically the cIOD (client I/O die), but containing an oversized iGPU, and an NPU. The point behind "Strix Halo" is to eliminate the need for a performance-segment discrete GPU, and conserve its PCB footprint.

According to leaks by Harukaze5719, a reliable source with AMD leaks, "Strix Halo" comes in a BGA package dubbed FP11, measuring 37.5 mm x 45 mm, which is significantly larger than the 25 mm x 40 mm size of the FP8 BGA package that the regular "Strix Point," "Hawk Point," and "Phoenix" mobile processors are built on. It is larger in area than the 40 mm x 40 mm FL1 BGA package of "Dragon Range" and upcoming "Fire Range" gaming notebook processors. "Strix Halo" features one or two of the same 4 nm "Zen 5" CCDs featured on the "Granite Ridge" desktop and "Fire Range" mobile processors, but connected to a much larger I/O die, as we mentioned.

Intel has reportedly chosen the TSMC 4 nm EUV foundry node for its next generation Arc Xe2 discrete GPUs based on the "Battlemage" graphics architecture. This would mark a generational upgrade from the Arc "Alchemist" family, which Intel built on the TSMC 6 nm DUV process. The TSMC N4 node offers significant increases in transistor densities, performance, and power efficiency over the N6, which is allowing Intel to nearly double the Xe cores on its largest "Battlemage" variant in numerical terms. This, coupled with increased IPC, clock speeds, and other features, should make the "Battlemage" contemporary against today's AMD RDNA 3 and NVIDIA Ada gaming GPUs. Interestingly, TSMC N4 isn't the most advanced foundry node that the Xe2 "Battlemage" is being built on. The iGPU powering Intel's Core Ultra 200V "Lunar Lake" processor is part of its Compute tile, which Intel is building on the more advanced TSMC N3 (3 nm) node.

ASUS announced a press event on July 17 to launch at least nine notebook designs powered by AMD Ryzen AI 300 series "Strix Point" mobile processors. All these notebooks are AI PCs that meet Microsoft Copilot+ requirements. Each of the 9 designs will have several variants based on the processor model, discrete graphics, and other hardware differentiators, making up dozens of individual SKUs. The AMD "Strix Point" mobile processor is based on a 4 nm monolithic die. It combines a 12-core/24-thread CPU based on a combination of "Zen 5" and "Zen 5c" cores, a 50 TOPS-class NPU, and a powerful iGPU based on the RDNA 3.5 graphics architecture, with 16 compute units.

Among the notebook designs ASUS plans to announce on July 17 are the ROG Zephyrus G16 (GA605), the TUF Gaming A14 (FA401), the TUF Gaming A16 (FA608), the Zenbook S16 (UM5606), Vivobook S14 (M5406), Vivobook S16 (M5506 and M5606), ProArt P16 (HN7606) and ProArt PX13 (HN7306). With these, ASUS is covering pretty much all its notebook market segments, including enthusiast gaming, performance gaming, boutique ultraportability, mainstream, and creative professional.

AMD's upcoming Ryzen 9000 series "Granite Ridge" desktop processors based on the "Zen 5" microarchitecture will see a slight improvement in memory overclocking capabilities. A chiplet-based processor, just like the Ryzen 7000 "Raphael," "Granite Ridge" combines one or two "Zen 5" CCDs, each built on the TSMC 4 nm process, with a client I/O die (cIOD) built on the 6 nm node. The cIOD of "Granite Ridge" appears to be almost identical to that of "Raphael." This is the chiplet that contains the processor's DDR5 memory controllers.

As part of the update, Ryzen 9000 "Granite Ridge" should be able to run DDR5-6400 with a 1:1 ratio between the MCLK and FCLK domains. This is a slight increase from the DDR5-6000 sweetspot speed of Ryzen 7000 "Raphael" processors. AMD is reportedly making it possible for motherboard manufacturers and prebuilt OEMs to enable a 1:2 ratio, making it possible to run high memory speeds such as DDR5-8000, although performance returns with memory speeds would begin to diminish beyond the DDR5-6400 @ 1:1 setting. Memory manufacturers should launch a new wave of DDR5 memory kits with AMD EXPO profiles for DDR5-6400.

AMD's Ryzen 9000 "Granite Ridge" family of Socket AM5 desktop processors based on the "Zen 5" microarchitecture arrive in July, with four processor models in the lead—the 9950X 16-core, the 9900X 12-core, the 9700X 8-core, and the 9600X 6-core. AMD is building the CCDs (CPU core dies) of these processors on the slightly newer 4 nm foundry node, compared to the 5 nm node that the Ryzen 7000 series "Raphael" processors based on "Zen 4" are built on; and generally lowered the TDP values of all but the top 16-core part. The company is reportedly reconsidering these changes, particularly in wake of company statements that the 9000X series may not beat the 7000X3D series in gaming performance, which may have sullied the launch, particularly for gamers.

From the company's Computex 2024 announcement of the Ryzen 9000 series, the 9950X has the same 170 W TDP as its predecessor, the 7950X. The 9900X 12-core part, however, comes with a lower 120 W TDP compared to the 170 W of the 7900X. Things get interesting with the 8-core and 6-core parts. Both the 9700X 8-core, and the 9600X 6-core chips come with 65 W TDP. The 9700X succeeds the 7700X, which came with a 105 W TDP, while the 9600X succeeds the 7600X that enjoys the same 105 W TDP. The TDP and package power tracing (PPT) values of an AMD processor are known to affect CPU boost frequency residence, particularly in some of the higher core-count SKUs. Wccftech reports that AMD is planning to revise the specifications of at least the Ryzen 7 9700X.

A new startup emerged out of stealth mode today to power the next generation of generative AI. Etched is a company that makes an application-specific integrated circuit (ASIC) to process "Transformers." The transformer is an architecture for designing deep learning models developed by Google and is now the powerhouse behind models like OpenAI's GPT-4o in ChatGPT, Anthropic Claude, Google Gemini, and Meta's Llama family. Etched wanted to create an ASIC for processing only the transformer models, making a chip called Sohu. The claim is Sohu outperforms NVIDIA's latest and greatest by an entire order of magnitude. Where a server configuration with eight NVIDIA H100 GPU clusters pushes Llama-3 70B models at 25,000 tokens per second, and the latest eight B200 "Blackwell" GPU cluster pushes 43,000 tokens/s, the eight Sohu clusters manage to output 500,000 tokens per second.

Why is this important? Not only does the ASIC outperform Hopper by 20x and Blackwell by 10x, but it also serves so many tokens per second that it enables an entirely new fleet of AI applications requiring real-time output. The Sohu architecture is so efficient that 90% of the FLOPS can be used, while traditional GPUs boast a 30-40% FLOP utilization rate. This translates into inefficiency and waste of power, which Etched hopes to solve by building an accelerator dedicated to power transformers (the "T" in GPT) at massive scales. Given that the frontier model development costs more than one billion US dollars, and hardware costs are measured in tens of billions of US Dollars, having an accelerator dedicated to powering a specific application can help advance AI faster. AI researchers often say that "scale is all you need" (resembling the legendary "attention is all you need" paper), and Etched wants to build on that.