cdawallyou do understand that C2Q hae a massive cache because they would take a massive performance hit if they had to send more and more data across the already clogged FSB to the ram so intel keeps jacking more cache on the chips to counteract this, however AMD uses HT and an onboard mem controller so it doesn't have to send data packets across the bus to talk to the ram it links directly thus AMD chips can have a much smaller cache and not suffer a performance hit

eidairaman1L2 Cache is a big Data Dump, all it allows is for the CPU to be off the FSB much longer, id be surprised if AMD dropped on Bigger L2 and see what it does even with the HT bus- see how much difference it makes- if any at all.

eidairaman1ya both companies are goin L3, but TBH, L3 Cache on the P4s didnt do much, im sure if the FSB was Pumped on the Gallatin (NorthwoodL3) Core, despite having the L3 cache the gallatin was faster than the Prescott- technically clock for clock the northwood ran much cooler and was alot faster, Hopefully AMD gets things right aswell, as it seems this line of CPus are their first with L3.

Musselswell if intel can beat AMD clock for clock atm without an integrated controller, they have some room for teething troubles with L3 cache on nehalem - at worst, it'll just even the ground.

That said, i'm not saying AMD cant catch up i just doubt it.