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Intel Xeon 5030

2
Cores
4
Threads
95 W
TDP
2.667 GHz
Frequency
N/A
Boost
Dempsey
Codename
Socket 771
Socket
Intel Socket 771
Intel Socket 771
The Intel Xeon 5030 was a server/workstation processor with 2 cores, launched in May 2006, at an MSRP of $156. It is part of the Xeon lineup, using the Dempsey architecture with Socket 771. Thanks to Intel Hyper-Threading the core-count is effectively doubled, to 4 threads. To further increase overall system performance, up to two Xeon 5030 CPUs can link up in a multi-processor (SMP) configuration. Xeon 5030 has 2 MB of L2 cache per core and operates at 2.667 GHz. Intel is building the Xeon 5030 on a 65 nm production process using 376 million transistors. The multiplier is locked on Xeon 5030, which limits its overclocking capabilities.
With a TDP of 95 W, the Xeon 5030 consumes a good deal of power, so decent cooling is needed. Intel's processor supports DDR2 memory. ECC memory is supported, too, which is an important capability for mission-critical systems, to avoid data corruption. This processor lacks integrated graphics, you might need a graphics card.
The SSE4 instruction set is not supported, which can cause problems with modern games, as they require that capability.

Physical

Socket: Intel Socket 771
Foundry: Intel
Process Size: 65 nm
Transistors: 376 million
Die Size: 2x 81 mm²
Package: FC-LGA6
tJMax: 67°C

Processor

Market: Server/Workstation
Production Status: End-of-life
Release Date: May 23rd, 2006
Launch Price: $156
Part#: SL96E

Performance

Frequency: 2.667 GHz
Turbo Clock: N/A
Base Clock: 166 MHz
Multiplier: 16.0x
Multiplier Unlocked: No
Voltage: 1.4 V
TDP: 95 W

Architecture

Codename: Dempsey
Generation: Xeon
(Dempsey)
Memory Support: DDR2
ECC Memory: Yes
Chipset: Intel E7520

Core Config

# of Cores: 2
# of Threads: 4
SMP # CPUs: 2
Integrated Graphics: N/A

Cache

Cache L1: 16 KB (per core)
Cache L2: 2 MB (per core)

Features

  • MMX
  • SSE
  • SSE2
  • SSE3
  • HTT
  • Intel 64
  • XD bit
  • VT
  • EIST

Notes

Level 1 caches arranged as 16KBytes L1 Data, 12Kuops L1 Trace cache per core.
Dec 23rd, 2024 19:50 EST change timezone

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