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Alder Lake CPUs common discussion

lexluthermiester said:
My question is why disable AVX512 at all? What's the technical purpose? Kinda stupid...
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Intel accidentally confirmed that AVX-512 would not work on Alder Lake because its Gracemont Efficiency cores simply don't support AVX-512.

https://hothardware.com/news/rumor-claims-intel-will-forcibly-disable-avx-512-on-alder-lake

They might be able to do a bios/windows update to fix it somehow

The weird thing is, the high end CPU's will have no AVX512, but the P core only ones could end up being able to use it as they have no E cores.
 
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Tigger said:
Intel accidentally confirmed that AVX-512 would not work on Alder Lake because its Gracemont Efficiency cores simply don't support AVX-512.

https://hothardware.com/news/rumor-claims-intel-will-forcibly-disable-avx-512-on-alder-lake

They might be able to do a bios/windows update to fix it somehow

The weird thing is, the high end CPU's will have no AVX512, but the P core only ones could end up being able to use it as they have no E cores.
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That doesn't really explain much about why those instructions, which were deliberately built-in, are being disabled. Why do they need to be?
 
My guess its reserved for the 13th Gen HEDT or 12th Gen XEON and Intel doesn't want to give buyers that need AVX512 to just use a i9 Alder Lake instead for a lot cheaper. That or the AVX512 set is somehow actually broken at the core and will give invalid results on scientific applications. We are all guessing why Intel has it on Alder Lake in the first place if it isn't supported. We can only guess.
 
ir_cow said:
My guess its reserved for the 13th Gen HEDT or 12th Gen XEON and Intel doesn't want to give buyers that need AVX512 to just use a i9 Alder Lake instead for a lot cheaper. That or the AVX512 set is somehow actually broken at the core and will give invalid results on scientific applications. We are all guessing why Intel has it on Alder Lake in the first place if it isn't supported. We can only guess.
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Though that idea has some plausibility, it really wouldn't make much sense either.
 
+1 to the thread director not being able to properly deal with it yet.

Gracemont supports AVX, AVX2, and AVX-VNNI but not avx 512. It's the most probable reason -- that something is not working right when deciding which cores to use during avx.
 
lexluthermiester said:
Though that idea has some plausibility, it really wouldn't make much sense either.
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when did market artificial market segmentation ever make sense to a consumer? :p
 
phanbuey said:
Gracemont supports AVX, AVX2, and AVX-VNNI but not avx 512. It's the most probable reason -- that something is not working right when deciding which cores to use during avx.
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But again, core selection can be handled programmatically, so why disable it instead of releasing a patch that just fixes the core selection problem? It would take all of two lines of code to instruct the Windows scheduler to select a Pcore when a call to the AVX512 instruction set is made.
 
lexluthermiester said:
But again, core selection can be handled programmatically, so why disable it instead of releasing a patch that just fixes the core selection problem? It would take all of two lines of code to instruct the Windows scheduler to select a Pcore when a call to the AVX512 instruction set is made.
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Well that's the assumption... 'can be handled programmatically' - but will it? is it at all times? does the CPU crash when the instruction is sent without special programmatic care? what about virtual machines and cloud providers / hadoop clusters that use ISA-L/ kernel virtualization that can mask cores? Legacy software in universities? -- do they have to rewrite software or will it just take a dirt nap when it tries to use a gracemont core? There's just so many failure points for a mass produced product that's going to be sitting in a poorly optimized/supported dell somewhere - especially since legacy code that would crash it is already out and in use.

It's such a perfect setup for a small disaster and bad publicity, so Intel probably decided to only release chips that are 100% stable under all circumstances and deal with customers that need avx 512 using a different product line.
 
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lexluthermiester said:
No, the instructions are dumped, an error code is generated and sent back to the OS.
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Correct, sure then the software crashes....

And you have a CPU that can sort of support AVX-512.

It's definitely technically possible. It's just a question of did they have enough time to make this implementation good enough. And the answer is no - it was clearly in the works and got dropped.

lexluthermiester said:
Legacy software would not call the AVX512 instructions and would not be affected.
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Why not? There's software out now (basically all AVX-512 enabled software) that is running 512 that isn't AL optimized = legacy.
 
lexluthermiester said:
No, the software just stops. There is a difference between a software crash and a halt-on-error.
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Not the point. Depends on how it's coded. You don't want your software stopping whether you catch the error or not. Stopping because of an error is synonymous with a crash and would be treated in the news as such.

Point is CPU can't support AVX-512 at the hardware level 100% and Intel can't control the software that will run on these chips, so they have to say that it doesn't support it. Or they risk lawsuits, bad press, customer dissatisfaction, loss of shareholder value -> lawsuits from shareholders vs management etc. etc.
 
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phanbuey said:
Not the point. Depends on how it's coded. You don't want your software stopping whether you catch the error or not. Stopping because of an error is synonymous with a crash and would be treated in the news as such.

Point is CPU can't support AVX-512 at the hardware level 100% and Intel can't control the software that will run on these chips, so they have to say that it doesn't support it. Or they risk lawsuits, bad press, customer dissatisfaction, loss of shareholder value -> lawsuits from shareholders vs management etc. etc.
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They possibly can fix it in the future if they choose to. The fact for now that they are forcing motherboard makers to bios disable it, means they might not have no intention of re enabling it in the future.
 
lexluthermiester said:
Not true. And, yes, yes you do.
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I'll be sure to tell my boss that if one of our apps goes down. "But sir, it caught the exception - and logged it successfully before it kicked all those doctors out in the middle of their medical visits!"

While we are at it, we should rename Crash to Desktop (CTD) to Desired Successful Halt On Error (DSHOE)

Tigger said:
They possibly can fix it in the future if they choose to. The fact for now that they are forcing motherboard makers to bios disable it, means they might not have no intention of re enabling it in the future.
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Right -- agreed. To be fair wasn't ever 'fully' functional -- you had to disable E cores it to work and only a few makers supported it (no msi). It's basically a half finished feature that some motherboards found a bios hack for.
 
phanbuey said:
I'll be sure to tell my boss that if one of our apps goes down. "But sir, it caught the exception - and logged it successfully before it kicked all those doctors out in the middle of their medical visits!"

While we are at it, we should rename Crash to Desktop (CTD) to Desired Successful Halt On Error (DSHOE)
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I think you misunderstood what I was describing. And since you insist on being unpleasant...
 
phanbuey said:
I'll be sure to tell my boss that if one of our apps goes down. "But sir, it caught the exception - and logged it successfully before it kicked all those doctors out in the middle of their medical visits!"

While we are at it, we should rename Crash to Desktop (CTD) to Desired Successful Halt On Error (DSHOE)


Right -- agreed. To be fair wasn't ever 'fully' functional -- you had to disable E cores it to work and only a few makers supported it (no msi). It's basically a half finished feature that some motherboards found a bios hack for.
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Might have to check my bios to see if it is still there, or gone with latest bios. I keep my board up to date as the platform is so new.
 
lexluthermiester said:
No, the instructions are dumped, an error code is generated and sent back to the OS.
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More exactly, an invalid opcode exception is generated. The exception handler (interrupt handler), if it exists, can then emulate the AVX-512 instruction using other available instructions, then return control to the thread that caused the exception. Even if that slows the program down to nearly zero, it prevents it from crashing.

The other alternative is to suspend the thread and make sure it continues its execution on a P core.

That's the theory at least, all modern CPUs can do that, but I don't know if it has ever been implemented.
 
lexluthermiester said:
I think you misunderstood what I was describing. And since you insist on being unpleasant...
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I was legitimately trying to be funny by showing the point from a business user point of view. Since my entire angle is that this is a business decision rather than an engineering decision.

Being unpleasant is one of my features though, so there's that.
 
phanbuey said:
I was legitimately trying to be funny by showing the point from a business user point of view. Since my entire angle is that this is a business decision rather than an engineering decision.

Being unpleasant is one of my features though, so there's that.
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Ah, I took that very differently. Fair enough.

Wirko said:
More exactly, an invalid opcode exception is generated.
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Yes. I was trying to keep the description simple so that non-coders would understand the idea.


The only thing I can think of that legitimately makes sense is that there is some form of power-gating flaw in the AVX512 section of the die that causes more power draw for that section than is needed and disabling it is the only fix. Otherwise, disabling make no sense whatsoever and it's just dumb.
 
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lexluthermiester said:
Ah, I took that very differently. Fair enough.


Yes. I was trying to keep the description simple so that non-coders would understand the idea.


The only thing I can think of that legitimately makes sense is that there is some form of power-gating flaw in the AVX512 section of the die that causes more power draw for that section than is needed and disabling it is the only fix. Otherwise, disabling make no sense whatsoever and it's just dumb.
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If you look at links here Lex, it actually seems to use less power with AVX-512 enabled.
https://www.techpowerup.com/forums/...-on-alder-lake-processors.290460/post-4676108
 
Placed a tentative order on 12100F + 16GB DDR4 3200 MHz kit.

Not finalizing it, as we don't have budget mobos yet, and not willing to splurge on Z690. If I understand right H610 only supports single channel and no XMP? That means basically to avoid it beyond office applications and aim for H670 or B660?
 
ExcuseMeWtf said:
Placed a tentative order on 12100F + 16GB DDR4 3200 MHz kit.

Not finalizing it, as we don't have budget mobos yet, and not willing to splurge on Z690. If I understand right H610 only supports single channel and no XMP? That means basically to avoid it beyond office applications and aim for H670 or B660?
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The upcoming MSI B/H motherboards are looking good
 
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