You are missing a significant point. Ryzen 5000's IOD is made on the old 12nm process of Glofo. It exists since Ryzen 3000 and hasn't been power optimized since then. Ryzen 7000 uses a new 6nm low power IOD. That's a completely different story.
No, it isn't a completely differnt story, but a relatively minor change. I/O power does not scale with node shrinks in the same way compute power does, and the IOD is almost entirely I/O and very little compute. There will be power savings from the upcoming IOD node shrink, but they won't be ground-breaking, and they won't come anywhere near the power level of any in-die or die-to-die interconnect - that simply isn't physically possible. The majority of power use "for the IOD" is power it needs to use to transmit the signals it generates through whatever wires those signals need to pass through - whether those are in the CPU package (IF) or motherboard (PCIe, DRAM, etc.). (This of course also means that IF power is spread roughly equally across the IOD and CCDs, as it's a bidirectional link with transmitters and receivers on both ends.) Which is an inherent inefficiency of IF through the CPU package/substrate: sending signals through a medium like this is
vastly more energy intensive than doing the same through silicon - orders of magintude higher. For AMD's CPUs to rid themselves of this (IMO relatively minor) Achilles heel, they need to switch to a more advanced form of packaging, such as LSI (TSMC's equivalent to Intel's EMIB) to eliminate the need to send signals through the substrate.
I really, really hope that AMD starts moving to more advanced packaging sooner rather than later, especially as Intel is already well on their way with Meteor Lake. LSI and similar interconnects allow for combining the best properties of monolithic
and MCM designs, with the only disadvantage being packaging complexity (which typically, at least early on, means higher costs and lower yields). But the tech exists, and AMD needs to start taking advantage of it sooner rather than later.
TSMC' N6 node is not optimal. They have shrinks - N5/N4 which are a generation ahead and will give even better thermals / lower power consumption.
Using a cutting-edge node for a die that's nearly exclusively I/O would be immensely wasteful and bring very few real-world benefits with it - I/O needs a lot of die area (which, like power, doesn't tend to shrink with node shrinks like logic area does) meaning you'll be spending a lot of wafers on a very expensive node making something that'll at best be marginally better than a slightly larger, much cheaper version of the same die. A more dense silicon lithography node does not in any way reduce the voltage or power necessary to transmit a high bandwidth signal through fiberglass-embedded copper wires. Better designs in silicon can (and do!) both increase bandwidth and reduce power, but those don't tend to scale much with node changes either, but with further design effort spent on refining the architectures involved. And, crucially, AMD already needs to increase IF clock speeds to match DDR5 clock speeds, which will most likely eat up whatever efficiency gains they have manged since the previous version of IF.
All of his articles for a good while now recently have been poorly researched and misleading if not outright false garbage. He's either gotten too lazy or too technologically illiterate to handle his current position IMO.
