The HPC research projects DEEP-SEA, IO-SEA and RED-SEA are wrapping up this month after a three-year project term. The three projects worked together to develop key technologies for European Exascale supercomputers, based on the Modular Supercomputing Architecture (MSA), a blueprint architecture for highly efficient and scalable heterogeneous Exascale HPC systems. To achieve this, the three projects collaborated on system software and programming environments, data management and storage, as well as interconnects adapted to this architecture. The results of their joint work will be presented at a co-design workshop and poster session at the EuroHPC Summit (Antwerp, 18-21 March, www.eurohpcsummit.eu).

The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that EPAC 1.0 RISC-V Test Chip samples were delivered to EPI and initial tests of their operation were successful.

One key segment of EPI activities is to develop and demonstrate fully European-grown processor IPs based on the RISC-V Instruction Set Architecture, providing power-efficient and high-throughput accelerator cores named EPAC (European Processor Accelerators).

Chiplet design of processors is getting more popular due to many improvements and opportunities it offers. Some of the benefits include lower costs as the dies are smaller compared to one monolithic design, while you are theoretically able to stitch as much of the chiplets together as possible. During the ISSCC 2020 conference, CEA-Leti, a French research institute, created a 96 core CPU made from six 3D stacked 16 core chiplets. The chip is created as a demonstration of what this modular approach offers and what are the capabilities of the chiplet-based CPU design.

The chiplets are manufactured on the 28 nm FD-SOI manufacturing process from STMicroelectronics, while the active interposer die below them that is connecting everything is made using the 65 nm process. Each one of the six dies is housing 16 cores based on MIPS Instruction Set Architecture core. Each chiplet is split into four 4-core clusters that make up for a total of 16 cores per chiplet. When it comes to the core itself, it is a scalar MIPS32v1 core equipped with 16 KiB of L1 instruction and an L1 data cache. For L2 cache, there is 256 KiB per cluster, while the L3 cache is split into four 1 MiB tiles for the whole cluster. The chiplets are stacked on top of an active interposer which connects the chiplets and provides external I/O support.

Asia is set to get its very own edition of the International Consumer Electronics Show (CES), from 2015. CEA, the organizers of the International CES, announced that the inaugural CES Asia expo will be held between May 25 and May 27, 2015. Shanghai, China, will be the seat of this event, with the event being hosted at the Shanghai New International Expo Center (SNIEC.) The event is a partnership between CEA and Shanghai-based event organizer Intex Shanghai.

Industry experts don't see this as CEA's attempt to compete with Computex, a PC industry-centric expo held each June in Taipei. CES, in its typical early January annual edition held in Las Vegas, USA, sees one of the consumer electronics industry's biggest gatherings, with manufacturers of not just PC hardware, but also home entertainment, automobile electronics, digital photography, mobiles and tablets, among others; meet, to show off their latest. CES Asia could serve as an important platform for China's emerging global brands in the consumer electronics industry, and make it easier for brands from across Asia to converge at a more convenient location than the US.

Seagate Technology plc (NASDAQ: STX) today announced that the company has been named an International CES Innovations 2014 Design and Engineering Awards Honoree for its Business Storage 8-bay rackmount network attached storage solution. Seagate Business Storage delivers centralized backup, data protection and remote access to critical information for small and medium-sized business organizations (SMBs) in capacities ranging from 4 to 32 terabytes.

"Seagate is pleased to be honored by the CEA for outstanding design and innovation of the industry's first hot-swappable 8-bay rackmount server in a 1U form factor," said Scott Horn, vice president of global marketing for Seagate. "This project includes not only a groundbreaking hardware design but also a new proprietary NAS OS to simplify storage management and monitoring for our small business customers. This product is only the latest in a new portfolio that further strengths Seagate's commitment to the small business space."

The Consumer Electronics Association (CEA) today announced that the 2013 International CES will feature a record amount of exhibit space, with the show floor totaling more than 1.87 million net square feet. The previous record was 1.862 million net square feet at the 2012 CES. Owned and produced by CEA, the 2013 CES, the world's largest innovation event, is scheduled Tuesday, January 8-Friday, January 11, 2013 in Las Vegas, Nevada.

"With the largest show floor in history, more innovative technologies and services will launch at the 2013 CES than anywhere else in the world," said Gary Shapiro, president and CEO, CEA. "From cloud-based services, advancements in digital health, connected vehicle technologies, the latest apps, flexible devices and beyond, the innovations unveiled at the 2013 CES will create new jobs and further economic growth around the world."