AMD Confirms Ryzen 9 7950X3D and 7900X3D Feature 3DV Cache on Only One of the Two Chiplets
AMD today announced its new Ryzen 7000X3D high-end desktop processors to much fanfare, with availability slated for February 2023, you can read all about them in our older article. In our coverage, we noticed something odd about the cache sizes of the 12-core 7900X3D and 16-core 7950X3D. Whereas the 8-core, single-CCD 7800X3D comes with 104 MB of total cache (L2+L3), which works out to 1 MB L2 cache per core and 96 MB of L3 cache (32 MB on-die + 64 MB stacked 3DV cache); the dual-CCD 7900X3D and 7950X3D was shown with total caches of 140 MB and 144 MB, while they should have been 204 MB or 208 MB, respectively.
In our older article, we explored two possibilities—one that the 3DV cache is available on both CCDs but halved in size for whatever reason; and the second more outlandish possibility that only one of the two CCDs has stacked 3DV cache, while the other is a normal planar CCD with just the on-die 32 MB L3 cache. As it turns out, the latter theory is right! AMD put out high-resolution renders of the dual-CCD 7000X3D processors, where only one of the two CCDs is shown having the L3D (L3 cache die) stacked on top. Even real-world pictures of the older "Zen 3" 3DV cache CCDs from the 5800X3D or EPYC "Milan-X" processors show CCDs with 3DV caches having a distinct appearance with dividing lines between the L3D and the structural substrates over the regions of the CCD that have the CPU cores. In these renders, we see these lines drawn on only one of the two CCDs.
In our older article, we explored two possibilities—one that the 3DV cache is available on both CCDs but halved in size for whatever reason; and the second more outlandish possibility that only one of the two CCDs has stacked 3DV cache, while the other is a normal planar CCD with just the on-die 32 MB L3 cache. As it turns out, the latter theory is right! AMD put out high-resolution renders of the dual-CCD 7000X3D processors, where only one of the two CCDs is shown having the L3D (L3 cache die) stacked on top. Even real-world pictures of the older "Zen 3" 3DV cache CCDs from the 5800X3D or EPYC "Milan-X" processors show CCDs with 3DV caches having a distinct appearance with dividing lines between the L3D and the structural substrates over the regions of the CCD that have the CPU cores. In these renders, we see these lines drawn on only one of the two CCDs.