SMART Modular Technologies, Inc. ("SMART"), a division of SGH and a global leader in memory solutions, solid-state drives, and hybrid storage announces its new Compute Express Link (CXL) Memory Module, the XMM CXL memory module. SMART's new DDR5 XMM CXL modules helps boost server and data center performance by enabling cache coherent memory to be added behind the CXL interface, further expanding big data processing capabilities beyond the current 8-channel/12-channel limitations of most servers.

The industry adoption of composable serial-attached memory architecture enables a whole new era for the memory module industry. Serial-attached memory adds capacity and bandwidth capabilities beyond main memory DIMM modules. Servers with XMM CXL modules can be dynamically configured for different applications and workloads without being shut down. Memory can be shared across nodes to meet throughput and latency requirements.

The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, today announced the release of the CXL 3.0 specification. The CXL 3.0 specification expands on previous technology generations to increase scalability and to optimize system level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains.

"Modern datacenters require heterogenous and composable architectures to support compute intensive workloads for applications such as Artificial Intelligence and Machine Learning - and we continue to evolve CXL technology to meet industry requirements," said Siamak Tavallaei, president, CXL Consortium. "Developed by our dedicated technical workgroup members, the CXL 3.0 specification will enable new usage models in composable disaggregated infrastructure."

Montage Technology, a leading data processing and interconnect IC design company, today announced that it has delivered the world's first Compute Express Link (CXL ) Memory eXpander Controller (MXC). The device is designed to be used in Add-in Cards (AIC), Backplanes or EDSFF memory modules to enable significant scaling of memory capacity and bandwidth for data-intensive applications such as high-performance computing (HPC) and artificial intelligence (AI). The MXC is a Type 3 CXL DRAM memory controller. The MXC supports and is compliant with both DDR4 & DDR5 JEDEC standards. It is also designed to the CXL 2.0 specification and supports PCIe 5.0 specification speeds. The MXC provides high-bandwidth and low-latency interconnect between the CPU and the CXL-based devices, allowing them to share memory for higher performance, reduced software stack complexity, and lower data center TCO.

Montage Technology's President, Stephen Tai said, "CXL is a key technology that enables innovative ways to do memory expansion and pooling which will play an important role in next-generation server platforms. I'm very excited that Montage is the first company in the industry to successfully deliver the MXC chip, which signals we are making a critical step towards advancing the CXL interconnect technology to the memory market." CXL Consortium's President, Siamak Tavallaei said, "The CXL Consortium is excited to see continued CXL specification adoption to enable technologies and solutions such as the CXL DRAM Memory eXpander Controller." Montage Technology is working closely with industry-leading memory manufacturers to deliver advanced memory products based on the CXL MXC and help develop a robust memory ecosystem around CXL.

The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, today announced the release of the CXL 2.0 specification. CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory - all while preserving industry investments by supporting full backwards compatibility with CXL 1.1 and 1.0.

"Datacenter architectures continue to evolve rapidly to support the growing demands of emerging workloads for Artificial Intelligence and Machine Learning, with CXL technology keeping pace to meet the performance and latency demands," said Barry McAuliffe, president, CXL Consortium. "Designed with breakthrough performance and easy adoption as guiding principles, the CXL 2.0 specification is a significant achievement from our dedicated technical work group members."