The mysterious Zen 6 "Morpheus" processor architecture was leaked accidentally by an AMD engineer's LinkedIn profile—news outlets picked up on this information last April. Naturally, Team Red's next priority is Zen 5—the latest reports suggest that two different chiplet designs are penciled in for mass production within the second quarter of 2024. Last September, insiders claimed that a proposed EPYC 9006 "Venice" CPU series was based on the sixth-gen microarchitecture. Everest/Olrak_29 has revealed various bits of speculative material regarding futuristic "Ryzen Client" processor designs since the start of 2024.

The latest postings to social media posit that AMD has selected an RDNA 5-based integrated graphics solution (possibly occupying a tile), thus "skipping RDNA 4" on their "Medusa" lineup of Ryzen Client processors. Leaked Microsoft documents revealed that its Xbox hardware design division was considering RDNA 5 for next-gen console specs. Medusa's CPU aspect is allegedly populated by Zen 6 "Morpheus" cores—as claimed in a January tweet. A new package design was also riffed on at the time: "Yes, I have teased this before...Medusa will use 2.5D interconnect with a much higher bandwidth," instead of a "traditional" multi-die design. Industry speculation has AMD's Zen 6 client architecture linked to a loose 2025/2026 launch window.

A couple of slides from AMD's internal presentation were leaked to the web by Moore's Law is Dead, referencing what's allegedly the next-generation "Zen 5" microarchitecture. Internally, the performance variant of the "Zen 5" core is referred to as "Nirvana," and the CCD chiplet (CPU core die) based on "Nirvana" cores, is codenamed "Eldora." These CCDs will make up either the company's Ryzen "Granite Ridge" desktop processors, or EPYC "Turin" server processors. The cores themselves could also be part of the company's next-generation mobile processors, as part of heterogenous CCXs (CPU core complex), next to "Zen 5c" low-power cores.

In broad strokes, AMD describes "Zen 5" as introducing a 10% to 15% IPC increase over the current "Zen 4." The core will feature a larger 48 KB L1D cache, compared to the current 32 KB. As for the core itself, it features an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage gets 6 ALUs, compared to the current 4. The floating point unit gets FP-512 capabilities. Perhaps the biggest announcement is that AMD has increased the maximum cores per CCX from 8 to 16. At this point we don't know if it means that "Eldora" CCD will have 16 cores, or whether it means that the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD is leveraging the TSMC 4 nm EUV node for "Eldora," the mobile processor based on "Zen 5" could be based on the more advanced TSMC 3 nm EUV node.

Hardware leaker, YuuKi_AnS, has briefly turned their attention away from all things Team Blue—their latest leak points to upcoming server-grade processors chez AMD. A Zen 6 core-based 9006 EPYC CPU series, codenamed "Venice," is expected to arrive within two to three years along with an all-new SP7 socket—this information seems to have been sourced from an unnamed server manufacturer's product roadmap. A partial view of said slide also reveals forthcoming equipment powered by Intel "Falcon Shore" and NVIDIA "Blackwell" GPU technologies.

As reported a couple of months ago, older insider info has AMD using "Weisshorn" as an in-house moniker for Zen 6 "Morpheus" architecture, destined for Venice CPUs—alleged to form part of a 2025/2026 EPYC lineup. YuuKi_AnS proposes that these will utilize either 12-channel or 16-channel DDR5 memory configurations—thus providing plenty of bandwidth across hundreds of Zen cores. Altogether very handy for cloud, enterprise, and HPC workloads—industry experts reckon that 384-core counts are feasible on single packages. Naturally, a Team Red timeline dictates that Zen 5 "Nirvana" is due before Zen 6 "Morpheus," so EPYC 9005 "Turin(-X)" and 8005 "Turin-Dense" lineups are (allegedly) up for a 2024-ish launch window on SP5 (LGA-6096) and SP6 (LGA 4094) socket types.

An AMD engineer inadvertently leaked the core codenames of the company's upcoming "Zen 5" and "Zen 6" microarchitectures. It's important to understand here what has been leaked. "Zen 5" and "Zen 6" are microarchitecture names, just like the current "Zen 4" and past "Zen 3" or older. AMD uses codenames for the CCD (CPU complex dies) based on these microarchitectures, which it shares between Ryzen client and EPYC enterprise processors. For example, the CCD codename for "Zen 3" is "Brekenridge," and for "Zen 4" it is "Durango." AMD also uses codenames for the CPU cores themselves. "Zen 3" CPU cores are codenamed "Cerebrus," and "Zen 4" CPU cores "Persphone." And now, the leak:

The CCD based on the upcoming "Zen 5" microarchitecture is codenamed "Eldora," and the "Zen 5" CPU core itself is codenamed "Nirvana." There's no codename for the CCD based on "Zen 6," but its CPU cores are codenamed "Morpheus." The "Zen 5" microarchitecture will be based on the 3 nm EUV foundry node; while "Zen 6" will be 2 nm EUV. The engineer in the screenshot is contributing to the power-management technology behind "Zen 5" and "Zen 6," and states that their work on "Zen 5" spanned January-December of 2022, which means the development phase of the next "Zen" architecture is probably complete, and the architecture is undergoing testing and refinement. It's also claimed that work on at least the power-management aspect of "Zen 6" has started from January 2023.