SK hynix Inc. announced today it has signed a non-binding preliminary memorandum of terms with the U.S. Department of Commerce to receive up to $450 million in proposed direct funding and access to proposed loans of $500 million as part of the CHIPS and Science Act for its investment to build a production base for semiconductor packaging in Indiana. Separately, SK hynix plans to seek from the U.S. Department of the Treasury a tax benefit equivalent of up to 25% of the qualified capital expenditures through the Investment Tax Credit program.

SK hynix said it deeply appreciates the U.S. government's support and will comply with the requirements for the remaining procedures until the proposed funding is finalized. The company also said that it will proceed with the construction of the Indiana production base as planned to meet the plan to provide AI memory products. Through this, it looks forward to contributing to build a more resilient supply chain of the global semiconductor industry.

Today, leading global fabless chipmaker MediaTek Inc., [joined by Indiana Governor Eric J. Holcomb, Deputy Secretary of Commerce Don Graves, Indiana Secretary of Commerce Bradley B. Chambers, and Purdue College of Engineering's Dr. Mung Chiang] announced their commitment to accept a state transition assistance package from the Indiana Economic Development Commission (IEDC) to support its very first Midwest semiconductor chip design center in West Lafayette, Indiana. MediaTek also shared its intention to create a new research partnership with Purdue to collaborate on engineering talent development and new research on next-generation computing and communications chip design. The news was shared with senior leaders, other international investors and policymakers assembled in National Harbor, Maryland for the 2022 SelectUSA Investment Summit.

This novel partnership in Indiana represents a new U.S. growth model for MediaTek USA; outside the traditional centers of gravity for chip design. "We believe strongly that being in Indiana means we'll have access to some of the best engineering talent in the world," said Dr. Kou-Hung Lawrence Loh, Corporate Senior Vice President of MediaTek Inc. and President of MediaTek USA, Inc. "Not just at Purdue, but West Lafayette is only four hours away from nearly a dozen of the top engineering schools in the country. In the post pandemic world, top candidates tell us they want to be closer to home, near family and they want to have a real house and great schools. Indiana offers all that and more."

Today, Intel is taking another step forward, with two new technology announcements: Intel Threat Detection Technology (Intel TDT), a set of silicon-level capabilities that will help the ecosystem detect new classes of threats, and Intel Security Essentials, a framework that standardizes the built-in security features across Intel processors. We are also announcing a strengthened academic partnership with Purdue University, to help accelerate the development and availability of cybersecurity talent.

Intel Threat Detection Technology leverages silicon-level telemetry and functionality to help our industry partners improve the detection of advanced cyberthreats and exploits. Today we are announcing the first two Intel Threat Detection Technology capabilities, including implementation plans by Microsoft and Cisco.

The first new capability is Accelerated Memory Scanning. Current scanning technologies can detect system memory-based cyberattacks, but at the cost of CPU performance. With Accelerated Memory Scanning, the scanning is handled by Intel's integrated graphics processor, enabling more scanning, while reducing the impact on performance and power consumption. Early benchmarking on Intel test systems show CPU utilization dropped from 20 percent to as little as 2 percent.

Researchers based on Purdue University have designed an intrachip cooling technology, which will likely pave the way for future generations of high performance 3D microprocessors. The research was part of a DARPA-funded commission for Purdue University's Birck Nanotechnology Center; a fundamental requirement stipulated by DARPA was the ability for this cooling system to handle chips generating 1 kW of heat per cm², more than 10x the amount current high-performance computers generate.

The new cooling system circulates an electrically insulated liquid coolant directly into electronic chips through an intricate series of tiny microchannels. This means that no longer will cooling systems be limited to the nowadays-employed conventional chip-cooling methods, which make use of finned metal plates called heat sinks. These are attached to computer chips to dissipate heat, but have a fundamental flaw: they do not remove heat efficiently enough for an emerging class of high-performance, 3D electronics, where too much heat hinders the performance of electronic chips or damages the tiny circuitry, especially in small "hot spots" that are located below the topmost layer of the chip.