Google Security Research team has just published its latest research on a fundamental flaw in the microcode patch verification system that affects AMD processors from "Zen 1" through "Zen 4" generations. The vulnerability stems from an inadequate hash function implementation in the CPU's signature validation process for microcode updates, enabling attackers with local administrator privileges (ring 0 from outside a VM) to inject malicious microcode patches, potentially compromising AMD SEV-SNP-protected confidential computing workloads and Dynamic Root of Trust Measurement systems. Google disclosed this high-severity issue to AMD on September 25, 2024, leading to AMD's release of an embargoed fix to customers on December 17, 2024, with public disclosure following on February 3, 2025; however, due to the complexity of supply chain dependencies and remediation requirements, comprehensive technical details are being withheld until March 5, 2025, allowing organizations time to implement necessary security measures and re-establish trust in their confidential compute environments.

AMD has released comprehensive mitigation measures through AGESA firmware updates across its entire EPYC server processor lineup, from the first-generation Naples to the latest Genoa-X and Bergamo architectures. The security patch, designated as CVE-2024-56161 with a high severity rating of 7.2, introduces critical microcode updates: Naples B2 processors require uCode version 0x08001278, Rome B0 systems need 0x0830107D, while Milan and Milan-X variants mandate versions 0x0A0011DB and 0x0A001244 respectively. For the latest Genoa-based systems, including Genoa-X and Bergamo/Siena variants, the required microcode versions are 0x0A101154, 0x0A10124F, and 0x0AA00219. These updates implement robust protections across all SEV security features - including SEV, SEV-ES, and SEV-SNP - while introducing new restrictions on microcode hot-loading capabilities to prevent future exploitation attempts.

AEWIN provides a series of performant Network Appliances and Edge Server powered by single AMD Zen 4c EPYC 8004 processor codenamed Siena. The latest AMD Siena CPU is produced with 5 nm manufacturing technology to have up to 64 cores (extreme density of 2CCX/CCD) and 225 W TDP with lower energy consumption compared to EPYC SP5. Siena SP6 CPU has the best performance per watt and is with the support of rich I/O and CXL 1.1.

SCB-1945 (1U) and SCB-1947A (2U) are two performant Network Appliances supporting 12x DDR5 sockets and 4x/8x PCIe Gen 5 slots for AEWIN self-design NICs with 1G to 100G copper/fiber interfaces (with/without bypass function) or other accelerators and NVMe SSDs. Both models provide the flexibility to change 2x front panel PCIe slots to 1x PCIe x16 slot for installing off-the-shelf add-on card for additional functions required. It can support 400G NIC card installed such as NVIDIA Mellanox PCIe 5.0 NIC.

Keen-eyed hardware tipster momomo_us this week spotted that an upcoming AMD data center "Siena Dense" CPU has received verification, in the general sense, for SATA and PCI support - courtesy of the Serial ATA International Organization (SATA-IO). The information dump was uploaded to SATA-IO's online database on April 6 of this year - under the heading: "AMD EPYC 8004 Series Processors." As covered by TPU mid-way through this month the family of enterprise-grade processors, bearing codename Siena, is expected to be an entry-level alternative to the EPYC Genoa-X range, set for launch later in 2023.

The EPYC Siena series is reported to arrive with a new socket type - SP6 (LGA 4844) - which is said to be similar in size to the older Socket SP3. The upcoming large "Genoa-X" and "Bergamo" processors will sit in the already existing Socket SP5 (LGA 6096) - 2022's EPYC Genoa lineup makes use of it already. AMD has not made its SP6 socket official to the public, but industry figures have been informed that it can run up to 64 "Zen 4" cores. This new standard has been designed with more power efficient tasks in mind - targeting intelligent edge and telecommunication sectors. The smaller SP6 socket will play host to CPUs optimized for as low as 70 W operation, with hungrier variants accommodated up to 225 W. This single platform solution is said to offer 6-channel memory, 96 PCIe Gen 5.0 lanes, 48 lanes for CXL V1.1+, and 8 PCIe Gen 3.0 lanes.

The second-hand market in China is always full of gems, but we never expected to see an unreleased 5 nm 96-core EPYC 9684X Genoa-X CPU with 1152 MB of L3 cache. According to the seller, the CPU is "almost new" and in working condition.

In case you missed it earlier, AMD is working on 5 nm Genoa-X EPYC CPUs which will feature up to 96 Zen 4 cores in 5 nm with over 1 GB of L3 cache per socket. These are scheduled to release this year, optimized for technical computing and databases. AMD is also working on Siena CPUs, which should also come this year, featuring up to 64 Zen 4 cores with optimized performance-per-watt, meant for intelligent edge and telco markets.