The Biden administration is set to announce new, targeted restrictions on China's semiconductor industry, focusing primarily on emerging chip manufacturing equipment companies rather than broad industry-wide limitations. According to Bloomberg, these new restrictions are supposed to take effect on Monday. The new rules will specifically target two manufacturing facilities owned by Semiconductor Manufacturing International Corp. (SMIC) and will add select companies to the US Entity List, restricting their access to American technology. However, most of Huawei's suppliers can continue their operations, suggesting a more mild strategy. The restrictions will focus on over 100 emerging Chinese semiconductor equipment manufacturers, many of which receive government funding. These companies are developing tools intended to replace those currently supplied by industry leaders such as ASML, Applied Materials, and Tokyo Electron.

The moderated approach comes after significant lobbying efforts from American semiconductor companies, who argued that stricter restrictions could disadvantage them against international competitors. Major firms like Applied Materials, KLA, and Lam Research voiced concerns about losing market share to companies in Japan and the Netherlands, where similar but less stringent export controls are in place. Notably, Japanese companies like SUMCO are already seeing the revenue impacts of Chinese independence. Lastly, the restrictions will have a limited effect on China's memory chip sector. The new measures will not directly affect ChangXin Memory Technologies (CXMT), a significant Chinese DRAM manufacturer capable of producing high-bandwidth memory for AI applications.

According to a recent report from Nikkei, China has claimed the number one spot as the single highest spender on chipmaking tools. As the data from SEMI highlights, China spent a whopping $25 billion on key semiconductor tools in the first half of 2024, more than the US, Taiwan, and South Korea combined. And the train of acceleration for the Chinese semiconductor industry doesn't seem to be slowing down, as the country is expected to spend more than $50 billion for the entire year 2024. However, this equipment is not precisely leading-edge, as Chinese companies are under Western sanctions and are unable to source advanced EUV lithography tools for making sub-7 nm chips.

Most of the spending is allocated to mature node chipmaking facilities. These so-called "second tier" companies are driving the massive expenditures, and they are plentiful. Nikkei reports that there are at least ten firms that operate with mature nodes like 10/12/16 nm nodes. Being the biggest spender, China is also one of the primary revenue sources for many companies. For the US chipmaking tool companies like Applied Materials, Lam Research, and KLA, Chinese purchases accounted for 32%, 39%, and 44% of their latest quarterly revenue, respectively. Tokyo Electron recorded orders to China accounting for 49.9% of its revenues in June, while the Netherlands giant ASML also attributed 49%. Perhaps even more interesting is the expected outlook for 2025, which shows no signs of slowing down. The Chinese semiconductor industry must establish complete self-sufficiency, and massive capital expenditures are expected to continue.

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

Tokyo Electron announced that its development team at Tokyo Electron Miyagi—the development and manufacturing site for its plasma etch systems—has developed an innovative etch technology capable of producing memory channel holes in advanced 3D NAND devices with a stack of over 400 layers. The new process developed by the team has brought dielectric etch application to the cryogenic temperature range for the first time, producing a system with exceptionally high etch rates.

The innovative technology not only enables a 10-µm-deep etch with a high aspect ratio in just 33 minutes, but also can reduce the global warming potential by 84% compared with previous technologies. The geometry of the etched structure is quite well-defined as shown in the figure 1. Potential innovations enabled by this technology will spur creation of 3D NAND flash memory with even larger capacity.