OpenSIL is an open-source CPU initialization framework project that seeks to replace on-chip initialization microcode, such as AGESA, across both client- and server processors. AMD looks to implement OpenSIL as it makes its AMD EPYC processors more friendly to large customers that want to take control of this aspect of the processor. Since its open-sourcing in June 2023, AMD has come up with reference motherboards implementing OpenSIL, as well as modifying a Supermicro server motherboard to the architecture, to demo at conferences. AMD firmware engineer Paul Grimes presented the company's progress with implementing OpenSIL, at the OSFC conference, in Germany. It's been known that AMD is targeting a 2025-26 timeline for OpenSIL to hit product, but AMD put out specifics, such as its next-generation "Venice" server processor supporting OpenSIL.

"Venice" is codename for an AMD EPYC server processor generation succeeding "Turin." It is built on the future "Zen 6" microarchitecture, and AMD could at least unveil the processor some time in 2025, if not mass-produce it. late-2024 thru 2025 could see the company ramp up "Turin" and other server processors implementing "Zen 5." That's not all, AMD plans to being OpenSIL even to client processors, with the generation of Ryzen processors based on "Zen 6." This will see the AGESA microcode replaced by a first-party firmware from AMD based on OpenSIL, which PC OEMs will be able to customize. The biggest impact of this change will be felt in the commercial notebook and commercial desktop segments, where large organizations can take greater control over the chip initialization firmware.

Hardware leaker, YuuKi_AnS, has briefly turned their attention away from all things Team Blue—their latest leak points to upcoming server-grade processors chez AMD. A Zen 6 core-based 9006 EPYC CPU series, codenamed "Venice," is expected to arrive within two to three years along with an all-new SP7 socket—this information seems to have been sourced from an unnamed server manufacturer's product roadmap. A partial view of said slide also reveals forthcoming equipment powered by Intel "Falcon Shore" and NVIDIA "Blackwell" GPU technologies.

As reported a couple of months ago, older insider info has AMD using "Weisshorn" as an in-house moniker for Zen 6 "Morpheus" architecture, destined for Venice CPUs—alleged to form part of a 2025/2026 EPYC lineup. YuuKi_AnS proposes that these will utilize either 12-channel or 16-channel DDR5 memory configurations—thus providing plenty of bandwidth across hundreds of Zen cores. Altogether very handy for cloud, enterprise, and HPC workloads—industry experts reckon that 384-core counts are feasible on single packages. Naturally, a Team Red timeline dictates that Zen 5 "Nirvana" is due before Zen 6 "Morpheus," so EPYC 9005 "Turin(-X)" and 8005 "Turin-Dense" lineups are (allegedly) up for a 2024-ish launch window on SP5 (LGA-6096) and SP6 (LGA 4094) socket types.