The Lunar Lake Package and Tiles

Lunar Lake sees a new way of organizing the various components of the SoC. It is essentially the Foveros technology behind Meteor Lake that's behind the processor's chiplet design, except Intel has moved around the various components. If you recall, Meteor Lake was a highly disaggregated processor, with the CPU cores located in the Compute Tile built on the Intel 4 node, the SoC and I/O tile on the 6 nm TSMC node, and the Graphics tile on the 5 nm node, all sitting on a 20 nm-class base tile that facilitates high-density microscopic wiring among the various tiles—like an interposer would.

With Lunar Lake, Intel has consolidated the Compute Tile, Graphics Tile, and most logic-heavy components of the former SoC tile, into a single Compute tile built on TSMC's 3 nm foundry node, while all the onboard controllers and I/O heavy components are disaggregated to the Platform I/O tile, which is built on the TSMC 6 nm process.


The base tile sits on the fiberglass substrate, which has fine high-density wiring to the two LPDDR5X memory chips that provide up to 32 GB of memory across two ranks, with a memory speed of LPDDR5X-8500. The presence of on-package memory lowers the memory physical-layer PHY power by 40% versus having memory chips on the motherboard or socketed as SO-DIMMs or CAMM2 modules.