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AMD Radeon R5 512 GB (SM2259XT2 + Solodigm N4PA Q5171A)

512 GB
Capacity
SM2259XT2
Controller
pQLC (PLC)
Flash
SATA 6 Gbps
Interface
2.5"
Form Factor

Multiple hardware versions found.

Performance could vary due to unannounced flash/controller changes.

Front
PCB Front
PCB Front
Flash
Flash
SSD Controller
Controller
NAND Die
NAND Die
The AMD Radeon R5 is a solid-state drive in the 2.5" form factor. It is only available in the 512 GB capacity listed on this page. With the rest of the system, the AMD Radeon R5 interfaces using a SATA 6 Gbps connection. The SSD controller is the SM2259XT2 from Silicon Motion, a DRAM cache is not available. AMD has installed 192-layer pQLC (PLC) NAND flash on the Radeon R5, the flash chips are made by Intel. Please note that this SSD is sold in multiple variants with different NAND flash or controller, which could affect performance, the "Notes" section at the end of this page has more info. To improve write speeds, a cache is used, so bursts of incoming writes are handled more quickly. The cache is sized at 125 GB. Copying data out of the SLC cache (folding) completes at 50 MB/s. The Radeon R5 is rated for sequential read speeds of up to 535 MB/s and 480 MB/s write.
The SSD's price at launch is unknown. AMD guarantees an endurance rating of 80 TBW, a very low value compared to other SSDs.

Solid-State-Drive

Capacity: 512 GB
Hardware Versions:
  • SM2259XT2 + Kioxia BiCS5
    256 GB
  • SM2259XT2 + Solodigm N4PA Q5171A
    512 GB
Overprovisioning: 35.2 GB / 7.4 %
Production: Active
Released: Unknown
Part Number: R5SL512G
Market: Consumer

Physical

Form Factor: 2.5"
Interface: SATA 6 Gbps
Protocol: AHCI
Power Draw: Unknown

Controller

Manufacturer: Silicon Motion
Name:
SM2259XT2
Find More Drives
Architecture: ARC 32-bit
Core Count: Single-Core
Frequency: 550 MHz
Foundry: TSMC
Process: 28 nm
Flash Channels: 2 @ 800 MT/s
Chip Enables: 8

NAND Flash

Manufacturer: Intel
Name: N4PA Q5171A
Rebranded: TWNIN4C513GQBUB100 TW033-1R T2451T
Type: pQLC (PLC)
Technology: 192-layer
Speed: 1600 MT/s
Capacity: 1 chip @ 4 Tbit
ONFI: 4.2
Topology: Floating Gate
Die Size: 73 mm²
(18.7 Gbit/mm²)
Dies per Chip: 3 dies @ 1368 Gbit
Planes per Die: 4
Decks per Die: 4
Read Time (tR): 110 µs
Program Time (tProg): 1400 µs
Block Erase Time (tBERS): 10 ms
Die Read Speed: 582 MB/s
Die Write Speed: 46 MB/s
Endurance:
(up to)		 3000 P/E Cycles
(250000 in SLC Mode)
Page Size: 16 KB
Block Size: 12288 Pages
Plane Size: 254 Blocks

DRAM Cache

Type: None

Performance

Sequential Read: 535 MB/s
Sequential Write: 480 MB/s
Random Read: Unknown
Random Write: Unknown
Endurance: 80 TBW
Warranty: Unknown
SLC Write Cache: Unknown
Cache Folding Speed: 50 MB/s

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • Unknown
RGB Lighting: No
PS5 Compatible: No

Reviews

Notes

Controller:

Depending on each SSD the controller clock can vary, i've seen it running from 425 MHz up to 550 MHz.

NAND Die:

Die read speed: aproximation
Die write speed: aproximation
In order to enable a balanced Gray data encoding, all five pages of data are needed in
both the first and second pass of the program algorithm. While this is the norm for most
QLC implementations except [1], it requires the storage of a few megabytes of data per
die in a DRAM or similar media. Instead, we use a 1b/cell (SLC) cache on the NAND die
to store the data needed for the two-pass PLC programming algorithm. To keep the area
overhead of the SLC cache to less than 2%, we improved the SLC reliability to 250k
program/erase (P/E) cycles, commensurate with 1k of P/E cycle capability in the present
PLC work.
Apr 9th, 2025 06:20 EDT change timezone

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