Capacity: | 2 TB (2000 GB) |
---|---|
Variants: | 500 GB 1 TB 2 TB |
Overprovisioning: | 185.4 GB / 10.0 % |
Production: | End-of-life |
Released: | Jun 25th, 2020 |
Price at Launch: | 270 USD |
Part Number: | LRD10Z002TG8 |
Market: | Consumer |
Form Factor: | M.2 2280 (Double-Sided) |
---|---|
Interface: | PCIe 3.0 x4 |
Protocol: | NVMe 1.3 |
Power Draw: |
Unknown (Idle) Unknown (Avg) 7.6 W (Max) |
Manufacturer: | Phison |
---|---|
Name: | PS5012-E12S-32 |
Architecture: | ARM 32-bit Cortex-R5 |
Core Count: | Quad-Core |
Frequency: | 667 MHz |
Foundry: | TSMC |
Process: | 12 nm |
Flash Channels: | 8 @ 667 MT/s |
Chip Enables: | 4 |
Controller Features: | DRAM (enabled) |
Manufacturer: | Toshiba |
---|---|
Name: | BiCS4 |
Part Number: | TH58LJT1T24BA8C |
Type: | TLC |
Technology: | 96-layer |
Speed: | 800 MT/s |
Capacity: | 8 chips @ 2 Tbit |
ONFI: | 4.0 |
Toggle: | 3.0 |
Topology: | Charge Trap |
Process: | 19 nm |
Die Size: | 86 mm² (6.0 Gbit/mm²) |
Dies per Chip: | 4 dies @ 512 Gbit |
Planes per Die: | 2 |
Decks per Die: | 2 |
Word Lines: |
109 per NAND String
88.1% Vertical Efficiency |
Read Time (tR): | 58 µs |
Program Time (tProg): | 561 µs |
Die Read Speed: | 551 MB/s |
Die Write Speed: | 57 MB/s |
Endurance: (up to) |
3000 P/E Cycles
(30000 in SLC Mode) |
Page Size: | 16 KB |
Block Size: | 1152 Pages |
Plane Size: | 1822 Blocks |
Type: | DDR4-2666 CL19 |
---|---|
Name: | SK Hynix H5AN8G6NCJR-VKC |
Capacity: |
2048 MB
(2x 1024 MB) |
Organization: | 8Gx16 |
Sequential Read: | 3,400 MB/s |
---|---|
Sequential Write: | 3,200 MB/s |
Random Read: | 680,000 IOPS |
Random Write: | 620,000 IOPS |
Endurance: | 800 TBW |
Warranty: | 5 Years |
MTBF: | 1.5 Million Hours |
Drive Writes Per Day (DWPD): | 0.2 |
SLC Write Cache: |
approx. 40 GB
(dynamic only) |
Speed when Cache Exhausted: | approx. 1000 MB/s |
TRIM: | Yes |
---|---|
SMART: | Yes |
Power Loss Protection: | No |
Encryption: |
|
RGB Lighting: | No |
PS5 Compatible: | No |
This section lists other SSDs in our database using the exact same hardware components |
Controller:2 main cores using Cortex-R5 clocked at 667 MHz with CoXProcessor technology (one additional dual-core) Cortex-R5 clocked at a lower clock for better efficience. The difference between this revision and the E12 revision is that this has a nichel IHS to improve the temperature, a smaller size, smaller node (12nm TSMC FinFET) and this works with less DRAM capacity. NAND Die:Read latency tR: 58 µs (ABL) |