Multiple hardware versions found.
Performance could vary due to unannounced flash/controller changes.
Capacity: | 120 GB |
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Variants: | 120 GB 240 GB 480 GB |
Hardware Versions: | |
Overprovisioning: | 16.2 GB / 14.5 % |
Production: | Active |
Released: | Dec 2023 |
Part Number: | Unknown |
Market: | Consumer |
Form Factor: | 2.5" |
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Interface: | SATA 6 Gbps |
Protocol: | AHCI |
Power Draw: |
0.33 W (Idle) Unknown (Avg) 1.8 W (Max) |
Manufacturer: | Phison |
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Name: | PS3111-S11-13 |
Architecture: | ARM 32-bit |
Core Count: | Single-Core |
Frequency: | 200 MHz |
Foundry: | UMC |
Process: | 40 nm |
Flash Channels: | 2 |
Chip Enables: | 8 |
Manufacturer: | Kioxia |
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Name: | BiCS5 |
Rebranded: | TT19G53AON |
Type: | TLC |
Technology: | 112-layer |
Speed: | 1200 MT/s |
Capacity: | 2 chips @ 512 Gbit |
Toggle: | 4.0 |
Topology: | Charge Trap |
Dies per Chip: | 1 die @ 512 Gbit |
Planes per Die: | 2 |
Word Lines: |
128 per NAND String
87.5% Vertical Efficiency |
Read Time (tR): | 56 µs |
Program Time (tProg): | 484 µs |
Die Read Speed: | 571 MB/s |
Die Write Speed: | 66 MB/s |
Endurance: (up to) |
3000 P/E Cycles
(100000 in SLC Mode) |
Page Size: | 16 KB |
Block Size: | 1344 Pages |
Plane Size: | 448 Blocks |
Type: | None |
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Sequential Read: | 500 MB/s |
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Sequential Write: | 360 MB/s |
Random Read: | 38,000 IOPS |
Random Write: | 72,000 IOPS |
Endurance: | 40 TBW |
Warranty: | 5 Years |
MTBF: | 2.0 Million Hours |
Drive Writes Per Day (DWPD): | 0.2 |
SLC Write Cache: | Yes |
TRIM: | Yes |
---|---|
SMART: | Yes |
Power Loss Protection: | No |
Encryption: |
|
RGB Lighting: | No |
PS5 Compatible: | No |
Controller:In order to improve performance, Phison implemented a way that the controller utilizes it's internal 32 MiB of SRAM as some kind of "Pit-stop" that is allocated for incoming Write request in order to improve performance since it's a very quick to access and fast RAM. This implementation was called Smart Cache Flush. NAND Die:Although this Die is a 4-plane design, most Kioxia BiCS5 NAND Dies used in most SSDs are dual planes design because of Yield and production cost. |