Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced that its 5-nanometer (nm) FinFET process technology is complete in its development and is now ready for customers' samples. By adding another cutting-edge node to its extreme ultraviolet (EUV)-based process offerings, Samsung is proving once again its leadership in the advanced foundry market.

Compared to 7 nm, Samsung's 5 nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture. In addition to power performance area (PPA) improvements from 7 nm to 5 nm, customers can fully leverage Samsung's highly sophisticated EUV technology. Like its predecessor, 5 nm uses EUV lithography in metal layer patterning and reduces mask layers while providing better fidelity.

TSMC announced they've completed the infrastructure design for the 5 nm process, which is the next step in silicon evolution when it comes to density and performance. TSMC's 5 nm process will leverage the company's second implementation of EUV (Extreme Ultra Violet) technology (after it's integrated in their 7 nm process first), allowing for improved yields and performance benefits.

According to TSMC, the 5 nm process will enable up to 1.8x the logic density of their 7 nm process, a 15% clock speed gain due to process improvements alone on an example Arm Cortex-A72 core, as well as SRAM and analog circuit area reduction, which means higher number of chips per wafer. The process is being geared for mobile, internet, and high performance computing applications. TSMC also provides online tools for silicon design flow scenarios that are optimized for their 5 nm process. Risk production is already ongoing.

AMD's senior VP of AMD's datacentre group Forrest Norrod, at the Rice Oil and Gas HPC conference, said that while graphene does have incredible promise for the world of computing, it likely will take some ten years before such exotic material are actually taken advantage off. As Norrod puts it, silicon still has a pretty straightforward - if increasingly complex - path down to 3 nanometer densities. And according to him, at the rate manufacturers are being able to scale down their production nodes further, the average time between node transitions stands at some four or five years - which makes the jump to 5 nm and then 3 nm look exactly some 10 years from now, where Norrod expects to go through two additional shrinking nodes for the manufacturing process.

Of course, graphene is being hailed as the next best candidate for taking over silicon's place at the heart of our more complex, high-performance electronics, due, in part, to its high conductivity independent of temperature variation and its incredible switching resistance - it has been found to be able to operate at Terahertz switching speeds. It's a 2D material, which means that implementations of it will have to occur in deposited sheets of graphene across some other material.

GlobalFoundries is looking to be sold lock-stock-and-barrel by its investors, after heavily downsizing and parting with some of its Singapore-based assets recently. Once promising to lead the market with 7 nm and 5 nm advancements, the company crashed out of the sub-10 nm race, making AMD, its biggest customer, look for 7 nm supplies from TSMC. GlobalFoundries is the world's third largest semiconductor foundry service provider, with an 8.4 percent market share, behind TSMC and Samsung. Intel doesn't offer manufacturing services, as its fabs are fully dedicated to manufacturing its own products.

GlobalFoundries's main investor is Abu Dhabi-based Mubadala Technology, which holds a 90 percent stake in the company. Korean semiconductor companies Samsung and SK Hynix are reportedly in the foray to buy out GlobalFoundries, as it would give them a turnkey presence in the US, with its Upstate New York facilities. The company is unlikely to entertain bids from Chinese companies, as CFIUS would likely block the sale. "Global Foundries is unlikely to be bought by a Chinese company such as SMIC in that the U.S. government is keeping China in check in various industries," said an industry insider, adding, "The most potential candidates include South Korean companies such as Samsung Electronics and SK Hynix, and Samsung Electronics can increase its share in the market to 23 percent at once if it takes over Global Foundries."

TSMC is giving final touches to set its flagship 7 nanometer EUV (extreme ultraviolet lithography) silicon fabrication node at its highest state of readiness for business, called mass-production. At this state, the node can mass-produce products for TSMC's customers. TSMC had taped out its first 7 nm EUV chips in October 2018. The company will also begin risk-production of the more advanced 5 nm node in April, staying on schedule. Mass production of 5 nm chips could commence in the first half of 2020.

The 7 nm EUV node augments TSMC's 7 nm DUV (deep ultraviolet lithography) node that's been already active since April 2018, and producing chips for AMD, Apple, HiSilicon, and Xilinx. At the turn of the year, 7 nm DUV made up 9 percent of TSMC's shipments. With the new node going online, 7 nm (DUV + EUV) could make up 25 percent of TSMC's output by the end of 2019.

The world's largest contract semiconductor manufacturing company, TSMC, has been cleared to commence construction of a new 3 nm chip factory at the Southern Taiwan Science Park in Tainan. The new factory is expected to use 20 percent renewable energy and 50 percent recycled water.

The factory's environmental impact assessment was accepted by the Environmental Protection Administration (EPA) on Dec. 19, after concerns were raised about use of water and power sources. TSMC is expected to invest NT$600 million (US$19.45 million) in the project, with construction to begin in 2022. Production is planned to start in late 2022 or early 2023. At the same site, TSMC is also building a 5 nm chip factory, which is expected to be up and running in late 2019 or early 2020.

TSMC has quickly (over a span of years, but still) become the de-facto silicon manufacturing giant in the industry. They produce silicon-based solutions for almost all the significant tech companies (NVIDIA, AMD, Apple, Qualcomm, including the silicon manufacturing leader of yonder, Intel), and are on the forefront of new fabrication technologies. Just today we've covered how they are already well on their way to their second-gen 7 nm (N7+) fabrication technology with usage of EUV, and carving their path forward for 5 nm (N5).

TSMC, the world's biggest contract semiconductor manufacturer, who is at the forefront of 7 nanometer production has just announced that they are making good progress with their second generation of 7 nm technology "N7+", using EUV (Extreme Ultraviolet Lithography). A first design for N7+ from an unnamed customer has been taped out. The company's first-gen 7 nm production is running well already, with final products, like Apple iPhone already in the hands of customers.

While not fully EUV yet, the N7+ process will see limited EUV usage, for up to four non-critical layers, which gives the company an opportunity to figure out how to make best use of the new technology, how to ramp up for mass production and how to fix the little quirks that show up as soon as you move from the lab to the factory.

Intel's in-house sub-10 nanometer silicon fabrication dreams seem more distant by the day. Raymond James analyst Chris Caso, in an interview with CNBC stated that Intel's 10 nm process development could set the company back by at least 5 years behind TSMC. In its most recent financial results call, Intel revised its 10 nm outlook to reflect that the first 10 nm processors could only come out by the end of 2019. "Intel's biggest strategic problem is their delay on 10nm production - we don't expect a 10nm server chip from Intel for two years," analyst Chris Caso said in a note to clients Tuesday. "10nm delays create a window for competitors, and the window may never again close."

By that time, Intel will have missed several competitive milestones behind TSMC, which is in final stages of quantitatively rolling out its 7 nm process. Caso predicts that by the time Intel goes sub-10 nm (7 nm or something in that nanoscopic ballpark), TSMC and Samsung could each be readying their 5 nm or 3 nm process roll-outs. A Rosenblatt Securities report that came out late-August was even more gloomy about the situation at Intel foundry. It predicted that foundry delays could set the company back "5, 6, or even 7" years behind rivals. Intel is already beginning offload some of its 14 nm manufacturing to TSMC. Meanwhile, AMD is reportedly planning to entirely rely on TSMC to make its future generations of "Zen" processors.

TSMC is close to adapt 3D stacked silicon wafers to complex silicon designs, such as graphics processors, using its new proprietary Wafer-on-Wafer (WoW) Advanced Packaging technology, which will be introduced with its 7 nm+ and 5 nm nodes. 3D stacked silicon fabrication is currently only implemented on "less complex" silicon designs, such as NAND flash, which don't run anywhere near as hot as complex designs ASIC designs, such as GPUs or CPUs. In its current form, TSMC achieved 2-layer stacks, in which two silicon layers that are "mirror images" of each other (for perfect alignment), sandwich bonding layers, through which pins for the upper layer pass through.

The bonding of the two layers is where the bulk of TSMC's innovations and "secret sauces" lie. For 3D NAND flash, multiple pancaked dies are wired out through their edges. You don't need as many pins to talk to a NAND flash die, as say a GPU die. For complex dies, designers have to pass thousands of pins through the "bottom layer," the connecting substrate, and eventually to the "top layer." The bottom layer hence is bumped out on both ends, one side interfacing with the package substrate for both dies, and the top side serving as a sort of substrate for the top die. This innovation is what TSMC calls "thru-silicon-vias" or TSVs.

Semiconductor manufacturers have been historically bullish when it comes to the introduction of new manufacturing technologies. Intel, AMD (and then Globalfoundries), TSMC, all are companies who thrive in investors' confidence: they want to paint the prettiest picture they can in terms of advancements and research leadership, because that's what attracts investment, and increased share value, and thus, increased funds to actually reach those optimistic goals.

However, we've seen in recent years how mighty Intel itself has fallen prey to unforeseen complications when it comes to advancements of its manufacturing processes, which saw us go from a "tick-tock" cadence of new architecture - new manufacturing process, to the introduction of 14 nm ++ processes. And as Intel, Globalfoundries and TSMC race towards sub 7-nm manufacturing processes with 250 mm wafers and EUV usage, things aren't getting as rosy as the ultraviolet moniker would make us believe.

TSMC has announced the location for their first 3 nm fab: it will be built in the Tainan Science Park, southern Taiwan. Rumors pegged the new 3 nm factory as possibly being built in the US, due to political reasons; however, TSMC opted to keep their production capabilities clustered in the Tainan Science Park, where they can better leverage their assets and supply chain for the production and support of the world's first 3 nm semiconductor factory. It certainly also helped the Taiwanese government's decision to pledge land, water, electricity and environmental protection support to facilitate TSMC's latest manufacturing plan. It's expected that at least part of the manufacturing machines will be provided by ASML, a Netherlands-based company which has enjoyed 25% revenue growth already just this year.

As part of the announcement, TSMC hasn't given any revised timelines for their 3 nm production, which likely means the company still expects to start 3 nm production by 2022. TSMC said its 7 nm yield is ahead of schedule, and that it expects a fast ramp in 2018 - which is interesting, considering the company has announced plans to insert several extreme ultraviolet (EUV) layers at 7 nm. TSMC has also said its 5 nm roadmap is on track for a launch in the first quarter of 2019.

IBM, its Research Alliance partners GLOBALFOUNDRIES and Samsung, and equipment suppliers have developed an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. In less than two years since developing a 7 nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip.

The resulting increase in performance will help accelerate cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today's devices, before needing to be charged.

Samsung stands as a technology giant in the industry, with tendrils stretching out towards almost every conceivable area of consumer, prosumer, and professional markets. It is also one of the companies which can actually bring up the fight to Intel when it comes to semiconductor manufacturing, with some analysts predicting the South Korean will dethrone Intel as the top chipmaker in Q2 of this year. Samsung scales from hyper-scale data centers to the internet-of-things, and is set to lead the industry with 8nm, 7nm, 6nm, 5nm, 4nm and 18nm FD-SOI in its newest process technology roadmap. The new Samsung roadmap shows how committed the company is (and the industry with it) towards enabling the highest performance possible from the depleting potential of the silicon medium. The 4 nm "post FinFET" structure process is set to be in risk production by 2020.

This announcement also marks Samsung's reiteration on the usage of EUV (Extreme Ultra Violet) tech towards wafer manufacturing, a technology that has long been hailed as the savior of denser processes, but has been ultimately pushed out of market adoption due to its complexity. Kelvin Low, senior director of foundry marketing at Samsung, said that the "magic number" for productivity (as in, with a sustainable investment/return ratio) with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.

With Intel's "tick-tock" product development cycle slowing down to a 3-launch cadence per silicon fab process, the company is preparing to launch no less than three micro-architectures on its next 10 nanometer silicon fab process. The first 10 nm CPU by Intel will launch in 2017.

In 2016, Intel will launch its 7th generation Core "Kaby Lake" processor, its third chip on the 14 nm process (after "Broadwell" and "Skylake"). The first 10 nm micro-architecture will be codenamed "Cannonlake," and will launch some time in 2017. Intel will build chips on the 10 nm for two more generations after "Cannonlake." The company's 2018 micro-architecture, built on the 10 nm will be codenamed "Icelake," and its 2019 release will be codenamed "Tigerlake." It's only 2020 that the company will pull out its next silicon fab process, 5 nm.

Taiwan's premier semiconductor foundry, TSMC, announced that it is on track to begin production of chips on its 7 nanometer silicon fab process by the first half of 2018. The company also announced that production on an even newer 5 nanometer process should commence two years later, in 2020. The company has currently cleared all decks for mass-production of chips on its 16 nm FFC (FinFET compact) node, with the company hoping to grab over 70% of the worldwide 14/16 nm production market-share by the end of 2016.