Samsung Electronics is hit by a major scandal involving current and former employees. It's being alleged that these employees are involved in falsifying information about the semiconductor fabrication yields of the company's 3/4/5 nanometer nodes to clear them for commercial activity. This came to light when Samsung was observing lower than expected yields after the nodes were approved for mass-production of logic chips for Samsung, as well as third-party chip-designers. A falsified yield figure can have a cascading impact across the supply-chain, as wafer orders and pricing are decided on the basis of yields. Samsung however, has downplayed the severity of the matter. The group has initiated an investigation into Samsung Device Solutions, the business responsible for the foundry arm of the company. This includes a thorough financial audit of the foundry to investigate if the investments made to improve yields were properly used.

Intel's upcoming "Meteor Lake" and "Arrow Lake" client mobile processors introduce an interesting twist to the chiplet concept. Earlier represented in vague-looking IP blocks, new artistic impressions of the chip put out by Intel shed light on a 3-die approach not unlike the Ryzen "Vermeer" MCM that has up to two CPU core dies (CCDs) talking to a cIOD (client IO die), which handles all the SoC connectivity; Intel's design has one major difference, and that's integrated graphics. Apparently, Intel's MCM uses a GPU die sitting next to the CPU core die, and the I/O (SoC) die. Intel likes to call its chiplets "tiles," and so we'll go with that.

The Graphics tile, CPU tile, and the SoC or I/O tile, are built on three different silicon fabrication process nodes based on the degree of need for the newer process node. The nodes used are Intel 4 (optically 7 nm EUV, but with characteristics of a 5 nm-class node); Intel 20A (characteristics of 2 nm), and external TSMC N3 (3 nm) node. At this point we don't know which tile gets what. From the looks of it, the CPU tile has a hybrid CPU core architecture made up of "Redwood Cove" P-cores, and "Crestmont" E-core clusters.

AMD's final refresh of the RDNA2 graphics architecture, the Radeon RX 6x50 series, could debut in June or July 2022, according to Greymon55, a reliable source with GPU leaks. The final refresh of RDNA2 could see AMD use faster 18 Gbps GDDR6 memory across the board, and eke out higher engine clocks on existing silicon IP. At this point it's not known if these new chips will be built on the same 7 nm process, or are an optical shrink to 6 nm (TSMC N6). Such a shrink to a node that offers 18% higher transistor density, would have significant payoffs with clock-speed headroom. AMD's RDNA3-based 5 nm GPUs could debut only toward the end of the year.

In related news, AMD is preparing to launch another entry-level SKU within the RX 6000 series; the Radeon RX 6500 (non-XT). Based on the same 6 nm Navi 24 silicon as the RX 6500 XT, this SKU could have a core-configuration that's in-between the RX 6500 XT and the RX 6400, in featuring 768 stream processors across 12 compute units; and 4 GB of GDDR6 memory, which is similar to the RX 6400, but with higher engine clocks. The RX 6500 is targeting a $150 (MSRP) price-point.

Renowned hardware leaker kopike7kimi on Twitter revealed some purported details on NVIDIA's next-generation architecture for HPC (High Performance Computing), Hopper. According to the leaker, Hopper is still sporting a classic monolithic die design despite previous rumors, and it appears that NVIDIA's performance targets have led to the creation of a monstrous, ~1000 mm² die package for the GH100 chip, which usually maxes out the complexity and performance that can be achieved on a particular manufacturing process. This is despite the fact that Hopper is also rumored to be manufactured under TSMC's 5 nm technology, thus achieving higher transistor density and power efficiency compared to the 8 nm Samsung process that NVIDIA is currently contracting. At the very least, it means that the final die will be bigger than the already enormous 826 mm² of NVIDIA's GA100.

If this is indeed the case and NVIDIA isn't deploying a MCM (Multi-Chip Module) design on Hopper, which is designed for a market with increased profit margins, it likely means that less profitable consumer-oriented products from NVIDIA won't be featuring the technology either. MCM designs also make more sense in NVIDIA's HPC products, as they would enable higher theoretical performance when scaling - exactly what that market demands. Of course, NVIDIA could be looking to develop an MCM version of the GH100 still; but if that were to happen, the company could be looking to pair two of these chips together as another HPC product (rumored GH-102). ~2,000 mm² in a single GPU package, paired with increased density and architectural improvements might actually be what NVIDIA requires to achieve the 3x performance jump from the Ampere-based A100 the company is reportedly targeting.

TSMC has held its quarterly earnings conference today and it's good news all around, at least if you're TSMC or one of its shareholders, as the company reported record profits of US$6.01 billion for the quarter, or an increase of 16.4 percent compared to the same quarter last year. At the same time, the company announced that it's going to increase its CapEx, by no less than US$40-44 billion this year, which should be compared to the US$30 billion in 2021. The company is expecting to continue to rake in money this quarter, with an expected revenue before expenditures and tax of US$16.6 to US$17.2 billion, compared to US$15.74 billion for this quarter.

Looking at the graphs provided by TSMC which shows where its revenue is coming from, its 7 nm and 5 nm nodes are now accounting for 50 percent of TSMC's revenues. The 5 nm node on its own, almost made as much money as its 16 and 28 nm nodes combined in Q4. We can also see that the 5 nm has gone from eight percent of TSMC's revenues in 2020, to 19 percent this year, with the 7 nm node dropping slightly from 33 percent to 31 percent. 2021 saw a massive 51 percent revenue growth in automotive components for TSMC compared to 2020, yet it only accounted for four percent of TSMC's total revenue for 2021. Smartphones and HPC are jointly holding 81 percent of TSMC's business based on revenue, which isn't likely to change any time soon.

Anandtech asked AMD during a meeting at CES about the production nodes used to make its chips at TSMC and the importance of leading edge nodes for AMD to stay competitive, especially in light of the cost of using said nodes. Lisa Su confirmed in her answer to Anandtech that AMD is using an optimised high-performance 5 nm node for its upcoming Zen 4 processor chiplets, which there interestingly appears to be both 2D and 3D versions of. This is the first time we've heard a mention of two different chiplet types using the same architecture and it could mean that we get to see Zen 4 based CPUs with and without 3D cache.

What strikes us as a bit odd about the Anandtech article, is that they mention the fact that several of TSMC's customers are already making 4 nm and soon 3 nm chips and are questioning why AMD wouldn't want to be on these same nodes. It seems like Anandtech has forgotten that not all process nodes are universally applicable and just because you can make one type of chip on a smaller node, doesn't mean it'll be suitable for a different type of chip. For the longest of times, mobile SoCs or other similar chips seem to always have been among the first things being made on new nodes, with more complex things like GPUs and more advanced CPUs coming later, to tweaked versions of the specific node. The fact that TSMC has no less than three 7 nm nodes, should be reason enough to realise that the leading edge node might not be the ideal node for all types of chips.

ASML, makers of vital semiconductor fabrication machinery powering the world's leading fabs, including TSMC, provided its first damage-assessment of the fire incident at one of its component plants near Berlin, on January 3. This plant manufactures several mechanical and optical components of semiconductor fabrication machinery, such as wafer tables and clamps, reticle chucks and mirror blocks.

ASML, in a press-release, disclosed that production of components used in DUV (deep-ultraviolet) machines, has been restarted, as that area of the plant is unaffected by the fire. A region of the plant that manufactures wafer clamps for use in its EUV (extreme ultraviolet) machines, however, has been affected by the fire. The company is still in the process of coming up with a recovery plan for this area, and will come up with a tentative date for restart of production only after that. EUV lithography is leveraged for 5 nm and upcoming 3 nm silicon fabrication nodes at TSMC, Samsung, and Intel. TSMC is known to be ASML's largest customer. ASML stated that it will release its Q4-2021 and full-year 2021 financial results on January 19, and it may provide more updates on the matter.The press-release follows.

AMD already declared the CPU core counts of its EPYC "Genoa" and "Bergamo" processors to top out at 96 and 128, respectively, a core-count believed to have been facilitated by the larger fiberglass substrate of the next-gen SP5 CPU socket, letting AMD add more 8-core "Zen 4" chiplets, dubbed CPU complex dies (CCDs). Until now, AMD has used the chiplet as a common component between its EPYC enterprise and Ryzen desktop processors, to differentiate CPU core counts.

A fascinating theory that hit the rumor-mill, indicates that the company might leverage 5 nm (TSMC N5) carve out larger CCDs with up to 16 "Zen 4" CPU cores. Half of these cores are capped at a much lower power budget, essentially making them efficient-cores. This is a concept AMD appears to be carrying over from its 15-Watt class mobile processors, which see the CPU cores operate under an aggressive power-management. These cores still turn out a reasonable amount of performance, and are functionally identical to the ones on 105 W desktop processors with a relaxed power budget.

AMD's next-generation Ryzen "Raphael" processor could launch only in the second half of 2022, confirms a leaked company slide scored by VideoCardz. The slide points to a Ryzen 5000X3D series product-stack update within the 1H-2022. These are Socket AM4 processors that leverage the company's updated "Zen 3(+)" CPU core die (CCD), which features 64 MB of 3D Vertical cache memory in addition to 32 MB of L3. AMD claims that 3DV Cache technology significantly improves performance akin to a generational update (anywhere between 5% to 25% depending on the application). The company is targeting "Spring" 2022 for launch, which would put this around early-Q2.

The "Raphael" Socket AM5 processor is sure to catch much of the attention, as it's the company's true next-gen desktop product. It heralds Socket AM5, a new LGA-based socket; and next-generation connectivity that includes DDR5 memory and PCI-Express Gen 5. The CCDs of these processors are built on the TSMC N5 (5 nm) silicon fabrication node, and are based on the "Zen 4" microarchitecture. The leaked slide shows the first grainy picture of Socket AM5, with a retention mechanism not unlike what we're used to, on the Intel platform. We're hearing rumors that AM5 will somehow manage cooler-compatibility with AM4 despite the radical redesign to the socket. An H2-2022 launch would put "Raphael" close to Intel's 13th Gen Core "Raptor Lake" launch, as team blue hopes to return to an annual IPC-uplift cadence, with up to 8 "Raptor Cove" P-cores, and 16 "Gracemont" E-cores.

According to an article by DigiTimes, which kind of states the obvious, the foundry industry isn't likely to change much over the next few years, as the cost of building a cutting edge foundry keeps increasing, which means the competition isn't likely to catch up with the market leaders. The costs mentioned are estimates, but seem quite likely and explains why there's so little competition in the foundry business.

It's unclear if the costs have been inflation adjusted or not, but a 90 nm 12-inch fab that could output 50,000 wafers a month, is said to have cost US$2.4 billion to build when it was the cutting edge node. Once things moved on to 28 nm, the equivalent fab would've cost US$6 billion, whereas a cutting edge 5 nm fab today, comes in at as much as US$16 billion. These are obviously long term investments, as even today, 90 nm nodes are used for plenty of chips, but most of the nodes above 28 nm are today used for specialty products rather than commonly used ICs, unless we're talking about 8-bit microcontrollers or some simpler components which companies such as TSMC and Samsung wouldn't even bother making.

China's technology reliance on 3rd party companies seems to be getting smaller. One of the leading technology companies in China, Huawei, has designed a laptop powered by a custom 5 nm Kirin SoC with DDR5 memory. Called the Dyna Cloud L420, Huawei has prepared this model for the Chinese market to provide a fully functional laptop that will get the job done, with no risk of the potential security backdoors implemented in the processor. Powered by a brand new Kirin 9006C SoC manufactured on TSMC's 5 nm process, it features eight unknown cores running at 3.1 GHz frequency. We assume that those are custom cores designed by Huawei. This SoC is accompanied by 8 GB of LPDDR5 memory, with 256 GB and 512 GB UFS 3.1 configurations storage options.

When it comes to the rest of the laptop, it rocks a 14-inch 2160x1440 display. I/O options are solid as well, as this machine has an HDMI video output, two USB-A, one USB-C, and Gigabit Ethernet using a mini-RJ45 port. Connectivity is provided by Wi-Fi 6 and Bluetooth 4.2. There is a 56 W/h battery that provides the juice to keep it running when it comes to the battery. And to complete all of that, this laptop officially only supports Huawei's proprietary Kirin OS (KOS) and Unity OS (UOS), with expected support for HarmonyOS in the future. Pricing and availability information is a mistery at the present date.

During the annual Snapdragon Tech Summit, Qualcomm Technologies, Inc. expanded the portfolio of solutions for Always On, Always Connected PCs with the introduction of the Snapdragon 8cx Gen 3 compute platform, designed to deliver the performance and exceptional experiences users deserve in premium ultra-slim and fanless laptops. To strengthen the entry-tier Windows PC and Chromebook ecosystems with robust 5G connectivity and advanced AI experiences, the Company also unveiled the Snapdragon 7c+ Gen 3 Compute Platform. Both platforms utilize smart, connected technology to modernize PC experiences and redefine mobile computing for end users.

"Snapdragon 8cx Gen 3 builds on the technology that has transformed the PC industry, delivering premium experiences with breakthrough performance per watt, immersive camera and audio with enhanced AI-acceleration, lightning-fast 5G connectivity, and chip-to-cloud security in thin, fanless systems," says Miguel Nunes, vice president, product management, Qualcomm Technologies, Inc. "With Snapdragon 7c+ Gen 3, we are raising the bar in the entry-tier by extending 5G mobile computing across ecosystems. Whether for consumers, business, or education, Snapdragon compute platforms deliver the capabilities and experiences that our ecosystem customers and end users need."

AMD later this month is preparing to address investors as part of a yet-unknown event. The company typically hosts Financial Analyst Day events around Q1-Q2, and goes to the investors with substantial material on the current state of the organization, the products on offer, what's on the horizon, and how it could impact the company's financials. An alleged presentation related to the November 2021 event was leaked to the web. The presentation provides a guided tour of the entire product portfolio of the company, spanning server processors, compute accelerators, consumer graphics, some client processors, and the semi-custom business.

The presentation outlines that the company has so far successfully executed its roadmaps for the client-CPU, server-CPU, graphics, and compute-accelerator segments. In the client CPU segment, it shows a successful execution up to 2021 with the "Zen 3" microarchitecture. In the server space, it mentions successful execution for its EPYC processors up to "Zen 3" with its "Milan" processors, and confirms that its next-generation "Zen 4" microarchitecture, and its sister-architecture, the "Zen 4c," will be built on the 5 nm silicon fabrication node (likely TSMC N5). The presentation also details the recently announced "Milan-X" processor for existing SP3 platforms, which debuts the 3D Vertical Cache technology, bringing up to 96 MB of L3 cache per CCD, and up to 768 MB of L3 cache (804 MB L1+L2+L3 cache) per socket.Update 10:54 UTC: The presentation can now be found on the AMD Investor Relations website.

TSMC will commercialize its N3 (3 nm) EUV silicon fabrication node in 2022, with volume production set to commence in the second half of the year. The company is looking to maximize capacity on its current N5 (5 nm) node, which already serves major customers such as Apple. AMD is expected to utilize N5 allocation going into 2022 as its next-generation "Zen 4" processors are expected to leverage the node to drive up CPU core counts and caches. The company is also utilizing N6 (6 nm) for its CDNA2 compute accelerator logic dies. N5 could also power mobile application processors from several manufacturers.

TSMC today introduced its N4P process, a performance-focused enhancement of the 5-nanometer technology platform. N4P joins the industry's most advanced and extensive portfolio of leading-edge technology processes. With N5, N4, N3 and the latest addition of N4P, TSMC customers will have multiple and compelling choices for power, performance, area, and cost for its products.

As the third major enhancement of TSMC's 5 nm family, N4P will deliver an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density. In addition, N4P lowers process complexity and improves wafer cycle time by reducing the number of masks. N4P demonstrates TSMC's pursuit and investment in continuous improvement of our process technologies.

With the x86 architecture, large hyperscale cloud providers have been experiencing all sorts of troubles, from high power consumption to the high pricing structure of these processors. Companies like Amazon Web Services (AWS) build their processors based on 3rd party instruction set architecture designs. Today, Alibaba, the Chinese giant, has announced the launch of two processors made in-house to serve everything from edge to central server processing. First in line is the RISC-V-based Xuantie series of processors, which can run anything from AliOS, FreeRTOS, RT-Thread, Linux, Android, etc., to other operating systems as well. These processors are open-source, capable of modest processing capabilities, and designed as IPs that anyone can use. You can check them out on T-Head GitHub repositories here.

The other thing that Alibaba announced is the development of a 128-core custom processor based on the Arm architecture. Called Yitian 710 server SoC, TSMC manufactures it on the company on 5 nm semiconductor node. So far, Alibaba didn't reveal any details about the SoC and what Arm cores are used. However, this signifies that the company seeks technology independence from outside sources and wants to take it all in-house. With custom RISC-V processors for lower-power tasks and custom Arm server CPUs, the whole infrastructure is covered. It is just a matter of time before Alibaba starts to replace x86 makers in full. However, given the significant number of chips that the company needs, it may not happen at any sooner date.

Marvell today announced the expansion of its industry-leading 5 nm data infrastructure platform with the launch of the industry's first 5 nm 50G PAM4 device for the carrier market, the Prestera DX 7321 Ethernet switch. The new switch builds on the success of the Prestera carrier-optimized portfolio and is ideal for 5G fronthaul and edge connectivity. In concert with this, Marvell's 5 nm OCTEON 10 DPU family, incorporating industry-leading hardware accelerators, is now sampling. By utilizing the industry's leading advanced process geometry, the Marvell Prestera switch and OCTEON DPU deliver 50% lower power than existing offerings, enabling new infrastructure solutions for next-generation carrier edge networks and RAN deployment models.

With the addition of the 5 nm Prestera device, the expanded carrier-optimized switch portfolio now comprises four cutting-edge Ethernet switches that scale port speeds from 1 Gbps to 400 Gbps with aggregate bandwidths ranging from 200 Gbps to 1.6 Tbps. The newest offering enhances Marvell's 5G solutions for Open RAN, vRAN and traditional RAN architectures, with Class D precision time protocol (PTP), which provides more timing headroom to enable larger cell coverage radius. The switch device incorporates integrated MACsec security and advanced telemetry to facilitate network visibility and automation.

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company's Gate-All-Around (GAA) transistor structure at its 5th annual Samsung Foundry Forum (SFF) 2021. With a theme of "Adding One More Dimension," the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year's event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations, and foundry services.

"We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application," said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time."

NVIDIA is rumored to be giving its GeForce RTX 30-series "Ampere" graphics card family a mid-term refresh by the 2022 International CES, in January; the company is also targeting Q4-2022, specifically October, to debut its next-generation RTX 40-series. The Q1 refresh will include "SUPER" branded SKUs taking over key price-points for NVIDIA, as it lands up with enough silicon that can be fully unlocked. This leak comes from Greymon55, a reliable source on NVIDIA leaks. It also aligns with the most recent pattern followed by NVIDIA to keep its GeForce product-stack updated. The company had recently released "Ti" updates to certain higher-end price-points, in response to competition from the Radeon RX 6000 "RDNA2" series.

NVIDIA's next-generation will be powered by the "Lovelace" graphics architecture that sees even more hardware acceleration for the RTX feature-set, more raytraced effects, and preparation for future APIs. It also marks NVIDIA's return to TSMC, with the architecture reportedly being designed for the 5 nm (N5) silicon fabrication node. The current-gen GeForce "Ampere" chips are being products on an 8 nm foundry node by Samsung.

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced that four of its System LSI products received product carbon footprint label certification from the Carbon Trust, the first of Samsung's logic chips to do so. Having received the semiconductor industry's first carbon footprint accreditation for memory chips from the Carbon Trust in 2019, Samsung has now broadened its ESG (Environmental, Social, and Governance) spectrum with this global recognition of 'eco-friendly' logic chips. Samsung also grabbed the industry's first triple Carbon Trust Standard for Carbon, Water and Waste in June 2021.

The Carbon Trust is an independent and expert partner of organizations around the world that advises businesses on their opportunities in a sustainable, low carbon world. The Carbon Trust also measures and certifies the environmental footprint of organizations, supply chains and products. Of the various certification categories of the Carbon Trust, Samsung's System LSI products received the CO2 Measured product carbon footprint label. The label certifies the chip's carbon footprint, which informs consumers of the impact that the product and its manufacturing process have on the environment. Receiving the CO₂ Measured label is a critical first step for carbon reduction, since it verifies the current carbon emissions of the product with globally recognized specifications (PAS 2050), which Samsung can use as a benchmark to measure future carbon reductions.

The first desktop processors to implement AMD's "Zen 4" microarchitecture will feature integrated graphics as standard across the lineup, according to a Chips and Cheese report citing leaked AMD design documents. Currently, most of the Socket AM4 desktop processor lineup lacks integrated graphics, and specialized "G" SKUs with integrated graphics dot it. These SKUs almost always come with compromises in CPU performance or PCIe I/O. With its 5 nm "Raphael" Socket AM5 desktop processor, AMD is planning to change this, in a bid to match up to Intel on the universality of integrated graphics.

Built in the 5 nm silicon fabrication process, the "Raphael" silicon combines "Zen 4" CPU cores along with an iGPU based on the RDNA2 graphics architecture. This would be the first time AMD updated the SIMD architecture of its Ryzen iGPUs since 2017. The RDNA2-based iGPU will come with a more advanced DCN (Display CoreNext) component than current RDNA2-based discrete GPUs, with some SKUs even featuring DisplayPort 2.0 support, besides HDMI 2.1. By the time "Raphael" is out (2022-23), it is expected that USB4 type-C would gain popularity, and mainstream motherboards as well as pre-built desktops could ship with USB4 with DisplayPort 2.0 passthrough. AMD relies on a discrete USB4 controller with PCI-Express 4.0 x4 wiring, for its first Socket AM5 platform.

AMD's upcoming Radeon RX 7000 series could include GPUs from both the RDNA3 and RDNA2 graphics architectures, according to reliable sources on social media. This theory holds that the company could introduce new 5 nm GPUs based on the new RDNA3 architecture for the higher end, namely the Navi 31 and Navi 32; while giving the current-gen RDNA2 architecture a new lease of life in the lower segments. This isn't, however, a simple rebrand.

Apparently, some existing Navi 2x series chips will receive an optical shrink to the 6 nm node, in a bid to improve their performance/Watt. Some of the performance/Watt improvement could be used to increase engine clocks. These include the Navi 22, with its 40 RDNA2 compute units and 192-bit GDDR6 memory bus; and the Navi 23, with its 32 RDNA2 compute units and 128-bit GDDR6 memory bus. The updated Navi 22 will power the SKU that succeeds the current RX 6600 XT, while the updated Navi 23 works the lower-mainstream SKU RX x500-class.

While the server industry transitions to the latest generation of processors based on the x86 platform, the Intel Ice Lake and AMD Milan CPUs entered mass production earlier this year and were shipped to certain customers, such as North American CSPs and telecommunication companies, at a low volume in 1Q21, according to TrendForce's latest investigations. These processors are expected to begin seeing widespread adoption in the server market in 3Q21. TrendForce believes that Ice Lake represents a step-up in computing performance from the previous generation due to its higher scalability and support for more memory channels. On the other hand, the new normal that emerged in the post-pandemic era is expected to drive clients in the server sector to partially migrate to the Ice Lake platform, whose share in the server market is expected to surpass 30% in 4Q21.

AMD's next generation RDNA3 graphics architecture generation could see a near-quadrupling in raw SIMD muscle over the current RDNA2, according to a spectacular rumor. Apparently, the company will deploy as many as 15,360 stream processors (quadruple that of a Radeon RX 6800), and spread across 60 WGPs (Workgroup Processors), and do away with the compute unit. This is possibly because the RDNA3 compute unit won't be as independent as the ones on the original RDNA or even RDNA2, which begins to see groups of two CUs share common resources.

Another set of rumors suggest that AMD won't play NVIDIA's game of designing GPUs with wide memory bus widths, and instead build on its Infinity Cache technology, by increasing the on-die cache size and bandwidth, while retaining "affordable" discrete memory bus widths, such as 256-bit. As for the chip itself, it's rumored that the top RDNA3 part, the so-called "Navi 31," could feature a multi-chip module design (at least two logic dies), each with 30 WGPs. Each of the two is expected to be built on a next-gen silicon fabrication node that's either TSMC N5 (5 nm), or a special 6 nm node TSMC is designing for AMD. Much like the next-generation "Lovelace" architecture by NVIDIA, AMD's RDNA3 could see the light of the day only in 2022.

NVIDIA's upcoming "Ada Lovelace" architecture, both for compute and graphics, is reportedly being designed for the 5 nanometer silicon fabrication node by TSMC. This marks NVIDIA's return to the Taiwanese foundry after its brief excursion to Samsung, with the 8 nm "Ampere" graphics architecture. "Ampere" compute dies continue to be built on TSMC 7 nm nodes. NVIDIA is looking to double the compute performance on its next-generation GPUs, with throughput approaching 70 TFLOP/s, from a numeric near-doubling in CUDA cores, generation-over-generation. These will also be run at clock speeds above 2 GHz. One can expect "Ada Lovelace" only by 2022, as TSMC N5 matures.