Wednesday, September 7th 2011

MSI Calls Bluff on Gigabyte's PCIe Gen 3 Ready Claim

In August, Gigabyte made a claim that baffled at least MSI, that scores of its motherboards are Ready for Native PCIe Gen. 3. Along with the likes of ASRock, MSI was one of the first with motherboards featuring PCI-Express 3.0 slots, the company took the pains to educate buyers what PCI-E 3.0 is, and how to spot a motherboard that features it. MSI thinks that Gigabyte made a factual blunder bordering misinformation by claiming that as many as 40 of its motherboards are "Ready for Native PCIe Gen. 3." MSI decided to put its engineering and PR team to build a technically-sound presentation rebutting Gigabyte's claims.

More slides, details follow.

MSI begins by explaining that PCIe support isn't as easy as laying a wire between the CPU and the slot. It needs specifications-compliant lane switches and electrical components, and that you can't count on certain Gigabytes for future-proofing.

MSI did some PCI-Express electrical testing using a 22 nm Ivy Bridge processor sample.
MSI claims that apart from the G1.Sniper 2, none of Gigabyte's so-called "Ready for Native PCIe Gen. 3" motherboards are what the badge claims to be, and that the badge is extremely misleading to buyers. Time to refill the popcorn bowl.
Source: MSI
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286 Comments on MSI Calls Bluff on Gigabyte's PCIe Gen 3 Ready Claim

#101
neliz
jfk1024WHY IS MSI WRONG? ...because the PCI-e 3.0 physical layer is the same as PCI-e 2.0.
If you read the presentation, you also see the other components that need be used besides the switches.
You can't just expect a 5 GT/s circuitry to handle 8GT/s data without issues.
Ultim8Cadaveca it could come back and bite everyone in the ass though apart from gigabyte.
lol
I fail to see how you can not do a complete ROM reflash on any mainboard and require a dual bios for this since it's pretty much standard business in the server world.

Unless of course, one certain company that likes to promote dual bios'es on their boards would tell the press that "it might" and "it could" to make people afraid.
jfk1024PS: Probably MSI needs a PCI-E 3.0 GPU to make some real "testing"
Yes, or a simple Gen3 card with test chip.
Posted on Reply
#102
Ultim8
Neliz it does, The controller is on the cpu.

For multi gpu yes you need PCIe3 switches for the bridge but Gigabyte have given all there 6 series pci gen3 for the first slot at least.
Posted on Reply
#103
RoutedScripter
HAHAHA lol big win for MSI PR .... what a good oportunity taken for some technical explanation which might not only win over people to buy msi boards but also make better company image

shame on you gigabyte ... would expected it to be asus
Posted on Reply
#104
neliz
Ultim8Neliz it does, The controller is on the cpu.

For multi gpu yes you need PCIe3 switches for the bridge but Gigabyte have given all there 6 series pci gen3 for the first slot at least.
Let me make this VERY clear for you. in a LOT of these boards, data travels through the PCI express switches as it NEEDS TO.
Otherwise it's impossible to switch the first slot between x16 and x8.

Posted on Reply
#105
Ultim8
nelizLet me make this VERY clear for you. in a LOT of these boards, data still travels to the PCI express switches as it NEEDS TO.
Otherwise it's impossible to switch the first slot between x16 and x8.

www.techpowerup.com/img/11-09-07/41g.jpg
Only if you use the 2nd slot, if you dont use the 2nd slot you dont need the switch.....then there is no bottle neck. Get it.
Posted on Reply
#106
neliz
Ultim8Only if you use the 2nd slot, if you dont use the 2nd slot you dont need the switch.....then there is no bottle neck. Get it.
Sorry, but if you don't know the first thing about how a Sandy Bridge CPU switches between 16/0 and 8/8 and why the switch chips are there and how the traces work. .I'll need to use mspaint to draw pictures. HOLD ON! :)
Posted on Reply
#107
jfk1024
nelizIf you read the presentation, you also see the other components that need be used besides the switches.
You can't just expect a 5 GT/s circuitry to handle 8GT/s data without issues.
The physical links are the same. So... i know you need a new physical link for every new coding, but you can also use the same physical link to transfer different encoded data.
Posted on Reply
#108
neliz
jfk1024The physical links are the same. So... i know you need a new physical link for every new coding, but you can also use the same physical link to transfer different encoded data.
you're talking about PCI Express 2.1 then? Which, with 128/130 encoding has exactly the same BW as PCI Express 2.0?
Posted on Reply
#109
Ultim8
lol.

Right the pcie controller is on the cpu do you agree?

So if the controller is on the cpu and the traces are identical (They are) then why wont a single graphics card work at 16x gen3?

The switch is only used one a 2nd gpu is inserted
Posted on Reply
#110
neliz
PCI Express switching 101:

On top the CPU
8 PCIe lanes go the the first slot
8 PCIe lanes go the the 4 PCI express switches
If no card is detected in the second slot, all traffic will go to slot 1
The clock gen for the second PCIe card is actually housed in the PCH/southbridge

The only way to do 8/8 is by having switches and a setup like in the picture below
NO switches, IE all 16 lines are going straight from the CPU to the first slot results in 16/4 setups for crossfire for instance.

Posted on Reply
#111
n-ster
nelizNo, Don't be ashamed, you were right and n-ster got stuck in Gigabyte's quagmire of lies, since the press release said that their ENTIRE (yeah ENTIRE!) 6 series line-up was compatible:

www.gigabyte.us/press-center/news-page.aspx?nid=1048
I never said GB did or did not lie, I was just showing the UD7 thing that the other was talking about.
nelizPCI-E 2.0 x16 is slower than PCI-E 3.0 x8.
I've talked with some knowledgeable MB folks and they all say that the CPUs will stay in 2.0 x16 mode when you install a PCI-E 3.0 card in it without the proper switches.
I might sound stupid, but...



PCI-E 2.X is 5GT/s, but with the overhead, it is actually closer to 4GT/s, so 16 lanes of 2.X should be equivalent to 8 lanes of PCI-E 3.0 no?
Posted on Reply
#112
jfk1024
nelizyou're talking about PCI Express 2.1 then? Which, with 128/130 encoding has exactly the same BW as PCI Express 2.0?
let's just wait until the ivy bridge and pci-e 3.0 gpu are released. Until then, It's just speculation.
Posted on Reply
#113
Ultim8
nelizPCI Express switching 101:

On top the CPU
8 PCIe lanes go the the first slot
8 PCIe lanes go the the 4 PCI express switches
If no card is detected in the second slot, all traffic will go to slot 1
The clock gen for the second PCIe card is actually housed in the PCH/southbridge

The only way to do 8/8 is by having switches and a setup like in the picture below
NO switches, IE all 16 lines are going straight from the CPU to the first slot results in 16/4 setups for crossfire for instance.

i54.tinypic.com/kb57ko.jpg
Exactly so the first slot will be gen3 x16 as long as the other pcie lanes are not occupied.
This is what i said from the beginning
Posted on Reply
#114
cadaveca
My name is Dave
Ultim8This is what i said from the beginning
But that is not possible. what will happen is that the primary slot will only get x8 link that is PCIe 3.0, and the other 8 lanes will not be capable of 3.0 due to the board's hardware in the link. This may create situation where the slot defaults to PCIe 1.0, or perhaps 2.0, because of the lane confusion.


TBH, I'm not sure, exactly, what will happen with these boards and the primary slot. It's not as simple as it seems.
Posted on Reply
#115
neliz
Ultim8Exactly so the first slot will be gen3 x16 as long as the other pcie lanes are not occupied.
This is what i said from the beginning
The first slot is X16 because they go through the PCI express switches :) so they ARE NOT GEN3 :)

I've highlighted it on a gigabyte board so you can see where the lanes are coming from.

Posted on Reply
#116
Ultim8
n-sterI never said GB did or did not lie, I was just showing the UD7 thing that the other was talking about.



I might sound stupid, but...

img.techpowerup.org/110908/Capture010.png

PCI-E 2.X is 5GT/s, but with the overhead, it is actually closer to 4GT/s, so 16 lanes of 2.X should be equivalent to 8 lanes of PCI-E 3.0 no?
PCIe3 8 will be faster as 128/130 encoding is ~1.5% loss
Posted on Reply
#117
Ultim8
But Neliz even from that diagram the PCIe switches are only touched or needed when a second pcie device is installed???
Posted on Reply
#118
[H]@RD5TUFF
sneekypeetI wasn't saying GB is more right than MSI. Just that MSI isn't any better;)
Exactlly there you really can't trust either, but I trust Gigabyte the least.
Posted on Reply
#119
neliz
n-sterI might sound stupid, but...
I think it will :p
PCI-E 2.X is 5GT/s, but with the overhead, it is actually closer to 4GT/s, so 16 lanes of 2.X should be equivalent to 8 lanes of PCI-E 3.0 no?
No! :)

How to calculate PCI Express bandwidth:
Transfer rate * encoding

PCI Express Gen2:
Transfer rate: 5GT/s = 5000 Gb/s = 625 GB/s
625 * 8/10 (encoding) = 500 MB/s
PCI Express = Full duplex, so total bandwidth = 500*2 = 1GB/s

16 lanes*1GB/s = 16GB/s

PCI Express Gen3:
Transfer rate: 8GT/s = 8000Gb/s = 1000 GB/s
1000 * 128/130 = 984.6154 GB/s
PCI Express = Full Duplex, so total bandwidth = 984.6154 * 2 = 1969.2308
8 lanes *1969.2308GB/s = 15753.8464 GB/s
Ultim8But Neliz even from that diagram the PCIe switches are only touched or needed when a second pcie device is installed???
No, PLEASE, check the picture:

You can see that only 8 lanes are connected to the CPU (on top) the other 8 lanes come from the PCI express switches.
If you have a good high res picture of a board you can actually SEE the traces from the switch to the slot.

Posted on Reply
#120
jfk1024
nelizI think it will :p




No, PLEASE, check the picture:

You can see that only 8 lanes are connected to the CPU (on top) the other 8 lanes come from the PCI express switches.
If you have a good high res picture of a board you can actually SEE the traces from the switch to the slot.

i56.tinypic.com/9ir7lf.jpg
Do you believe yourself saying that?
Posted on Reply
#121
neliz
jfk1024Do you believe yourself saying that?
Yes, do you have any reason to doubt?
Please prove me wrong because I hate it when I make big mistakes in public :)
Posted on Reply
#122
jfk1024
nelizYes, do you have any reason to doubt?
Please prove me wrong because I hate it when I make big mistakes in public :)
when the second pci-e slot is NC the SW is OFF so all the PCI-e lanes are directly connected to the CPU.
Posted on Reply
#123
n-ster
so PCI-E 2.X x16 is faster than PCI-E 3.0 x8... So speed-wise, PCI-E 2.X x16 is already pushing PCI-E 3.0 bandwidth, although in an 8 lane configuration
Posted on Reply
#124
neliz
jfk1024when the second pci-e slot is NC the SW is OFF so all the PCI-e lanes are directly connected to the CPU.
No because I just showed in the picture above that only 8 lanes are directly connected to the CPU, the other 8 lanes COME FROM THE SWITCH.

If you can show me a pericom switch that has a supersecret awesomemode where it magically transforms from a 5GT/s switch to a 8GT/s passive transceiver, you've got me convinced.
Otherwise, I have NO idea where you get your information from that the Gen2 switches can turn themselves of and do some mystical rerouting.
n-sterso PCI-E 2.X x16 is faster than PCI-E 3.0 x8... So speed-wise, PCI-E 2.X x16 is already pushing PCI-E 3.0 bandwidth, although in an 8 lane configuration
Gigabyte's wording was "Gen3 maximum bandwidth" which would be 32GB/s not 16GB/s
Posted on Reply
#125
Steven B
no when there no device in second slot the lanes are directed toward slot 1 for full 16x. The whole does with having lanes directly connected is because it saves money on switches that aren't needed.
Posted on Reply
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