Tuesday, September 18th 2018
AMD Readying a 10-core AM4 Processor to Thwart Core i9-9900K?
To sustain its meteoric rise at the stock markets, AMD needs to keep investors convinced it has a competitive edge over Intel, even if it means investing heavily on short-term roadmap changes. According to an Elchapuzas Informatico article, AMD could be working on a new 10-core/20-thread processor for the AM4 platform, to compete with the upcoming Core i9-9900K 8-core/16-thread processor from Intel. The said processor is being labeled "Ryzen 7 2800X" and plastered over CineBench nT screenshots, where due to the sheer weight of its 10 cores, it tops the nT test in comparison to Intel's mainstream-desktop processors, including the 2P Xeon X5650 12-core/24-thread.
The Forbes article that cites the Elchapuzas Informatico, however, is skeptical that AMD could make such a short-sighted product investment. It believes that development of a 10-core die on existing "Zen+" architecture could warrant a massive redesign of the CCX (Zen Compute Complex), and AMD would only get an opportunity to do so when working on "Zen 2," which AMD still expects to debut by late-2018 on its EPYC product line. We, however, don't discount the possibility of a 10-core "Zen+" silicon just yet. GlobalFoundries, AMD's principal foundry partner for CPUs, has given up on 7 nm, making the company fall back to TSMC to meet its 7 nm roadmap commitments. TSMC already has a long list of clientele for 7 nm, including high-volume contracts from Apple, Qualcomm, and NVIDIA. This could force AMD to bolster its existing lineup as a contingency for delays in 7 nm volume production.
Source:
Forbes
The Forbes article that cites the Elchapuzas Informatico, however, is skeptical that AMD could make such a short-sighted product investment. It believes that development of a 10-core die on existing "Zen+" architecture could warrant a massive redesign of the CCX (Zen Compute Complex), and AMD would only get an opportunity to do so when working on "Zen 2," which AMD still expects to debut by late-2018 on its EPYC product line. We, however, don't discount the possibility of a 10-core "Zen+" silicon just yet. GlobalFoundries, AMD's principal foundry partner for CPUs, has given up on 7 nm, making the company fall back to TSMC to meet its 7 nm roadmap commitments. TSMC already has a long list of clientele for 7 nm, including high-volume contracts from Apple, Qualcomm, and NVIDIA. This could force AMD to bolster its existing lineup as a contingency for delays in 7 nm volume production.
133 Comments on AMD Readying a 10-core AM4 Processor to Thwart Core i9-9900K?
Years ago, when AMD released 3 core CPU's, people said it wasn't possible or AMD couldn't do it because this, that or the other thing. They did it anyway. When Intel released the Core series of CPU's and claimed that it was a massive leap forward and that the bottom tier Core CPU's could stand their ground with the top tier Pentium series, people said it wasn't possible and yet it happened.
@Valantar, for someone like you to say a company like AMD can't do something they have literally already done is so absurd that it is almost beyond belief. It is preposterous for you, or anyone else, to say with any level of credibility that a 10 core, or even an 11 core, CPU can not be produced by a company that has already produced CPU's with over triple that core count in mass amounts. So when I said that your opinions are not very good, it is because they lack logic, reason and merit, but also stand in the face of known technological, scientific and historical facts. Those arguments are as incredulous and vapid as they are illogical.
- I didn't say AMD didn't have the resources to do this, I said it wouldn't make sense to waste resources on a one-off product added to an existing product line that wouldn't stand a chance to recoup the R&D costs.
- "A rebadge of Threadripper dies" makes no sense, given that all Ryzen dies on the same process are the same die, just different bins. Ryzen 1000, TR 1000 and Epyc 1st gen are all the same die. Ryzen 2000 and TR 2000 is also the same die. Ryzen 3000 (and likely TR 3000) will in all likelihood be the same (Zen2) die as 7nm Epyc.
- Whether these were "Threadripper dies" or not, it doesn't take away from the inherent issues with cramming two dice within the confines of an AM4 package. This would require a thicker/more complex substrate, which would mess with cooler compatibility, at the very least. Nor would getting the IF traces implemented be an easy task in a package that small.
- The need for symmetric CCXes within a die is a documented feature of the Ryzen architecture. Of course AMD isn't flaunting this, but I've seen it reported from reputable sources that asymmetrical disabling of cores is impossible with the current design. This might change with Zen2, or it might not - we don't know.
- Previous 3-core AMD chips were all based on a fundamentally different design from Zen. Don't see how this is applicable. Sure, the concept has been realized before, but with an entirely different basis.
Beyond this, nothing you've said is really applicable. TR and Epyc are MCM products, while the AM4 has no such thing. Making one wouldn't be impossible, but complicated, expensive, and would introduce the same issues we see with TR for consumer-facing applications (NUMA awareness, latency, etc.). It doesn't seem reasonable whatsoever that AMD would spend a significant amount of money on this when it would be obsolete in 6-8 months when 7nm Zen2 Ryzen CPUs arrive.Of course, a 10-core could be a 7nm chip based on a 2x8-core Zeppelin (with three cores disabled per CCX) - but that would mean launching their first 7nm Ryzen as an afterthought product on an existing product line. Sure, the standalone launch would garner attention, but wouldn't it then make more sense for this to kickstart the 3000-series, rather than call it "2800X" and make it seem like a minor upgrade from the 2700X when it's in fact based on a significantly updated architecture?
Again: neither of these theories make sense in terms of business, economics, or engineering when factoring in the running of the business. Can it be done? Sure, probably. Would it be smart? No. And if there's one thing we can say about AMDs strategies over the last few years, they're damn smart.
Even if they went this route, I'd expect it more for Zen2. The time needed to get the silicon back from the fab and make the fixes and go through the changes needed to make it work, you're already looking at close to a year out hoping you only need to make 1 change in those 10+ metal layers.
The third option, using defective 7nm dies, doesn't make sense for strategic and marketing reasons - while launching a retail 7nm CPU in 2018 would be a triumph, it'd be a short-lived, low-volume, very expensive product that would essentially undermine the entire 3000-series when it launches next spring. And the converse option, kick-starting the 3000-series with a high-end 7nm part in late 2018, would be downright dumb in terms of marketing - the vast majority of customers would want to wait for more reasonably priced 6-8-core parts, which would then arrive more than half a year later. That's more than long enough for people to lose interest and buy whatever's available. Of course, this also presupposes that they can't use defective 7nm dice (once these enter volume production) for Epyc CPUs, which have far higher margins and would make far more sense for a low-volume part (especially as there'd be no extra R&D cost).... but they already harvest defective dice for <8-core SKUs (and 12c/24c Threadripper). No need to put them to use in any other way unless the defect rate on 12nm is far higher than what's reasonable at this stage in production. In all likelihood they're already disabling fully functioning silicon to fulfill the need for low-end silicon. And why would they design a 6-core die? Unless you're expecting next-gen APUs to have 6 cores in a single CCX, this doesn't really align with AMD's stated strategies either. And given that Epyc is confirmed to launch with 64 cores, that means that the next-gen larger CCX is 8 cores, not 6. While it does make sense to separate out consumer and enterprise silicon as sales volumes grow, it makes more sense for them to launch single-CCX =<8-core CPUs (essentially the entire consumer lineup in a single-CCX design) than having up to 6 in one CCX and 8-12 in two.That is of course true. But then again, neither can you. Unless you're working for AMD developing their CPU strategy?
If AMD thinks they can profit from a 10 core product, then they are going to do it regardless.
Fact; If AMD thinks they can benefit from the release of a 10core CPU line and it is worth their time to do so, they will without fail.
Fact; As AMD has already released CPU lines with core counts greater than 10, making a 10core line is very possible and equally plausible.
Fact; AMD has historically been known for taking advantage of any and every opportunity available, including reworking existing designs to maximize capitalization.Yeah you seem to do that quite often..And you think that because you failed to read through everything.
Fact, Raven Ridge comes with a similar half-CCX variant. One only needs to add it to the 'Summit Ridge', potentially 4+4+2.
I have been discussing the merits of this leak, as well as the engineering/marketing/sales/strategy aspects of going forward with a design like this. I think it's a genuinely bad idea. You don't. We disagree. Deal with it. This is not bashing AMD, it's the complete opposite: not wanting AMD to waste their relatively limited resources on a silly product that won't do them any good in neither the short or long term. If you read this as bashing AMD, there is something very much wrong with how you're reading this.
Now, either please reread my posts here and try to figure out what you've misunderstood, or stop replying to me. I really can't be bothered dealing with this any more, as the misunderstanding is entirely on you.
I'm not a fan of company bashing in general unless the company in question has few or no redeeming qualities. In the case of AMD, they currently hold two very important crowns in the X86 CPU market; They have the highest performing single socket CPU crown and they have the best value for money spent crown. In Intel's case, they hold the best gaming performance crown, but not by much and they may loose it. In the last 18ish months AMD has forged ahead and they show no signs of slowing down. This is good for the entire industry as it is forcing Intel to actually compete with someone other than themselves. AMD releasing a 10core CPU not only makes sense from a logistics perspective, but it makes sense from a competition perspective. A 10core offering is good for the market even if the benefit isn't large as it will show everyone that AMD doesn't just have bite, but also ability to sustain.
As for AMD having limited resources: of course they do. Arguing anything else is kind of absurd, really. They've just recently gone from losing money over multiple years to making a profit (an achievement that deserves a lot of praise, but nonetheless hasn't lasted long enough for them to have a lot of cash on hand). In terms of revenue, they're less than 1/10 the size of Intel. They're half the size of Nvidia by the same measure, and Nvidia only competes with them in half their product stack. There is zero question that AMD's R&D and silicon development budgets are far smaller than those of their competitors. What does this mean? That relative to their competition (which is the only reasonable metric), they have limited resources.
This is actually one of the absolutely brilliant things of the base Zen design and the MCM approach: they turned an economic disadvantage into a technological advantage. AMD has also clearly stated that they went for the "one die to rule them all" design approach (plus APUs, of course) for cost reasons - which, given their size and resources was very smart. I'm quite convinced they will add another design in relatively short order (for a product stack of three, not two designs), but not before 7nm is here, and to me it seems most likely for that design to be an 8-core single-CCX (given the 8-core CCXes shown by 64-core EPYC), possibly with an iGPU.
Their current silicon product stack consists of two parts: 4c+GPU and 4c+4c. If the leaks of 64-core Epycs are true, that means an 8c+8c die is incoming. That leaves a significant gap between it and the (inevitable, as more doesn't make sense for ULV mobile) 4c+GPU refresh. 10 cores in silicon would strike a weird balance here - it would require two CCXes (unless you're implying they design yet another CCX, with 10 cores, which would be more expensive), and is a core count that makes sense for low-end harvested dice from the 16-core die. Designing an in-between 8c-single-CCX (either with or without an iGPU, based on the same CCX design as the 8c+8c Zeppelin) die to fill this gap makes a lot more sense. The 8c+8c die seen in current 7nm Epyc leaks would make a single-die 10-core AM4 design quite easy (and I don't really doubt we'll see it once 7nm Ryzen launches), but launching it at this time makes no sense for either marketing or sales reasons, as I've said before. There's more money to be had by selling the same harvested dice as lower-end Epycs.
As for my posts being "bashing": in my understanding of that term, that would require me to be unequivocally and universally critical of AMD at every level; presenting them as if they had few or no redeeming qualities. Which it should be plenty clear from my posts that I haven't done whatsoever. Nor have I even actually criticized AMDs current products or strategies - quite the opposite! What I've said is that this leak, which neither aligns with AMDs public roadmaps, their stated strategies, their publicized silicon development, or their product segmentation strategy, would be a strategically bad move - in particular as any Ryzen 3000-series based off a 16-core Zeppelin would render it obsolete when it launches in 6-8 months.
Let's see:Is this bashing?Or this? Just based on these two quotes alone, you should have been entirely able to tell that I haven't been bashing - or even criticizing! - AMD. Again: this has to boil down to reading comprehension. I'm leaning towards you wanting to antagonize me or read what I'm saying in an oppositional light due to the other thread where we've been arguing, but that might be going a bit far. Still, your reading of my posts makes no sense.You're preaching to the choir here, man. This right here is exactly why it makes no sense for AMD to go off-roadmap and spend tens of millions of dollars on a 10-core piece of silicon on 12nm that will inevitably be short-lived and still won't recapture the gaming crown from Intel. To quote myself yet again:I really don't know who it is you're arguing against - it certainly isn't me.
AMD has countered Intel's mesh topology. Their counter is the IF-linked MCM design. It works wonderfully as long as your workload doesn't exceed 8 cores/16 threads per task (which very few workloads even for servers do, and the upcoming 16c/32t Zeppelins will make up for any deficiencies here). AMDs response has a latency disadvantage in some scenarios, but a whole host of advantages that more than make up for this.
What you're effectively saying here is that AMD should ditch their current (known working, performant, efficient, easy to produce) IF-connected MCM approach and spend another on-die IF link on hooking up two measly cores? Why? Those cores would still not have direct access to a memory controller (unless they make this a three-channel design, making it require a non-AM4 platform) or PCIe controller, both of which are attached to the two current CCXes.
As for your half-CCX example, care to share a link? I can't find that image in any AMD/Zen-related WikiChip page that I've looked at. And that's really besides the point: the 2-core image is showing a Raven Ridge chip with two cores disabled after production, such as the Athlon 200GE. AMD hasn't (yet, at least) made available any in-silicon CCX with any more or less the 4 physical cores. Given how small 4 cores will be on 7nm, there's little reason to believe a piece of silicon like that will ever be made.
Adding another core would bring the same latency/NUMA issues Threadripper has (in gaming and other desktop use cases) to desktop. It would basically only be able to compete better than 2700X in workstation applications, maybe not even too well at that. Additional cost, complexity, power management/usage (2 cores, additional IF links) on top of all this.
While it could be done I cannot see how that would be worth the effort.
At the same time Zen 2 is reportedly planned for 2019H1.
Whether or not your theoretical core count comes to pass who knows? I don't see them breaking up the need for symmetry in the current line of Zen considering their cadence (yearly releases). They don't have a lot of time to course correct on Zen itself with the cash they have on hand (not much), and engineering team they have (small comparative to Intel).
Anyhow, as @londiste reiterated above, x and y measurements are not the main limitation for adding a second die to AM4. Adding an internal IF link between two dice would necessitate adding layers to the substrate, making it thicker than it is. This would again make the package incompatible with the AM4 spec, meaning that a lot of coolers would no longer fit (particularly the ones with clip-on mounting, though also likely quite a few with short mounting screws). If you doubt this - have you seen a Threadripper CPU in person? If not, let me tell you from experience: the substrate is insanely thick. I took this when I was installing the 1920X in my GF's video editing workstation:
That substrate alone is thicker than an entire mobile CPU package (I googled: CFL-H is 1.49mm, and that substrate is thicker than that), and comes close to some desktop packages. Sure, the TR substrate is designed for EPYC, and thus has room for even more IF links, two extra memory channels and extra PCIe - but it's also around 4x the area of AM4. Less area means more layers for fitting the same number of traces. In other words, fitting a 2-die package with the requisite IF link inside of the restrictions of the AM4 package dimensions would be quite the challenge, if possible at all.
For reference: while not as good a picture, the AM4 package is clearly a lot thinner than the TR4 package.
Then, again, there are issues like NUMA awareness (or the lack of it), latency between the dice, leaving one die without directly connected PCIe (at the very least) and RAM (unless you run one channel off each die, which would bring its own performance issues), and so on and so forth. A package like this would probably be a decent workstation chip (even with two less memory channels than TR it would be a beast for multi-threaded workloads), but it wouldn't make sense as a high-end consumer chip.
Saying this isn't bashing AMD. It's providing sound reasoning why this rumor doesn't ring true in terms of the technology behind AMD's current offerings (and what they have publicized about their future plans). It doesn't align with what they've said, and it would only barely make sense as a product. It definitely wouldn't be a suitable "answer" to the 9700K/9900K for those who need such an answer (Intel fans or people who only play games), as it wouldn't outperform the 2700X in those applications). In short: it makes far more sense for AMD to have a bit of patience, wait until 7nm Zen2 is available in sufficient quantities for a consumer launch (which I'm willing to bet will be around April, as a yearly cadence makes sense), and blow people's minds by how good it is. Zen2 should bring both higher clocks, even better efficiency (I'm really looking forward to 7nm APUs!), and improved IPC. It should be a real triple threat. There's no reason for AMD to rush out some oddball in-between "answer" to Intel's rather desperate attempt at matching AMD's core count advantage before that.
I know about the presence of CCX variants, but that is about it. Nothing solid other than the topology clues. It would be very easy actually, since the chip is an SoC and just adding more CCX islands only insert to the existing 'SoC' layout. The core matrices are asymmetrical anyway, this whole 'symmetrical die' rumour couldn't end soon enough. Infinity Fabric is outside the respective scope.
- CCXes on the same die are also connected through Infinity Fabric. As such, IF is never beyond the scope of any multi-CCX Zen design.
- You can't "just add" parts without accounting for I/O, even if it's an SoC. Your reasoning doesn't at all account for how the parts of the SoC actually communicate or work together.
- The part about Zen requiring symmetrical CCXes is not a rumor - this has been confirmed by AMD in interviews. As for requiring symmetrical dice in MCM setups, I haven't seen that part confirmed, but it makes sense in a system architecture/resource allocation perspective. It might be possible, but making an asymmetrical MCM setup would be far more challenging to implement and balance/tune in terms of cache migration, PCIe, RAM, thread scheduling, and so on. Possibly doable, but impractical.
Now, you say "I know about the presence of CCX variants". What does that mean? Where do you know of this from? Do you know of anything that isn't simply a version with disabled silicon, like <8-core Ryzen or <4-core APUs? If so, from where? I would be very interested in reading further about this, as it would be a very unexpected turn in AMD's strategy. The only variants I've seen are the CCXes with different cache layouts between the CPU and APU CCXes. Do you know this (as in: have evidence) or is it something deduced from looking at core layouts? I don't mean to come off as too critical here, it's just that I have never seen this reported anywhere by anyone, so any new info is very interesting to me.If it was really this simple, what are you doing on here? You should be telling AMD how they're leaders are idiots and you should be running the company.