The United States, currently led by the Trump administration, could be preparing a surprise package to its close silicon ally—Taiwan. During a House GOP issues conference in Florida, US President Donald Trump announced that he would impose 25% to 100% tariffs on Taiwan-made chips, including the world's leading silicon manufacturer, TSMC. Trump addressed the conference, saying, "In the very near future, we are going to be placing tariffs on foreign production of computer chips, semiconductors, and pharmaceuticals to return production of these essential goods to the United States. They left us and went to Taiwan; we want them to come back. We do not want to give them billions of dollars like this ridiculous program that Biden has given everybody billions of dollars. They already have billions of dollars. […] They did not need money. They needed an incentive. And the incentive is going to be they [do not want to] pay a 25%, 50% or even a 100% tax."

The issue for TSMC is its massive reliance on US companies to drive revenue. The majority of its cutting-edge silicon is going to only a handful of companies, including Apple, NVIDIA, Qualcomm, and Broadcom. With tariffs, the supply chain economics, especially in the world of semiconductors, will break. TSMC's most significant export country is the US, and US companies with trillions of US Dollars of market capitalization rely on Taiwanese silicon. As a result, TSMC will most likely raise its wafer prices, with results trickling down to US companies raising their product prices with additional price hikes. TSMC plans to bring its advanced manufacturing on American soil, but given that these tariffs might break the economic model it currently operates under, it may need to happen sooner. Taiwan-based silicon giant has planned to leave US facilities trailing behind by a generation or two of advanced manufacturing, while domestic facilities produce the newest nodes. If Trump decides to go through tariffs, TSMC could make additional changes to its US-based manufacturing plans.

The DeepSeek open-source large language model from China has been the hottest topic in the AI industry over the weekend. The model promises a leap in performance over OpenAI and Meta, and can be accelerated by far less complex hardware. The AI enthusiast community has been able to get it to run on much less complex accelerators such as the M4 SoCs of Mac minis, and gaming GPUs. The model could cause companies to reassess their AI strategy completely, perhaps pulling them away from big cloud companies, toward local acceleration on cheaper hardware; and cloud companies themselves would want to reconsider their orders of AI GPUs in the short-to-medium term.

All this puts the supply chain of AI acceleration hardware in a bit of a spot. The NVIDIA stock is down 12 percent in pre-market trading as of this writing. Microsoft and Meta Platforms also faced a cut, shedding over 3% each. Alphabet lost 3% and Apple 1.5%. Microsoft, Meta and Apple are slated to post their quarterly earnings this week. Companies within NVIDIA's supply chain, such as ASML and TSMC, also saw drops, with ASML and ASM International losing 10-14% in European pre-trading.

Earlier this week, Taiwan experienced a magnitude 6.4 earthquake—this seismic event interrupted manufacturing activities at several TSMC chip-making facilities. As a precaution, foundry employees in both Central and Southern Taiwan were evacuated. Production resumed fairly quickly following inspections of crucial infrastructure—no major damage to facilities or equipment was noted. The latest reports suggest that a relatively minor number of TSMC wafers have been affected by the recent quake, while some recalibration of instrumentation is required to get things back on track.

Inside sources reckon that up to 20,000 wafers (possibly 10,000 at a minimum) could be scrapped—assessments are reportedly still underway, but a small proportion of client shipments could be disrupted. News articles point to this total being spread across three affected locations. Fab 18 is a key 3 nm production hub—situated in Taiwan's Southern Science Park, Tainan's Fab 14 specializes in 4 nm and 5 nm processes, and Fab 8 (Hsinchu) takes care of 200 nm. Industry experts believe that TSMC will bounce back quickly, and that the damaged wafer count represents a minor dent in the proverbial armor—on a good day, manufacturing output can reach up to 37,000 units.

In the early hours of Tuesday, a magnitude 6.4 earthquake struck near a remote mountainous region roughly 24 miles southeast of Chiayi in Taiwan, causing temporary operational halts at multiple TSMC facilities. The tremor occurred at 12:17 AM local time and was felt in Tainan, home to four of TSMC's manufacturing sites. Workers in both Central and Southern Taiwan were evacuated as a precaution, following standard company protocols designed to ensure employee safety. TSMC initiated thorough structural inspections immediately after the quake. According to company representatives, all crucial infrastructure, such as water supply and power systems, remained fully functional. With no significant damage detected during safety assessments, TSMC has gradually restarted its production lines, minimizing any long-term impact on its global client base.

Despite the relatively brief disruption, the incident exposes the fragility of the semiconductor manufacturing process. Taiwan's frequent seismic activity has the potential to affect the complex manufacturing processes crucial for producing silicon. Given the company's massive consumption of chemicals and silicon ingots, any significant production setbacks at TSMC can resonate through global supply chains. To reduce these geographical and nature-inspired risks, TSMC is investing heavily in new manufacturing facilities elsewhere, notably in Arizona. Although these sites are expected to enhance the company's resilience, they will only account for around 10% of TSMC's total production capacity. Additionally, as TSMC doesn't plan to bring state-of-the-art production to other sites, the company must implement safety features against earthquake protection in its Taiwan facilities to continue production. A minor manufacturing hiccup can equate to billions of losses across the supply chain.

C.C. Wei, TSMC CEO and Chairman, has shared his latest views regarding his company's North American manufacturing center—Reuters cornered him for comment during a mid-week appearance at a National Taiwan University-held event. The Taiwanese government has recently lowered its "silicon shield"—following much (reported) deliberation over "legal restrictions on transferring leading-edge process technology overseas." This relaxation of rules has TSMC considering a new set of investments for operations outside of Taiwan—with an expansion into advanced node process manufacturing. Currently, 2 nm (N2) is a home turf-speciality—industry experts estimate an expenditure of $28-30 (USD) billion to bring this production technology over to the States. TSMC's CEO has described additional challenges—on top of (and impacting) finances—local bureaucracy is a big one.

Wei stated: "every step requires a permit, and after the permit is approved, it takes at least twice as long as in Taiwan." According Reuters, he reckons that it would be difficult for their North American sites to access the latest technologies ahead of teams in Taiwan. He detailed his company's recruitment of several experts—tasked with talking to local government; about regulatory issues. This was not a cheap undertaking: "we ended up establishing 18,000 rules, which cost us $35 million." TSMC's Arizona production hub will (eventually) consist of three large factories—despite long-term teething problems, Fab 21 is reported to be churning out the first wave of "Made in America" product for a very important client: Apple. Wei expressed positives views when asked about the USA site's prospects—during an earnings conference (Jan 16)—he believes that it will eventually produce the "same quality of chips as in Taiwan," through a "smooth ramp-up process."

Samsung's native foundry operations have wrestled with the 3 nm Gate-All-Around (GAA) process—these problems have persisted since the first reports of "missed production targets" emerged late last year—online speculators floated a very disappointing yield figure: only 20%. Last December, industry moles proposed that the South Korean technology giant had devised plans to form an Exynos-centric "multi-channel partnership" with rival chipmakers. Speculation pointed to TSMC being the only valid ally. Semiconductor industry tipster—Jukanlosreve—believes that negotiations have taken place, and the answer was a firm "no." TSMC's most advanced node process order books are likely filled up with more important customers—industry watchdogs reckon that Apple usually gets first dibs.

Taiwan's top semiconductor manufacturer leads the market with its cutting-edge lithography techniques. Insiders believe that Samsung was impressed by TSMC's 2 nm trial production runs achieving (rumored) 60% yields. The higher-end Exynos chipsets are normally produced with the best node process available, but missed manufacturing goals have caused Samsung to drop in-house tech. In the recent past, Qualcomm's most powerful Snapdragon mobile chipsets have been deployed on flagship Galaxy S smartphones. Jukanlosreve believes that TSMC rejected Samsung's proposed Exynos deal due to a fear of revealing too many "trade secrets." Potentially, the South Koreans could have learned a thing or two about improving yields—courtesy of TSMC's expert knowledge.

TSMC (TWSE: 2330, NYSE: TSM) today announced consolidated revenue of NT$868.46 billion, net income of NT$374.68 billion, and diluted earnings per share of NT$14.45 (US$2.24 per ADR unit) for the fourth quarter ended December 31, 2024. Year-over-year, fourth quarter revenue increased 38.8% while net income and diluted EPS both increased 57.0%. Compared to third quarter 2024, fourth quarter results represented a 14.3% increase in revenue and a 15.2% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, fourth quarter revenue was $26.88 billion, which increased 37.0% year-over-year and increased 14.4% from the previous quarter. Gross margin for the quarter was 59.0%, operating margin was 49.0%, and net profit margin was 43.1%. In the fourth quarter, shipments of 3-nanometer accounted for 26% of total wafer revenue; 5-nanometer accounted for 34%; 7-nanometer accounted for 14%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 74% of total wafer revenue.

The latest news reports suggest that Apple is currently verifying the quality of TSMC Arizona-made chips—the process has reached a "final test stage" with samples from an initial batch being compared to "Made in Taiwan" product. TSMC's native foundries—utilizing the latest cutting-edge technologies—are accustomed to pumping out plenty of high-quality and advanced chips. Nikkei Asia believes that an approval—if USA-made silicon passes muster—will result in commercial mass-produced chips being delivered as soon as Q1 2025. This would be a significant victory for TSMC's relatively new Arizona fab—reported teething problems have caused delays and budgets to balloon. Apple could be the first of TSMC's customers to send products to market that have Arizona-manufactured silicon onboard.

Taiwan's chip-making industry is facing an uncertain future due to regional political tensions—in reaction, the nation's government has started shifting its stance on guarding TSMC's most advanced production processes. Leading-edge process technologies could be heading overseas, with new investments being considered at the Arizona campus. TSMC and Amkor are working on setting up advanced packaging and test facilities at the Peoria location, so current logistics are not ideal—US-made product has to be sent to an Amkor packaging facility in Taiwan. TSMC USA's future looks quite promising—AMD and NVIDIA are reportedly the next in line to receive locally produced samples for verification. Industry moles reckon that Team Green's advanced "Blackwell" AI GPUs could be produced in Peoria—based on alleged partnership negotiations from late last year.

According to a well-known industry analyst, Ming-Chi Kuo, NVIDIA has restructured its "Blackwell" architecture roadmap, emphasizing dual-die designs using CoWoS-L packaging technology. The new roadmap eliminates several single-die products that would have used CoWoS-S packaging, changing NVIDIA's manufacturing strategy. The 200 Series will exclusively use dual-die designs with CoWoS-L packaging, featuring the GB200 NVL72 and HGX B200 systems. Notably absent is the previously expected B200A single-die variant. The 300 Series will include both dual-die and single-die options, though NVIDIA and cloud providers are prioritizing the GB200 NVL72 dual-die system. Starting Q1 2025, NVIDIA will reduce H series production, which uses CoWoS-S packaging, while ramping up 200 Series production. This transition indicates significantly decreased demand for CoWoS-S capacity through 2025.

While B300 systems using single-die CoWoS-S are planned for 2026 mass production, the current focus remains on dual-die CoWoS-L products. From TSMC's perspective, the transition between Blackwell generations requires minimal process adjustments, as both use similar front-end-of-line processes with only back-end-of-line modifications needed. Supply chain partners heavily dependent on CoWoS-S production face significant impact, reflected in recent stock price corrections. However, NVIDIA maintains this change reflects product strategy evolution rather than market demand weakness. TSMC continues expanding CoWoS-R capacity while slowing CoWoS-S expansion, viewing AI and high-performance computing as sustained growth drivers despite these packaging technology transitions.

Last November, Taiwan's National Science and Technology Council indicated that it was considering a relaxation of "legal restrictions on transferring leading-edge process technology overseas." TSMC is the nation's most prized chip foundry, but new manufacturing operations are spreading across the globe. The very best node processes—currently TSMC's advanced 2 nm (N2)—have been restricted to home turf, yet global tensions have prompted the Taiwanese government to reconsider its guarded approach. A freshly published Taipei Times report has focused on an important announcement made at a recent government press conference. Taiwan's Minister of Economic Affairs of Taiwan, J.W. Kuo, stated that TSMC is now allowed to manufacture 2 nm chips on foreign soil—according to him, the foundry behemoth is "cautiously" evaluating an investment of roughly $28 to 30 (USD) billion into 2-nanometer production facilities Stateside.

His colleagues have worked hard—in the past—on preserving the country's "Silicon Shield," but fresh adjustments are sweeping in. Kuo commented: "those were old-time rules. Times have changed." TSMC's—allegedly costly—North American hub is reportedly marked down for a "by 2030" push into 2 nm process territories. Taiwan's Economic Affairs minister continued with his reasonings: "Private businesses should make their own business decisions based on their own technological progress...The basic principle is that businesses can make profits from their overseas investments. TSMC is building factories in the US with the aim of serving its US customers, as 60 percent of the world's chip-designing companies are based in the US." He also downplayed concerns regarding possible upcoming shifts in US trade policy making—Taiwan's "strong technological capabilities" are expected to weather the storm. Newly implemented US trade tariffs are expected to have only a "minor impact."

TSMC is reportedly making decent progress with its advanced 2 nm (N2) node—industry news pieces from earlier this month pointed to the initiation of production lines across three fabrication sites. Taiwan's Economic Daily News has kept close tabs on these trial runs—insiders have indicated that TSMC's Kaohsiung plant is capable of matching the Baoshan location's targeted manufacturing output (5000 wafers per month, 60 percent yield). Reports suggest that the Kaohsiung 2 nm trial production will start up later this month—much earlier than anticipated.

The Taiwanese chip foundry giant is taking on the challenge of meeting "greater than expected" demand for its new generation 2 nm product—TSMC chairman C.C. Wei has previously stated that its latest and greatest is more popular (pre-launch) with customers than older 3 nm lines. Apple is rumored to be first in line—not a big surprise since TSMC has (supposedly) rolled out the VVIP red carpet for them in recent times. The Economic Daily News article also mentions Qualcomm and MediaTek being next in the queue for N2. TSMC's best foundries are expected to initiate mass production by the end of 2025.

ADATA brought some innovative storage products to the 2025 International CES. The XPG MARS 970 Storm is an M.2 NVMe Gen 5 SSD with a self-contained liquid cooling loop. Its construction involves a baseplate from which heat is conventionally transferred to a cylindrical heat dissipation surface—a sort of radiator, where a pair of tiny 20 mm fans push and pull air through, to keep the controller cool. Speaking of which, the drive is based on the Silicon Motion SM2508 flagship controller that's built on the TSMC 6 nm process. It comes in capacities of up to 8 TB. ADATA claims sequential transfer speeds of up to 14 GB/s reads, with up to 12 GB/s writes.

You can have this drive without this cooling solution (eg: if you have a nice one of your own from your motherboard). It's called the MARS 970 Blade. It can be used without a cooler, but performance will be lesser. ADATA hence advertises sequential speeds of up to 12 GB/s reads, with up to 10 GB/s writes. The MARS 970 Blade strangely only comes in capacities of up to 4 TB—there's no 8 TB variant.

AMD at the 2025 International CES announced the Radeon RX 9070 XT and Radeon RX 9070 desktop performance-segment graphics cards. These will be the face of AMD's next generation of gaming graphics products, and will be powered by the new RDNA 4 graphics architecture. AMD hopes to launch both cards within Q1 2025. AMD changed the nomenclature of its gaming GPUs mainly because it has made a tactical retreat from the enthusiast graphics segment, its fastest products will compete in the performance segment. From the way AMD arranged the Radeon RX 9070 series and 9060 series product stack against the backdrop of the Radeon RX 7000 series, the GeForce RTX 4000 series, and the anticipated GeForce RTX 5000 series, the RX 9070 XT will offer performance roughly similar to the Radeon RX 7900 XT in raster, with the RX 9070 being slightly faster than the RX 7800 XT. The RX 9060 XT will beat the RX 7700 XT, while the RX 9060 beats the RX 7600 XT.

With RDNA 4, AMD claims generational SIMD performance increase on the RDNA 4 compute units. The 2nd Gen AI accelerators will boast of generational performance increase, and AMD will debut a locally-accelerated generative AI application down the line, called the AMD Adrenalin AI, which can generate images, summarize documents, and perform some linguistic/grammar tasks (rewriting), and serve as a chatbot for answering AMD-related queries. This is basically AMD's answer to NVIDIA Chat RTX. AMD's 3rd Gen Ray accelerator is expected to reduce the performance cost of ray tracing, by putting more of the ray tracing workload through dedicated hardware, offloading the SIMD engine. Lastly, AMD is expected to significantly upgrade the media acceleration and display I/O of its GPUs.

Hong Kong tech media HKEPC report indicates that NVIDIA's GeForce RTX 5080 graphics card will launch on January 21, 2025. The release follows a planned announcement event on January 6, where CEO Jensen Huang will present the new "Blackwell" architecture. Anticipated specifications based on prior rumors point to RTX 5080 using GB203-400-A1 chip, containing 10,752 CUDA cores across 84 SM. The card maintains 16 GB of memory but upgrades to GDDR7 technology running at 30 Gbps, while other cards in the series are expected to use 28 Gbps memory. The graphics card is manufactured using TSMC's 4NP 4 nm node. This improvement in manufacturing technology, combined with architectural changes, accounts for most of the expected performance gains, as the raw CUDA core count only increased by 10% over the RTX 4080. NVIDIA is also introducing larger segmentation between its Blackwell SKUs, as the RTX 5090 has nearly double CUDA cores and double GDDR7 memory capacity.

NVIDIA is organizing a GeForce LAN event two days before the announcement, marking the return of this gathering after 13 years, so the timing is interesting. NVIDIA wants to capture gamer's hearts with 50 hours of non-stop gameplay. Meanwhile, AMD currently has no competing products announced in the high-end graphics segment, leaving NVIDIA without direct competition in this performance tier. This market situation could affect the final pricing of the RTX 5080, which will be revealed during the January keynote. While the January 21 date appears set for the RTX 5080, launch dates for other cards in the Blackwell family, including the RTX 5090 and RTX 5070 series, remain unconfirmed. NVIDIA typically releases different models in their GPU families on separate dates to manage production and distribution effectively.

TSMC is making progress with its most advanced 2 nm (N2) node, a recent report from MoneyDJ quoting industry sources indicates that the company is setting up a test production line at the Hsinchu Baoshan fab (Fab 20) in Taiwan. In the early stages, TSMC aims for small monthly outputs with about 3,000-3,500 wafers. However, the company has big plans to combine production from two factories in Hsinchu and Kaohsiung, TSMC expects to deliver more than 50,000 wafers monthly by the end of 2025 and by the end of 2026 projecting a production of around 125,000 wafers per month. Breaking it down by location, the Hsinchu factory should reach 20,000-25,000 wafers monthly by late 2025, growing to about 60,000-65,000 by early 2027. Meanwhile, the Kaohsiung factory is expected to produce 25,000-30,000 wafers monthly by late 2025, also increasing to 60,000-65,000 by early 2027.

TSMC's chairman C.C. Wei says there's more demand for these 2 nm chips than there was for the 3 nm. This increased "appetite" for 2 nm chips is likely due to the significant improvements this technology brings: it uses 24-35% less power, can run 15% faster at the same power level, and can fit 15% more transistors in the same space compared to the 3 nm chips. Apple will be the first company to use these chips, followed by other major tech companies like MediaTek, Qualcomm, Intel, NVIDIA, AMD, and Broadcom.

TSMC's new semiconductor manufacturing facility in Phoenix, Arizona, will face production costs approximately 30% higher than its Taiwan-based operations when it begins mass production in early 2025. The increased expenses stem from higher tariffs and transportation costs associated with importing necessary materials from Taiwan. The Arizona facility will start producing 10,000 12-inch wafers monthly using a 4 nm node, with plans to double output to 20,000 wafers at full capacity. Four major technology companies—Apple, NVIDIA, AMD, and Qualcomm—have committed to purchasing chips from the plant for their AI and high-performance computing needs. The 445-hectare facility highlights ongoing challenges in America's semiconductor industry. Despite the aim to strengthen domestic chip manufacturing, the plant must import materials from Taiwan to maintain production quality, revealing gaps in the US semiconductor supply chain.

This overseas dependency drives up operational costs significantly. While TSMC's investment marks an essential step in rebuilding domestic capacity, the substantial cost difference between US and Taiwanese production raises questions about long-term viability. TSMC has already begun trial production at the site and plans to expand operations with additional phases. The company's Phase 2 facility is completed, and equipment is being installed, while future expansions aim to produce 2 nm chips by 2028. However, unless the cost gap narrows, the higher production expenses could impact the plant's competitiveness in the global semiconductor market, even competing with its own Taiwanese facilities, where customers could decide to use Taiwanese fabs due to lower costs. Meanwhile, TSMC continues to expand its Taiwan operations, with plans to build new 2 nm facilities in Kaohsiung's Science Park starting next year.

Fujitsu has previewed its next-generation Monaka processor, a 144-core powerhouse for data center. Satoshi Matsuoka of the RIKEN Center for Computational Science showcased the mechanical sample on social media platform X. The Monaka processor is developed in collaboration with Broadcom and employs an innovative 3.5D eXtreme Dimension System-in-Package architecture featuring four 36-core chiplets manufactured using TSMC's N2 process. These chiplets are stacked face-to-face with SRAM tiles through hybrid copper bonding, utilizing TSMC's N5 process for the cache layer. A distinguishing feature of the Monaka design is its approach to memory architecture. Rather than incorporating HBM, Fujitsu has opted for pure cache dies below compute logic in combination with DDR5 DRAM compatibility, potentially leveraging advanced modules like MR-DIMM and MCR-DIMM.

The processor's I/O die supports cutting-edge interfaces, including DDR5 memory, PCIe 6.0, and CXL 3.0 for seamless integration with modern data center infrastructure. Security in the design is taken care of with the implementation of Armv9-A's Confidential Computing Architecture for enhanced workload isolation. Fujitsu has set ambitious goals for the Monaka processor. The company aims to achieve twice the energy efficiency of current x86 processors by 2027 while maintaining air cooling capabilities. The processor aims to do AI and HPC with the Arm SVE 2 support, which enables vector lengths up to 2048 bits. Scheduled for release during Fujitsu's fiscal year 2027 (April 2026 to March 2027), the Monaka processor is shaping up as a competitor to AMD's EPYC and Intel's Xeon processors.

TSMC (TWSE: 2330, NYSE: TSM) today announced its net revenue for November 2024: On a consolidated basis, revenue for November 2024 was approximately NT$276.06 billion, a decrease of 12.2 percent from October 2024 and an increase of 34.0 percent from November 2023. Revenue for January through November 2024 totaled NT$2,616.15 billion, an increase of 31.8 percent compared to the same period in 2023.

TSMC is reportedly negotiating with NVIDIA to manufacture advanced "Blackwell" GPUs in its Arizona facility. First reported by Reuters, this partnership could mark another major shift in AI chip production toward US soil. The discussion centers around TSMC's Fab 21 in Phoenix, Arizona, specializing in 4 nm and 5 nm chip production. NVIDIA's Blackwell GPUs utilize TSMC's 4NP process technology, making the Arizona facility a technically viable production site. However, the proposed arrangement faces several logistical challenges. A key issue is the absence of advanced packaging facilities in the United States. There is Amkor that planned to do advanced packaging, but it's only scheduled to begin packaging in 2027. TSMC's sophisticated CoWoS packaging technology is currently available only in Taiwan. This means that chips manufactured in Arizona would need to be shipped back to Taiwan for final assembly, potentially increasing production costs.

While alternative solutions exist, such as redesigning the chips to use Intel's packaging technology or focusing on gaming GPU production in Arizona, these options present their own complications. Intel's packaging methods would likely increase costs, and the current absence of graphics card manufacturing infrastructure in the US makes domestic gaming GPU production less practical. Both TSMC and NVIDIA have declined to comment on the ongoing negotiations, as this is confidential information unknown to the public. Interestingly, TSMC's Arizona facility has already attracted a few more US firms for domestic manufacturing, like Apple, rumored to manufacture its A16 Bionic chip and AMD with high-performance designs, likely either EPYC or Instinct MI chips.

Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU.

The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.

In case you're wondering why Intel went with TSMC 3 nm to build the Compute tile of its "Arrow Lake" processor, and the SoC tile of "Lunar Lake," instead of Intel 3, or even Intel 20A, perhaps there's more to the recent story about Broadcom voicing its disappointment in the Intel 18A foundry node. The September 2024 report didn't specify a number to what yields on the Intel 18A node looked like to spook Broadcom, but we now have some idea as to just how bad things are. Korean publication Chosun, which tracks developments in the electronics and ICT industries, reports that yields on the Intel 18A foundry node stand at an abysmal 10%, making it unfit for mass-production. Broadcom validated Intel 18A as it was prospecting a cutting-edge node for its high-bandwidth network processors.

The report also hints that Intel's in-house foundry nodes going off the rails could be an important event leading up to the company's Board letting go of former CEO Pat Gelsinger, as huge 2nd order effects will be felt across the company's entire product stack in development. For example, company roadmaps put the company's next-generation "Clearwater Forest" server processor, slated for 2025, as being designed for the Intel 18A node. Unless Intel Foundry can pull a miracle, an effort must be underway to redesign the chip for whichever TSMC node is considered cutting-edge in 2025.

SK Hynix plans to produce its 6th generation high-bandwidth memory chips (HBM4) using TSMC's 3 nm process, a change from initial plans to use the 5 nm technology. The Korea Economic Daily reports that these chips will be delivered to NVIDIA in the second half of 2025. NVIDIA's GPU products are currently based on 4 nm HBM chips. The HBM4 prototype chip launched in March by SK Hynix features vertical stacking on a 3 nm die., compared to a 5 nm base die, the new 3 nm-based HBM chip is expected to offer a 20-30% performance improvement. However, SK Hynix's general-purpose HBM4 and HBM4E chips will continue to use the 12 nm process in collaboration with TSMC.

While SK Hynix's fifth-generation HBM3E chips used its own base die technology, the company has chosen TSMC's 3 nm technology for HBM4. This decision is anticipated to significantly widen the performance gap with competitor Samsung Electronics, which plans to manufacture its HBM4 chips using the 4 nm process. SK hynix is currently leading the global HBM market with almost 50% of market share, most of its HBM products been delivered to NVIDIA.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

Taiwanese political officials have agreed to discuss transferring TSMC's advanced 2 nm chip technology to allied democratic nations, but only after establishing the main mass production launch in late 2025 in Taiwan. This new stance comes amid growing international pressure and recent comments from upcoming US president Donald Trump about semiconductor manufacturing. The announcement by National Science and Technology Council Minister Cheng-Wen Wu marks a notable departure from earlier statements by Economic Affairs Minister J.W. Kuo, who had previously emphasized legal restrictions on transferring leading-edge process technology overseas. Interestingly, these different positions aren't so different from one point: timeline of node deployments. As TSMC produces latest nodes in Taiwan, overseas production will lag by a generation or two.

TSMC plans to implement its 2 nm technology in US facilities by 2030. The company's Arizona facility, Fab 21, will begin with less advanced N4 and N5 processes in early 2025 and progress to 3 nm technology by 2028. However, this timeline could face pressure for acceleration, mainly if new trade policies are implemented. Industry analyst Dan Nystedt points out significant challenges in transferring advanced chip production. Integrating research and development with manufacturing processes in Taiwan provides crucial advantages for initial production ramps, making simultaneous mass production launches in multiple locations technically challenging. Simply put, there aren't enough capable engineers, scientists, and factory workers capable of doing what TSMC accomplishes in Taiwan.

Germany is set to invest €2 billion in the semiconductor industry after recent setbacks, according to TrendForce via Liberty Times citing Bloomberg. The German government's new funding is in response to the chip sector's problems, including Intel's delay of the Magdeburg factory and global disruptions in the semiconductor supply chain. The investment will support 10 to 15 projects from wafer production to microchip assembly to strengthen Germany's and Europe's microelectronics ecosystem. This is in line with the European Chips Act which aims to increase the EU's global production capacity to 20% by 2030.

Intel's €30 billion Magdeburg factory delay and other cancelled chip projects from Wolfspeed and ZF Friedrichshafen AG have created uncertainty in the German market. The Ministry of Economic Affairs is now calling for new applications for funding, with up to €3 billion available. The timing of the semiconductor investment follows the global supply chain disruptions caused by the pandemic and the increasing geopolitical tensions between the US, China and Taiwan. Germany is following a broader trend of governments investing in local semiconductor production to increase technological independence and economic resilience. The funding is subject to budget reallocation with the new government after February 2025 elections. In the first round of subsidies from the European Chips Act, Germany allocated resources to two key initiatives: Intel's investment and a collaborative project between Infineon and TSMC in Dresden.