TSMC's new semiconductor manufacturing facility in Phoenix, Arizona, will face production costs approximately 30% higher than its Taiwan-based operations when it begins mass production in early 2025. The increased expenses stem from higher tariffs and transportation costs associated with importing necessary materials from Taiwan. The Arizona facility will start producing 10,000 12-inch wafers monthly using a 4 nm node, with plans to double output to 20,000 wafers at full capacity. Four major technology companies—Apple, NVIDIA, AMD, and Qualcomm—have committed to purchasing chips from the plant for their AI and high-performance computing needs. The 445-hectare facility highlights ongoing challenges in America's semiconductor industry. Despite the aim to strengthen domestic chip manufacturing, the plant must import materials from Taiwan to maintain production quality, revealing gaps in the US semiconductor supply chain.

This overseas dependency drives up operational costs significantly. While TSMC's investment marks an essential step in rebuilding domestic capacity, the substantial cost difference between US and Taiwanese production raises questions about long-term viability. TSMC has already begun trial production at the site and plans to expand operations with additional phases. The company's Phase 2 facility is completed, and equipment is being installed, while future expansions aim to produce 2 nm chips by 2028. However, unless the cost gap narrows, the higher production expenses could impact the plant's competitiveness in the global semiconductor market, even competing with its own Taiwanese facilities, where customers could decide to use Taiwanese fabs due to lower costs. Meanwhile, TSMC continues to expand its Taiwan operations, with plans to build new 2 nm facilities in Kaohsiung's Science Park starting next year.

Fujitsu has previewed its next-generation Monaka processor, a 144-core powerhouse for data center. Satoshi Matsuoka of the RIKEN Center for Computational Science showcased the mechanical sample on social media platform X. The Monaka processor is developed in collaboration with Broadcom and employs an innovative 3.5D eXtreme Dimension System-in-Package architecture featuring four 36-core chiplets manufactured using TSMC's N2 process. These chiplets are stacked face-to-face with SRAM tiles through hybrid copper bonding, utilizing TSMC's N5 process for the cache layer. A distinguishing feature of the Monaka design is its approach to memory architecture. Rather than incorporating HBM, Fujitsu has opted for pure cache dies below compute logic in combination with DDR5 DRAM compatibility, potentially leveraging advanced modules like MR-DIMM and MCR-DIMM.

The processor's I/O die supports cutting-edge interfaces, including DDR5 memory, PCIe 6.0, and CXL 3.0 for seamless integration with modern data center infrastructure. Security in the design is taken care of with the implementation of Armv9-A's Confidential Computing Architecture for enhanced workload isolation. Fujitsu has set ambitious goals for the Monaka processor. The company aims to achieve twice the energy efficiency of current x86 processors by 2027 while maintaining air cooling capabilities. The processor aims to do AI and HPC with the Arm SVE 2 support, which enables vector lengths up to 2048 bits. Scheduled for release during Fujitsu's fiscal year 2027 (April 2026 to March 2027), the Monaka processor is shaping up as a competitor to AMD's EPYC and Intel's Xeon processors.

TSMC (TWSE: 2330, NYSE: TSM) today announced its net revenue for November 2024: On a consolidated basis, revenue for November 2024 was approximately NT$276.06 billion, a decrease of 12.2 percent from October 2024 and an increase of 34.0 percent from November 2023. Revenue for January through November 2024 totaled NT$2,616.15 billion, an increase of 31.8 percent compared to the same period in 2023.

TSMC is reportedly negotiating with NVIDIA to manufacture advanced "Blackwell" GPUs in its Arizona facility. First reported by Reuters, this partnership could mark another major shift in AI chip production toward US soil. The discussion centers around TSMC's Fab 21 in Phoenix, Arizona, specializing in 4 nm and 5 nm chip production. NVIDIA's Blackwell GPUs utilize TSMC's 4NP process technology, making the Arizona facility a technically viable production site. However, the proposed arrangement faces several logistical challenges. A key issue is the absence of advanced packaging facilities in the United States. There is Amkor that planned to do advanced packaging, but it's only scheduled to begin packaging in 2027. TSMC's sophisticated CoWoS packaging technology is currently available only in Taiwan. This means that chips manufactured in Arizona would need to be shipped back to Taiwan for final assembly, potentially increasing production costs.

While alternative solutions exist, such as redesigning the chips to use Intel's packaging technology or focusing on gaming GPU production in Arizona, these options present their own complications. Intel's packaging methods would likely increase costs, and the current absence of graphics card manufacturing infrastructure in the US makes domestic gaming GPU production less practical. Both TSMC and NVIDIA have declined to comment on the ongoing negotiations, as this is confidential information unknown to the public. Interestingly, TSMC's Arizona facility has already attracted a few more US firms for domestic manufacturing, like Apple, rumored to manufacture its A16 Bionic chip and AMD with high-performance designs, likely either EPYC or Instinct MI chips.

Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU.

The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.

In case you're wondering why Intel went with TSMC 3 nm to build the Compute tile of its "Arrow Lake" processor, and the SoC tile of "Lunar Lake," instead of Intel 3, or even Intel 20A, perhaps there's more to the recent story about Broadcom voicing its disappointment in the Intel 18A foundry node. The September 2024 report didn't specify a number to what yields on the Intel 18A node looked like to spook Broadcom, but we now have some idea as to just how bad things are. Korean publication Chosun, which tracks developments in the electronics and ICT industries, reports that yields on the Intel 18A foundry node stand at an abysmal 10%, making it unfit for mass-production. Broadcom validated Intel 18A as it was prospecting a cutting-edge node for its high-bandwidth network processors.

The report also hints that Intel's in-house foundry nodes going off the rails could be an important event leading up to the company's Board letting go of former CEO Pat Gelsinger, as huge 2nd order effects will be felt across the company's entire product stack in development. For example, company roadmaps put the company's next-generation "Clearwater Forest" server processor, slated for 2025, as being designed for the Intel 18A node. Unless Intel Foundry can pull a miracle, an effort must be underway to redesign the chip for whichever TSMC node is considered cutting-edge in 2025.

SK Hynix plans to produce its 6th generation high-bandwidth memory chips (HBM4) using TSMC's 3 nm process, a change from initial plans to use the 5 nm technology. The Korea Economic Daily reports that these chips will be delivered to NVIDIA in the second half of 2025. NVIDIA's GPU products are currently based on 4 nm HBM chips. The HBM4 prototype chip launched in March by SK Hynix features vertical stacking on a 3 nm die., compared to a 5 nm base die, the new 3 nm-based HBM chip is expected to offer a 20-30% performance improvement. However, SK Hynix's general-purpose HBM4 and HBM4E chips will continue to use the 12 nm process in collaboration with TSMC.

While SK Hynix's fifth-generation HBM3E chips used its own base die technology, the company has chosen TSMC's 3 nm technology for HBM4. This decision is anticipated to significantly widen the performance gap with competitor Samsung Electronics, which plans to manufacture its HBM4 chips using the 4 nm process. SK hynix is currently leading the global HBM market with almost 50% of market share, most of its HBM products been delivered to NVIDIA.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

Taiwanese political officials have agreed to discuss transferring TSMC's advanced 2 nm chip technology to allied democratic nations, but only after establishing the main mass production launch in late 2025 in Taiwan. This new stance comes amid growing international pressure and recent comments from upcoming US president Donald Trump about semiconductor manufacturing. The announcement by National Science and Technology Council Minister Cheng-Wen Wu marks a notable departure from earlier statements by Economic Affairs Minister J.W. Kuo, who had previously emphasized legal restrictions on transferring leading-edge process technology overseas. Interestingly, these different positions aren't so different from one point: timeline of node deployments. As TSMC produces latest nodes in Taiwan, overseas production will lag by a generation or two.

TSMC plans to implement its 2 nm technology in US facilities by 2030. The company's Arizona facility, Fab 21, will begin with less advanced N4 and N5 processes in early 2025 and progress to 3 nm technology by 2028. However, this timeline could face pressure for acceleration, mainly if new trade policies are implemented. Industry analyst Dan Nystedt points out significant challenges in transferring advanced chip production. Integrating research and development with manufacturing processes in Taiwan provides crucial advantages for initial production ramps, making simultaneous mass production launches in multiple locations technically challenging. Simply put, there aren't enough capable engineers, scientists, and factory workers capable of doing what TSMC accomplishes in Taiwan.

Germany is set to invest €2 billion in the semiconductor industry after recent setbacks, according to TrendForce via Liberty Times citing Bloomberg. The German government's new funding is in response to the chip sector's problems, including Intel's delay of the Magdeburg factory and global disruptions in the semiconductor supply chain. The investment will support 10 to 15 projects from wafer production to microchip assembly to strengthen Germany's and Europe's microelectronics ecosystem. This is in line with the European Chips Act which aims to increase the EU's global production capacity to 20% by 2030.

Intel's €30 billion Magdeburg factory delay and other cancelled chip projects from Wolfspeed and ZF Friedrichshafen AG have created uncertainty in the German market. The Ministry of Economic Affairs is now calling for new applications for funding, with up to €3 billion available. The timing of the semiconductor investment follows the global supply chain disruptions caused by the pandemic and the increasing geopolitical tensions between the US, China and Taiwan. Germany is following a broader trend of governments investing in local semiconductor production to increase technological independence and economic resilience. The funding is subject to budget reallocation with the new government after February 2025 elections. In the first round of subsidies from the European Chips Act, Germany allocated resources to two key initiatives: Intel's investment and a collaborative project between Infineon and TSMC in Dresden.

Apple is reportedly considering diversifying its chip manufacturing strategy with a new silicon manufacturer: Intel. While the upcoming iPhone 17 series, expected next year, will likely feature A19 chips produced by TSMC, a recent rumor from Chinese leaker Fixed Focus Digital hints at a potential switch to Intel for the A20 chipsets powering the 2026 iPhone 18 series. The A18 and A18 Pro chipsets debuted alongside the iPhone 16 series in September 2024, manufactured using TSMC's N3E node. Apple's A19 chips are expected to upgrade to TSMC's N3P node. According to the source, Apple is seeking an Intel 20A node. However, since the A20 node is canceled in favor of 18A, Apple could be an Intel Foundry customer for either 18A or 14A nodes.

Despite the buzz, skepticism persists. Intel has historically struggled with process node transitions and even outsourced production of its Arrow Lake CPUs to TSMC, raising questions about its readiness to deliver on Apple's demands. On the other hand, alternative reports suggest Apple might stick with TSMC's yet-unnamed 2 nm node for the A20, maintaining continuity in its supply chain. As the iPhone 18 series remains two years away, much can change. For now, we are left speculating whether this rumored collaboration with Intel represents a new chapter in Apple's chipset innovation or just a rumor with little substance. If the US government mandates more domestic production, chip designers could be looking at some of the more local manufacturing options, like Intel does on US soil. That could force Apple, NVIDIA, AMD, and Qualcomm to look into Intel's offerings.

The EUV lithography machine from ASML ordered by Rapidus is expected to arrive in Japan in mid-December, according to information from Nikkei cited by TrendForce. This marks the first deployment of EUV technology in Japan, an important step for the country's semiconductor industry as it seeks to establish itself as a major player. Rapidus is currently building a factory in Chitose, Hokkaido, and plans to start mass production of 2 nm chips in 2027. The company also plans to purchase several EUV devices if the 2-nanometer chip production is successful, and intends to build a second production facility specifically for 1.4 nm chips. To support these operations, ASML will establish a service center in Chitose City.

NVIDIA CEO Jensen Huang hinted at the possibility of outsourcing AI chip production to Rapidus. As of October, construction progress on the Rapidus facility, which began in September 2023, is up to 63% and remains on track. In addition to Rapidus, Micron's Hiroshima plant is scheduled to install EUV equipment in 2025, allowing for mass production in 2026. JASM, a TSMC subsidiary in Japan, plans to integrate EUV lithography with a second wafer plant in 2027 that will have a 6 nm production line.

TSMC has reportedly postponed the opening ceremony of its Arizona Fab 21 facility, initially planned for December 6, amidst the changing US political landscape. The ceremony is now expected to take place after President-elect Donald Trump's inauguration in early 2025, showing that the chipmaker is taking a cautious approach to geopolitical shifts. The delay comes as TSMC finds itself at the intersection of global semiconductor politics. The company has invested heavily in its Arizona operations (estimated at $65 billion total), with Wang Yinglang, deputy general manager of wafer factory operations, leading the project. Despite initial skepticism, Wang's team has maintained an ambitious timeline, with mass production scheduled to begin in the first half of 2025.

Rumors also suggest that TSMC's decision stems from broader concerns about the incoming administration's semiconductor policies. However, TSMC maintains a strong position due to its unmatched technological capabilities, particularly in advanced manufacturing processes, which competitors like Intel and Samsung struggled to achieve. The Arizona facility represents a crucial piece of TSMC's global expansion strategy, which includes new factories in Japan and Germany. While the company faces challenges, including labor issues and rising costs in the US, its strategic importance to the global semiconductor supply chain remains unchanged. The only thing that is changing is the timeline of the opening ceremony, while high-volume production stays on track.

According to Taiwanese media Commercial Times, Intel is significantly increasing its outsourcing of "Arrow Lake" CPU production to TSMC, a strategic move as it grapples with persistent issues in its own foundry division. This decision to outsource a substantial portion of Arrow Lake's production is a significant shift in Intel's strategy, showing the company's rising reliance on external partners to meet quality and performance demands. The Arrow Lake Core Ultra 200 series is Intel's first major outsourcing initiative, in which Intel gave its core IP to third-party foundries, more specifically for a 3 nm node at TSMC. However, it clearly indicates the performance gaps in Intel's own Intel Foundry and the high demand expectations for the new CPUs. Originally intended to use Intel 20A node, Intel shifted focus of 18A node for its products and upcoming foundry customers.

Intel's recent orders with TSMC extend to its upcoming Lunar Lake chips and next-generation Falcon Shores AI GPUs, both of which will use TSMC's 3 nm process. Although Intel's 18A node remains promising, the company relies on current products to sustain its revenue streams, making TSMC's support crucial in ensuring timely shipments. This increased outsourcing reflects Intel's need to maintain competitive performance in the short term. Once its Foundry division meets performance and capacity targets, Intel aims to bring more CPU manufacturing back in-house. However, if anything goes wrong, Intel could face challenges securing sufficient volume from TSMC, as the foundry has longstanding commitments with major clients like Apple, NVIDIA, Qualcomm, and AMD.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Even with billions of US dollars being invested overseas, TSMC cannot legally manufacture its most advanced nodes outside of Taiwan. According to Taiwan's Minister of Economic Affairs J.W. Kuo, "Since Taiwan has regulations to protect its own technologies, TSMC cannot produce 2-nanometer chips overseas currently." He added, "Although TSMC plans to make 2-nanometer chips [abroad] in the future, its core technology will stay in Taiwan." This provides crucial insight into TSMC's strategic positioning, both in its US expansion plans and in navigating global geopolitical waters, especially with Taiwan being the major hub of silicon innovation. Taiwan's semiconductor industry follows strict regulations regarding overseas production capabilities, requiring companies to maintain their most advanced manufacturing processes within Taiwan.

The company's international expansion strategy includes significant developments in the United States. TSMC's Arizona facilities are central to these plans, with multiple fabs in different stages of development. The initial Arizona facility will begin producing 4 nm chips imminently, while a second facility, scheduled to open in 2028, will manufacture then mature 3 nm and 2 nm chips. A third planned facility aims to produce 2 nm or more sophisticated chips. Meanwhile, Taiwan-based facilities will produce more advanced chips at the same time, with volume production of A-16 chips planned for late 2026, following the rollout of 2 nm chip production in 2025. Furthermore, Taiwan-US semiconductor cooperation will continue regardless of political changes. Taiwan Semiconductor Industry Association (TSIA) Chairman and TSMC Senior Vice President Cliff Hou noted that historical evidence suggests US electoral outcomes have not significantly impacted this technological partnership, though some adjustments may occur.

AMD Ryzen AI MAX 300-series processors, codenamed "Strix Halo," have been on in the news for close to a year now. These mobile processors combine "Zen 5" CPU cores with an oversized iGPU that offers performance rivaling discrete GPUs, with the idea behind these chips being to rival the Apple M3 Pro and M3 Max processors powering MacBook Pros. The "Strix Halo" mobile processor is an MCM that combines one or two "Zen 5" CCDs (some ones featured on "Granite Ridge" desktop processors and "Turin" server processors), with a large SoC die. This die is built either on the 5 nm (TSMC N5) or 4 nm (TSMC N4P) node. It packs a large iGPU based on the RDNA 3.5 graphics architecture, with 40 compute units (CU), and a 50 TOPS-class XDNA 2 NPU carried over from "Strix Point." The memory interface is a 256-bit wide LPDDR5X-8000 for sufficient memory bandwidth for the up to 16 "Zen 5" CPU cores, the 50 TOPS NPU, and the large 40 CU iGPU.

Golden Pig Upgrade leaked what looks like a company slide from a notebook OEM, which reveals the iGPU model names for the various Ryzen AI MAX 300-series SKUs. Leading the pack is the Ryzen AI MAX+ 395. This is a maxed out SKU with a 16-core/32-thread "Zen 5" CPU that uses two CCDs. All 16 cores are full-sized "Zen 5." The CPU has 64 MB of L3 cache (32 MB per CCD), each of the 16 cores has 1 MB of dedicated L2 cache. The iGPU is branded Radeon 8060S, it comes with all 40 CU (2,560 stream processors) enabled, besides 80 AI accelerators, and 40 Ray accelerators. The Ryzen AI MAX 390 is the next processor SKU, it comes with a 12-core/24-thread "Zen 5" CPU. Like the 395, the 390 is a dual-CCD processor, all 12 cores are full-sized "Zen 5." There's 64 MB of L3 cache, and 1 MB of L2 cache per core. The Radeon 8060S graphics solution is the same as the one on the Ryzen AI MAX+ 395, it comes with all 40 CU enabled.

M31 Technology Corporation, a leading global provider of silicon intellectual property (IP), today announced that its cutting-edge USB4 IP has achieved silicon validation on TSMC's 5 nm (N5) process. The newly validated IP enhances data transfer capabilities for a new wave of mobile and portable devices. The announcement coincides with M31's participation in TSMC's 2024 Open Innovation Platform (OIP) Ecosystem Forum in Taiwan. This milestone underscores the close collaboration between M31 and TSMC, reflecting M31's commitment to advancing high-performance IP solutions by leveraging TSMC's innovative platform to drive next-generation connectivity.

M31's USB4 IP is built on the latest USB4 specification and represents a major leap in the evolution of USB architecture. It supports multi-protocol tunneling, enabling simultaneous transmission of multiple data types—such as USB, DisplayPort, and PCIe—over a single connection. The USB4 IP achieves 40 Gbps data transfer rates, significantly enhancing bandwidth associated with previous USB standards. The IP is fully compatible with USB 3.2, USB 2.0, and Thunderbolt 3, ensuring seamless integration with existing and future devices.

According to a recent Reuters report, OpenAI is continuing with its moves in the custom silicon space, expanding beyond its reported talks with Broadcom to include a broader strategy involving multiple industry leaders. Broadcom is a fabless chip designer known for a wide range of silicon solutions spanning from networking, PCIe, SSD controllers, and PHYs all the way up to custom ASICs. The company behind ChatGPT is actively working with both Broadcom and TSMC to develop its first proprietary AI chip, specifically focused on inference operations. Getting a custom chip to do training runs is a bit more complex task, and OpenAI leaves that to its current partners until the company figures out all details. Even with an inference chip, the scale at which OpenAI works and serves its models makes financial sense for the company to develop custom solutions tailored to its infrastructure needs.

This time, the initiative represents a more concrete and nuanced approach than previously understood. Rather than just exploratory discussions, OpenAI has assembled a dedicated chip team of approximately 20 people, led by former Google TPU engineers Thomas Norrie and Richard Ho. The company has secured manufacturing capacity with TSMC, targeting a 2026 timeline for its first custom-designed chip. While Broadcom's involvement leverages its expertise in helping companies optimize chip designs for manufacturing and manage data movement between chips—crucial for AI systems running thousands of processors in parallel—OpenAI is simultaneously diversifying its compute strategy. This includes adding AMD's Instinct MI300X chips to its infrastructure alongside its existing NVIDIA deployments. Similarly, Meta has the same approach, where it now trains its models on NVIDIA GPUs and serves them to the public (inferencing) using AMD Instinct MI300X.

According to a recent Reuters report, TSMC has decided to cut off Chinese firm Sophgo following the discovery of TSMC-manufactured components in Huawei's advanced AI processor. The suspension came after technology research firm TechInsights identified a TSMC-manufactured chip within Huawei's Ascend 910B processor during a detailed analysis. This discovery raised significant concerns, as Huawei has been restricted from accessing such technology under US export controls since 2020. TSMC promptly notified US authorities upon learning of the situation and launched an internal investigation. While being sanctioned by the US, Huawei needed to use a proxy firm to get access to high-end silicon manufacturing to produce its Ascend accelerators.

Sophgo, which has ties to cryptocurrency mining equipment manufacturer Bitmain, strongly denies any business relationship with Huawei. The company states it has provided TSMC with a detailed investigation report asserting its compliance with all applicable laws, saying: "SOPHGO has never been engaged in any direct or indirect business relationship with Huawei. SOPHGO has been conducting business in strict compliance with applicable laws and regulations, including but not limited to all the applicable US national export control laws and regulations, and has never been in violation of any of such laws and regulations. SOPHGO has provided detailed investigation report to TSMC to prove that SOPHGO is not related to the Huawei investigation."

The American semiconductor landscape reached a significant milestone as TSMC's new Arizona manufacturing facility demonstrated remarkable production efficiency, exceeding its Taiwanese counterparts by 4% in yield rates. This achievement, revealed at a recent industry webinar by the company's US division chief, represents a major step forward in America's push to strengthen domestic chip manufacturing capabilities. Since initiating its 4 nm node production operations this spring, the Phoenix-based facility has demonstrated impressive technical proficiency, achieving production standards that match and surpass TSMC's established Taiwanese facilities. The project, backed by substantial federal support, including $11.6 billion in combined grants and loans plus significant tax incentives, aims to establish three cutting-edge manufacturing plants in Arizona.

The company's global leadership praised the facility's performance, noting its strategic importance in demonstrating TSMC's ability to maintain exceptional manufacturing standards across international locations. This success carries particular weight given the project's earlier hurdles, which included workforce challenges and timeline adjustments that shifted the entire production schedule by approximately one year. This development gains additional significance against industry-wide challenges, particularly as competitors like Intel and Samsung face operational and financial obstacles. The semiconductor giant's plans now extend to potential further expansion, with the Phoenix site capable of hosting up to six manufacturing facilities. Future growth prospects could be enhanced by proposed additional government initiatives supporting domestic chip production.

Details of what is claimed to be Google's upcoming Tensor G5 and G6 SoCs have popped up over on Notebookcheck.net and the site claims to have found the specs on a public platform, without going into any further details. Those that were betting on the Tensor G5—codenamed Laguna—delivering vastly improved performance over the Tensor G4, are likely to be disappointed, at least on the CPU side of things. As previous rumours have suggested, the chip is expected to be manufactured by TSMC, using its N3E process node, but the Tensor G5 will retain the single Arm Cortex-X4 core, although it will see a slight upgrade to five Cortex-A725 cores vs. the three Cortex-A720 cores of the Tensor G4. The G5 loses two Cortex-A520 cores in favour of the extra Cortex-A725 cores. The Cortex-X4 will also remain clocked at the same peak 3.1 GHz as that of the Tensor G4.

Interestingly it looks like Google will drop the Arm Mali GPU in favour of an Imagination Technologies DXT GPU, although the specs listed by Notebookcheck doesn't add up with any of the specs listed by Imagination Technologies. The G5 will continue to support 4x 16-bit LPDDR5 or LPDDR5X memory chips, but Google has added support for UFS 4.0 memory, something that's been a point of complaint for the Tensor G4. Other new additions is support for 10 Gbps USB 3.2 Gen 2 and PCI Express 4.0. Some improvements to the camera logic has also been made, with support for up to 200 Megapixel sensors or 108 Megapixels with zero shutter lag, but if Google will use such a camera or not is anyone's guess at this point in time.

Last time we reported on Samsung Foundry, the company publicly apologized for its setbacks in the memory and foundry divisions, especially as its 3 nm GAA FET node has failed to attract new customers. On the other hand, Intel has also been struggling with its Foundry unit bleeding billions of Dollars in a bid to secure its spot as one of the best foundries for companies to manufacture their chips. There is no better pair than two struggling foundries looking for customers and new ways to conduct research than Intel and Samsung. According to an exclusive by South Korean media outlet "MK," it has reportedly been confirmed that Intel approached Samsung to form a "Foundry Alliance" to boost their foundry business units.

According to the source, Intel CEO Pat Gelsinger is reportedly eager to meet with Samsung Electronics Chairman Lee Jae-yong face-to-face to discuss "comprehensive collaboration in the foundry sector." What exactly will happen between the two is still unclear. Back in 2014, GlobalFoundries and Samsung formed a partnership for 14 nm FinFET offerings, and that was a wide success. Jointly developing a node and offering it in their foundry units could be the target goal for Intel and Samsung. At some level, research and development, as well as sharing valuable manufacturing information on yield improvements, should be beneficial for both to put together the final pieces of the semiconductor puzzle.

At TSMC's earnings call on the 17th, the company revealed that its CoWoS (Chip-on-Wafer-on-Substrate) capacity will double each year in 2024 and 2025, but demand will continue to outpace supply. According to a report from Money DJ, the CoWoS expansion wave is expected to extend into 2026, promising strong growth for equipment suppliers for at least the next two to three years.

TSMC stated that advanced packaging currently accounts for approximately 7-9% of its revenue, and growth in this segment is expected to outpace the company's average over the next five years. While the gross margin for advanced packaging is slightly below the company average, it is steadily approaching it. Regarding CoWoS capacity, customer demand significantly exceeds TSMC's ability to supply, even with production capacity doubling year-on-year in both 2024 and 2025.

TSMC today announced consolidated revenue of NT$759.69 billion (US$23.50 billion), net income of NT$325.26 billion (US$10.08 billion), and diluted earnings per share of NT$12.54 (US$1.94 per ADR unit) for the third quarter ended September 30, 2024. Year-over-year, third quarter revenue increased 39.0% while net income and diluted EPS both increased 54.2%. Compared to second quarter 2024, third quarter results represented a 12.8% increase in revenue and a 31.2% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, third quarter revenue was $23.50 billion, which increased 36.0% year-over-year and increased 12.9% from the previous quarter. Gross margin for the quarter was 57.8%, operating margin was 47.5%, and net profit margin was 42.8%. In the third quarter, shipments of 3-nanometer accounted for 20% of total wafer revenue; 5-nanometer accounted for 32%; 7-nanometer accounted for 17%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 69% of total wafer revenue.