Tuesday, April 1st 2025
TSMC Reportedly Preparing New Equipment for 1.4 nm Trial Run at "P2" Baoshan Plant
Industry insiders posit that TSMC's two flagship fabrication facilities are running ahead of schedule with the development of an advanced 2 nm (N2) process node. A cross-facility mass production phase is tipped to begin later this year, which leaves room for next-level experiments. Taiwan's Economic Daily News has heard supply chain whispers about the Baoshan "P2" plant making internal preparations for a truly cutting edge 1.4 nm-class product. According to the report, unnamed sources have claimed that: "TSMC has made a major breakthrough in the advancement of its 1.4 nm process. (The company) has recently notified suppliers to prepare the necessary equipment for 1.4 nm, and plans to install a trial production 'mini-line' at P2 (Baoshan Fab 20)."
Their Hsinchu-adjacent "Fab 20" site is touted as a leading player in the prototyping of this new technology. Industry moles reckon that "1.4 nm expertise" will eventually trickle over to nearby "P3 and P4 plants" for full production phases. Allegedly, these factories were originally going to be involved in the manufacturing of 2 nm (N2) wafers. Additionally, TSMC's "Fab 25" campus could potentially play host to trial 1.4 nm activities—the Economic Daily News article proposes that four plants based in the Central Taiwan Science Park are pitching in with collaborative work. As interpreted by TrendForce, "P1" could begin "risk trial production" by 2027, followed by full-scale output within the following year.
Sources:
Economic Daily News TW, TrendForce
Their Hsinchu-adjacent "Fab 20" site is touted as a leading player in the prototyping of this new technology. Industry moles reckon that "1.4 nm expertise" will eventually trickle over to nearby "P3 and P4 plants" for full production phases. Allegedly, these factories were originally going to be involved in the manufacturing of 2 nm (N2) wafers. Additionally, TSMC's "Fab 25" campus could potentially play host to trial 1.4 nm activities—the Economic Daily News article proposes that four plants based in the Central Taiwan Science Park are pitching in with collaborative work. As interpreted by TrendForce, "P1" could begin "risk trial production" by 2027, followed by full-scale output within the following year.
24 Comments on TSMC Reportedly Preparing New Equipment for 1.4 nm Trial Run at "P2" Baoshan Plant
"Analysts at TechInsights believe that TSMC's N2 offers a high-density (HD) standard-cell transistor density of 313 MTr/mm^2, which far exceeds the HD cell density of Intel's 18A (238 MTr/mm^2) and Samsung's SF2/SF3P (231 MTr/mm^2)."
gimme sub-sub nm or gimme death :roll:
You go, TSMC !
And to further put a damper on things, the per-wafer cost will rise 10% and design costs by even more, so the price-performance delta on N2 is going to be razor thin.
wccftech.com/tsmc-details-its-high-end-2nm-process-revealing-performance-efficiency-improvements/
Edit:
Searched for where your quote is from and I do not seem to be far from what TechInsights said in more detail:
www.pazimbabwe.com/intel-vs-tsmc-process-nodes-battle-speed-or-density-which-wins
Is not like someone would check on them or call the scam....
Nope, in this statement, TSMC compared it to N3E with all its density optimizations in place, using ARM test chips designed for density rather than frequency. Meanwhile, even mobile chips prioritized clock speed over density, creating the misleading impression that the gains weren’t significant.
However, when we examine the specs, SRAM in N2 is 20% denser than in N3E. That alone already gives it an advantage over Intel’s A18, which has specs comparable to N3E. Don't forget that logic always shrinks much more than SRAM.
SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements | Tom's Hardware
IEDM 2022 – TSMC 3nm - SemiWiki
Chiplet is the canonical implementation of the idea of using multiple nodes as they fit (plus the size/yield considerations) where each piece is produced on most suitable (or in reality, cheapest) process and later connected together.
The more interesting approach that seems to be taking hold is using the same process but different libraries on the same die. Basically building the parts you need to be fast with HP transistors and have the rest on HD with the density it provides. TSMC has offered it since N5 I believe and it does get used on N3. Others are at least capable of it as well.
And stop the off-colored comments.