Today at the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled new breakthroughs to help drive the semiconductor industry forward into the next decade and beyond. Intel Foundry showcased new material advancements that help improve interconnections within a chip, resulting in up to 25% capacitance by using subtractive ruthenium. Intel Foundry also was first to report a 100x throughput improvement using a heterogeneous integration solution for advanced packaging to enable ultra-fast chip-to-chip assembly. And to further drive gate-all-around (GAA) scaling, Intel Foundry demonstrated work with silicon RibbonFET CMOS and with gate oxide module for scaled 2D FETs for improved device performance.

"Intel Foundry continues to help define and shape the roadmap for the semiconductor industry. Our latest breakthroughs underscore the company's commitment to delivering cutting-edge technology developed in the U.S., positioning us well to help balance the global supply chain and restore domestic manufacturing and technology leadership with the support of the U.S. CHIPS Act," says Sanjay Natarajan, Intel senior vice president and general manager of Intel Foundry Technology Research.

Broadcom Inc. today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs). The 3.5D XDSiP integrates more than 6000 mm² of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power computing for AI at scale. Broadcom has achieved a significant milestone by developing and launching the industry's first Face-to-Face (F2F) 3.5D XPU.

The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPUs. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost. Traditional methods like Moore's Law and process scaling are struggling to keep up with these demands. Therefore, advanced system-in-package (SiP) integration is becoming crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm² of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as new and increasingly complex LLMs are introduced, their training necessitates 3D silicon stacking for better size, power, and cost. Consequently, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.

Infineon Technologies AG, a global leader in semiconductor solutions, and Quantinuum, a global leader in integrated, full-stack quantum computing, today announced a strategic partnership to develop the future generation of ion traps. This partnership will drive the acceleration of quantum computing and enable progress in fields such as generative chemistry, material science, and artificial intelligence.

"We are thrilled to partner with Quantinuum, a leader in quantum computing, to push the boundaries of quantum computing and generate larger, more powerful machines that solve meaningful real-life problems," said Richard Kuncic, Senior Vice President and General Manager Power Systems at Infineon Technologies. "This collaboration brings together Infineon's state-of-the-art knowledge in process development, fabrication, and quantum processing unit (QPU) technology with Quantinuum's cutting-edge ion-trap design expertise and experience with operating high-performance commercial quantum computers."

xMEMS Labs, developers of the foremost platform for piezoMEMS innovation and creators of the world's leading all-silicon micro speakers, today announced its latest industry-changing innovation: the xMEMS XMC-2400 µCooling chip, the first-ever all-silicon, active micro-cooling fan for ultramobile devices and next-generation artificial intelligence (AI) solutions.

For the first time, with active, fan-based micro-cooling (µCooling) at the chip level, manufacturers can integrate active cooling into smartphones, tablets, and other advanced mobile devices with the silent, vibration-free, solid-state xMEMS XMC-2400 µCooling chip, which measures just 1-millimeter thin.

Texas Instruments (TI) (Nasdaq: TXN) and the U.S. Department of Commerce have signed a non-binding Preliminary Memorandum of Terms for up to $1.6 billion in proposed direct funding under the CHIPS and Science Act to support three 300 mm wafer fabs already under construction in Texas and Utah. In addition, TI expects to receive an estimated $6 billion to $8 billion from the U.S. Department of Treasury's Investment Tax Credit for qualified U.S. manufacturing investments. The proposed direct funding, coupled with the investment tax credit, would help TI provide a geopolitically dependable supply of essential analog and embedded processing semiconductors.

"The historic CHIPS Act is enabling more semiconductor manufacturing capacity in the U.S., making the semiconductor ecosystem stronger and more resilient," said Haviv Ilan, president and CEO of Texas Instruments. "Our investments further strengthen our competitive advantage in manufacturing and technology as we expand our 300 mm manufacturing operations in the U.S. With plans to grow our internal manufacturing to more than 95% by 2030, we're building geopolitically dependable, 300 mm capacity at scale to provide the analog and embedded processing chips our customers will need for years to come."

Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, today announced the demonstration of high quality 300 mm-Si-based quantum dot spin qubit processing with devices resulting in a statistically relevant, average charge noise of 0.6µeV/√ Hz at 1 Hz. In view of noise performance, the values obtained are the lowest charge noise values achieved on a 300 mm fab-compatible platform.

Such low noise values enable high-fidelity qubit control, as reducing the noise is critical for maintaining quantum coherence and high fidelity control. By demonstrating those values, repeatedly and reproducibly, on a 300 mm Si MOS quantum dot process, this work makes large-scale quantum computers based on Si quantum dots a realistic possibility.

An Innovate UK project worth £1.1M has been awarded to the Lancaster University spinout firm Quinas, the global semiconductor company IQE and Lancaster and Cardiff Universities. Quinas will coordinate the ambitious project which is the first step towards volume production of the universal computer memory ULTRARAM invented by Lancaster Physics Professor Manus Hayne.

ULTRARAM has extraordinary properties, combining the non-volatility of a data storage memory, like flash, with the speed, energy-efficiency, and endurance of a working memory, like DRAM. Most of the funding for the one-year project will be spent at IQE which will scale up the manufacture of compound semiconductor layers from Lancaster University to an industrial process at the Cardiff based firm. This will involve IQE developing advanced capability for growth of the compound semiconductors gallium antimonide and aluminium antimonide for the first time. The project follows significant investment to boost the UK semiconductor industry and the establishment of the world's first compound semiconductor cluster in South Wales.

A recent report from Taiwan TV News has revealed that TSMC's overseas expansion plans will only contribute around 10% of the company's total silicon production capacity. TSMC's overseas expansion strategy has been a topic of significant interest in the tech industry as the company seeks to diversify its manufacturing capabilities beyond its home base in Taiwan. The company has announced plans to build new fabrication plants in the United States, Japan, and potentially other regions in an effort to mitigate supply chain risks and better serve its global customer base. However, according to the report, these overseas facilities will only account for a small fraction of 10% of TSMC's overall production capacity.

The majority of the company's manufacturing will continue to be centered in Taiwan, where it maintains its most advanced and high-volume fabs. There are also significant challenges and investments required to establish new semiconductor manufacturing facilities overseas. Building a state-of-the-art fab can cost billions of dollars and take several years to complete, making it a complex and capital-intensive undertaking. Despite the relatively small contribution of its overseas facilities, TSMC's global expansion is still seen as a crucial step in diversifying its supply chain and mitigating geopolitical risks. The company's ability to maintain its technological leadership and meet the growing demand for advanced chips will be crucial in the years to come.

Intel Corporation (Nasdaq: INTC) and Apollo (NYSE: APO) today announced a definitive agreement under which Apollo-managed funds and affiliates will lead an investment of $11 billion to acquire from Intel a 49% equity interest in a joint venture entity related to Intel's Fab 34. The transaction represents Intel's second Semiconductor Co-Investment Program (SCIP) arrangement. SCIP is an element of Intel's Smart Capital strategy, a funding approach designed to create financial flexibility to accelerate the company's strategy, including investing in its global manufacturing operations, while maintaining a strong balance sheet.

Located in Leixlip, Ireland, Fab 34 is Intel's leading-edge high-volume manufacturing (HVM) facility designed for wafers using the Intel 4 and Intel 3 process technologies. To date, Intel has invested $18.4 billion in Fab 34. This transaction allows Intel to unlock and redeploy to other parts of its business a portion of this investment while continuing the build-out of Fab 34. As part of its transformation strategy, Intel has committed billions of dollars of investments to regaining process leadership and building out leading-edge wafer fabrication and advanced packaging capacity globally.

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announces a new high-volume 200 mm silicon carbide ("SiC") manufacturing facility for power devices and modules, as well as test and packaging, to be built in Catania, Italy. Combined with the SiC substrate manufacturing facility being readied on the same site,these facilities will form ST's Silicon Carbide Campus, realizing the Company's vision of a fully vertically integrated manufacturing facility for the mass production of SiC on one site.The creation of the new Silicon Carbide Campus is a key milestone to support customers for SiC devices across automotive, industrial and cloud infrastructure applications, as they transition to electrification and seek higher efficiency.

"The fully integrated capabilities unlocked by the Silicon Carbide Campus in Catania will contribute significantly to ST's SiC technology leadership for automotive and industrial customers through the next decades," said Jean-Marc Chery, President and Chief Executive Officer of STMicroelectronics. "The scale and synergies offered by this project will enable us to better innovate with high-volume manufacturing capacity, to the benefit of our European and global customers as they transition to electrification and seek more energy efficient solutions to meet their decarbonization goals."

Beijing has doubled down on its push for semiconductor self-sufficiency with the establishment of a new $47.5 billion investment fund to accelerate growth in the domestic chip sector. The fund, officially registered on May 24th under the name "China Integrated Circuit Industry Investment Fund Phase III", represents the largest of three state-backed vehicles aimed at cultivating China's semiconductor capabilities. The announcement comes as tensions over advanced chip technology continue to escalate between the U.S. and China. Over the past couple years, Washington has steadily ratcheted up export controls on semiconductors to Beijing over national security concerns about potential military applications. These measures have lent new urgency to China's quest for self-sufficiency in chip design and manufacturing.

With a war chest of 344 billion yuan ($47.5 billion), the "Big Fund" dwarfs the combined capital of the first two semiconductor investment vehicles launched in 2014 and 2019. Officials have outlined a multipronged strategy targeting key bottlenecks, focusing on equipment for chip fabrication plants. The fund has bankrolled major projects such as flash memory maker Yangtze Memory Technologies and leading foundries like SMIC and Huahong. China's homegrown chip industry still needs to catch up to global leaders like Intel, Samsung, and TSMC. However, the immense scale of state-directed capital illustrates Beijing's unwavering commitment to developing a self-reliant supply chain for semiconductors—a technology viewed as indispensable for economic and military competitiveness. News of the "Big Fund" sent Chinese chip stocks surging over 3% on hopes of fresh financing tailwinds.

Toshiba Electronic Devices & Storage Corporation ("Toshiba") today held a ceremony to mark the completion of a new 300-millimeter wafer fabrication facility for power semiconductors and an office building at Kaga Toshiba Electronics Corporation in Ishikawa Prefecture, Japan, one of Toshiba's key group companies. The completion of construction is a major milestone for Phase 1 of Toshiba's multi-year investment program. Toshiba will now proceed with equipment installation, toward starting mass production in the second half of fiscal year 2024. Once Phase 1 reaches full-scale operation, Toshiba's production capacity for power semiconductors, mainly MOSFETs and IGBTs, will be 2.5 times that of fiscal 2021, when the investment plan was made. Decisions on the construction and start of operation of Phase 2 will reflect market trends.

The new manufacturing building follows and will make a major contribution to Toshiba's Business Continuity Plan (BCP): it has a seismic isolation structure that absorbs earthquake shock and redundant power sources. Energy from renewable source and solar panels on the roof of the building (onsite PPA model) will allow the facility to meet 100% of its power requirement with renewable energy.

As a part of its Q1 earnings call discussion, one of the largest semiconductor manufacturers, TSMC, has unveiled a strategic move to charge a premium for chips manufactured at its newly established overseas fabrication plants. During an earnings call, TSMC's CEO, C.C. Wei, announced that the company will impose higher pricing for chips produced outside Taiwan to offset the higher operational costs associated with these international locations. This move aims to maintain TSMC's target gross margin of 53% amidst rising expenses such as inflation and elevated electricity costs. This decision comes as TSMC expands its global footprint with new facilities in the United States, Germany, and Japan (JAMS) to meet the increasing demand for semiconductor chips worldwide. The company's new US-based Arizona facility, known as Fab 21, has faced delays due to equipment installation issues and labor negotiations.

Chips produced at this site, utilizing TSMC's advanced N5 and N4 nodes, could cost between 20% to 30% more than those manufactured in Taiwan. TSMC's strategy to manage the cost disparities across different geographic locations involves strategic pricing, securing government support, and leveraging its manufacturing technology leadership. This approach reflects the company's commitment to maintaining its competitive edge while navigating the complexities of global semiconductor manufacturing in today's fragmented market. Introducing a location premium is expected to impact American semiconductor designers, who may need to pass these costs on to specific market segments, particularly those with lower price sensitivity, such as government-related projects. Despite these challenges, TSMC's overseas expansion underscores its adaptive strategies in the face of global economic pressures and industry demands, ensuring its continued position as a leading player in the semiconductor industry.

SK hynix Inc., the world's leading producer of High-Bandwidth Memory (HBM) chips, announced today that it will invest an estimated $3.87 billion in West Lafayette, Indiana to build an advanced packaging fabrication and R&D facility for AI products. The project, the first of its kind in the United States, is expected to drive innovation in the nation's AI supply chain, while bringing more than a thousand new jobs to the region.

The company held an investment agreement ceremony with officials from Indiana State, Purdue University, and the U.S. government at Purdue University in West Lafayette on the 3rd and officially announced the plan. At the event, officials from each party including Governor of Indiana Eric Holcomb, Senator Todd Young, Director of the White House Office of Science and Technology Policy Arati Prabhakar, Assistant Secretary of Commerce Arun Venkataraman, Secretary of Commerce State of Indiana David Rosenberg, Purdue University President Mung Chiang, Chairman of Purdue Research Foundation Mitch Daniels, Mayor of city of West Lafayette Erin Easter, Ambassador of the Republic of Korea to the United States Hyundong Cho, Consul General of the Republic of Korea in Chicago Junghan Kim, SK vice chairman Jeong Joon Yu, SK hynix CEO Kwak Noh-Jung and SK hynix Head of Package & Test Choi Woojin, participated.

Construction of Intel's New Albany, Ohio fabrication site started back in late 2022—since then, a series of setbacks have caused anticipated timelines to slip. Team Blue's original plans included a 2025 opening ceremony—last month, this was amended to late 2026 or early 2027. New equipment deliveries have been affected by extreme weather conditions—Intel appears to be shoring up its flood prevention systems at their Licking County location. Ohio's Department of Development received a progress report at the start of this month, authored by Team Blue staffers—revised figures indicate that Fabrication sites 1 and 2 are expected to reach operational status somewhere within "2027-2028."

Jim Evers (Intel's Ohio Site Manager) stated: "we are making great progress growing the Silicon Heartland. In addition to the approximately $1.5 billion investment in completed spends through 12/31/23 referenced in the report, Intel has an additional $3 billion in contractually committed spends underway, totaling $4.5 billion committed toward our Ohio One projects." Intel committed a hefty $20 billion greenfield investment into the two Ohio wafer fab sites, but the latest progress report indicates that just under a quarter of that budget has trickled out of company coffers (so far). Evers's statement continued: "this investment is growing every day as we work to establish a new manufacturing campus to build leading-edge semiconductor chips right here in Ohio." A Tom's Hardware report reminds us about Team Blue's New Albany project receiving "over $2 billion in incentives." Industry rumors posit that the US government is readying a multi-billion dollar grant for Intel's Arizona facility.

Silicon Box, a cutting-edge, advanced panel-level packaging foundry announced its intention to collaborate with the Italian government to invest up to $3.6 billion (€3.2 billion) in Northern Italy, as the site of a new, state-of-the-art semiconductor assembly and test facility. This facility will help meet critical demand for advanced packaging capacity to enable next generation technologies that Silicon Box anticipates by 2028. The multi-year investment will replicate Silicon Box's flagship foundry in Singapore which has proven capability and capacity for the world's most advanced semiconductor packaging solutions, then expand further into 3D integration and testing. When completed, the new facility will support approximately 1,600 Silicon Box employees in Italy. The construction of the facility is also expected to create several thousand more jobs, including eventual hiring by suppliers. Design and planning for the facility will begin immediately, with construction to commence pending European Commission approval of planned financial support by the Italian State.

As well as bringing the most advanced chiplet integration, packaging, and testing to Italy, Silicon Box's manufacturing process is based on panel-level-production; a world leading, first-of-its-kind combination that is already shipping product to customers from its Singapore foundry. Through the investment, Silicon Box has plans for greater innovation and expansion in Europe, and globally. The new integrated production facility is expected to serve as a catalyst for broader ecosystem investments and innovation in Italy, as well as the rest of the European Union.

Lee Kang-Wook, Vice President of Research and Development at SK Hynix, has discussed the increased importance of advanced chip packaging with Bloomberg News. In an interview with the media company's business section, Lee referred to a tradition of prioritizing the design and fabrication of chips: "the first 50 years of the semiconductor industry has been about the front-end." He believes that the latter half of production processes will take precedence in the future: "...but the next 50 years is going to be all about the back-end." He outlined a "more than $1 billion" investment into South Korean facilities—his department is hoping to "improve the final steps" of chip manufacturing.

SK Hynix's Head of Packaging Development pioneered a novel method of packaging the third generation of high bandwidth technology (HBM2E)—that innovation secured NVIDIA as a high-profile and long term customer. Demand for Team Green's AI GPUs has boosted the significance of HBM technologies—Micron and Samsung are attempting to play catch up with new designs. South Korea's leading memory supplier is hoping to stay ahead in the next-gen HBM contest—supposedly 12-layer fifth generation samples have been submitted to NVIDIA for approval. SK Hynix's Vice President recently revealed that HBM production volumes for 2024 have sold out—currently company leadership is considering the next steps for market dominance in 2025. The majority of the firm's newly announced $1 billion budget will be spent on the advancement of MR-MUF and TSV technologies, according to their R&D chief.

Taiwan's Commercial Times has published coverage of a newly launched TSMC recruitment drive—proceedings kicked off last weekend with company representatives heading to the National Taiwan University campus. On the second of March, TSMC set up an outdoor booth on the grounds of Taipei's public research university—where the national comprehensive institute organized a Talent Recruitment Enterprise Expo. Unsurprisingly, TSMC recruiters are seeking potential "talents with high enthusiasm for semiconductors." Ctee's reporter found out that Taiwan's premier foundry is expecting to: "recruit approximately 6,000 new colleagues in Taiwan in 2024, including engineers and technicians." TSMC is reportedly responding to business growth and technology development demands—so much so, that its native manufacturing plants require a fresh influx of workers.

According to Ctee's report, TSMC's March recruitment tour is due to snake through Taiwan and then head over to mainland China: "Tsinghua University, National Cheng Kung University, National Yang-Ming Jiaotong University, Central China University, Zhongxing University, Zhongshan, National Chung Cheng University, Beijing University of Science and Technology, etc., totaling 19 physical activities and four online talent recruitment briefings." A parallel "2024 DNA Summer Internship Program" has also been rolled out: "inviting interested students to join and use internships to personally experience the environment and culture of TSMC." The company's growing global layout also provides opportunities for new employees to work overseas—the article highlights TSMC's newly opened semiconductor fabrication plant in Kumamoto Prefecture, Japan as the preferred choice for "internal employees." The multinational firm's Arizona facilities did not get a shout out, despite recent good news. Reports from mid-2023 suggest that TSMC's core values are at odds with North American work culture.

Morris Chang, TSMC's founder and semiconductor industry icon, was present at the opening ceremony of his company's new semiconductor fabrication plant in Kumamoto Prefecture, Japan. According to a Nikkei Asia article, Chang predicted that the nation will experience "a chip renaissance" during his February 24 commencement speech. The Japanese government also announced that it will supply an additional ¥732 billion ($4.86 billion) in subsidies for Taiwan Semiconductor Manufacturing Co. to expand semiconductor operations on the island of Kyūshū. Economy Minister Ken Saito stated: "TSMC is the most important partner for Japan in realizing digital transformation, and its Kumamoto factory is an important contributor for us to stably procure cutting-edge logic chips that is extremely essential for the future of industries in Japan."

Chang disclosed some interesting insights during last weekend's conference segment—according to Nikkei's report, he revealed that unnamed TSMC customers had made some outlandish requests: "They are not talking about tens of thousands of wafers. They are talking about fabs, (saying): 'We need so many fabs. We need three fabs, five fabs, 10 fabs.' Well, I can hardly believe that one." The Taiwanese chip manufacturing giant reportedly has the resources to create a new "Gigafab" within reasonable timeframes, but demands for (up to) ten new plants are extremely fanciful. Chang set expectations at a reasonable level—he predicted that demand for AI processors would lie somewhere in the middle ground: "between tens of thousands of wafers and tens of fabs." Past insider reports suggested that OpenAI has been discussing the formation of a proprietary fabrication network, with proposed investments of roughly $5 to $7 trillion. OpenAI CEO, Sam Altman, reportedly engaged in talks with notable contract chip manufacturers—The Wall Street Journal posited that TSMC would be an ideal partner.

TSMC Arizona's second semiconductor fabrication site has celebrated a "topping out" milestone—as documented in an official blog post (via LinkedIn) from yesterday. Workers were photographed installing an important/final piece of structure—the aforementioned "topping out" milestone signifies: "the last steel beam being raised into place on a construction project." The Taiwanese multinational semiconductor contract manufacturer has had a rough time in establishing operations out in the desert/greater Phoenix area—the "Fab 21 Phase 2" plant is not expected to meet its original 2026 opening window. TSMC Chairman Mark Liu is reportedly leaving his position due to consistent Arizona-related problems and delays.

The TSMC LinkedIn account shared some additional and certainly much-needed positive news: "We also recently achieved the topping milestone on our second fab's auxiliary buildings, which will supply the necessary utilities infrastructure to the second fab clean room." Thursday's blog (February 22) also discloses that the primary site—Fab 21 Phase 1—is still on track to begin production within the first half of 2025, thanks to "significant" bursts in construction progress. The author moved onto future production prospects: "Once operational, our two fabs at TSMC Arizona will manufacture the most advanced semiconductor technology in the U.S., creating 4,500 direct high-tech, high-wage jobs and enabling our customers' leadership in the high-performance computing and artificial intelligence era for decades."

Japan's Jiji news agency has cottoned onto a major computer memory industry rumble—a Friday Reuters report suggests that Kioxia has offered an olive branch to SK Hynix, perhaps in a renewed push to get its proposed (and once rejected) merger with Western Digital over the finishing line. The South Korean memory manufacturing juggernaut took great issue with the suggested formation of a mighty Japanese-American 3D NAND memory chip conglomerate—SK Hynix's opposition reportedly placed great pressure on Western Digital (WD), and discussions with Kioxia ended last October.

Kioxia is seemingly eager to resume talks with WD, but requires a thumbs up from SK Hynix—according to Jiji's insider source(s), the Tokyo-headquartered manufacturer is prepared to offer its South Korean rival a nice non-volatile memory production deal. Kioxia's best Japanese 3D NAND fabrication facilities could play host to SK Hynix designs, although it is too early to tell whether this bid has been accepted. The Yokkaichi and Kitakami plants are set to receive a 150 billion yen Government subsidy—Kioxia and WD's joint venture is expected to move into cutting-edge semiconductor production. The Japanese government is hoping to secure its native operations in times of industry flux.

According to a Bloomberg report, Intel is seeking to raise at least $2 billion in equity funding from investors for expanding its fabrication facility in Leixlip, Ireland, known as Fab 34. The chipmaker has hired an advisor to find potential investors interested in providing capital for the project. Fab 34 is currently Intel's only chip plant in Europe that uses cutting-edge extreme ultraviolet (EUV) lithography. It produces processors on the Intel 4 process node, including compute tiles for Meteor Lake client CPUs and expected future Xeon data center chips. While $2 billion alone cannot finance the construction of an entirely new fab today, it can support meaningful expansion or upgrades of existing capacity. Intel likely aims to grow Fab 34's output and/or transition it to more advanced 3 nm-class technologies like Intel 3, Intel 20A, or Intel 18A.

Expanding production aligns with Intel's needs for its own products and its Intel Foundry Services business, providing contract manufacturing. Intel previously secured a $15 billion investment from Brookfield Infrastructure for its Arizona fabs in exchange for a 49% stake, demonstrating the company's willingness to partner to raise capital for manufacturing projects. The Brookfield deal also set a precedent of using outside financing to supplement Intel's own spending budget. It provided $15 billion in effectively free cash flow Intel can redirect to other priorities like new fabs without increasing debt. Intel's latest fundraising efforts for the Ireland site follow a similar equity investment model that leverages outside capital to support its manufacturing expansion plans. Acquiring High-NA EUV machinery for manufacturing is costly, as these machines can reach up to $380 million alone.

Intel is aiming to get its $20 billion fabrication location—in New Albany, Ohio—up and running by 2025, but the advanced manufacturing facility is facing another round of setbacks. According to a WCMH NBC4 local news report (covering the Colombus, Ohio area), a planned "oversized equipment" reshuffle has been delayed—the shifting of heavy machinery was supposed to start last weekend. Extreme weather conditions (flooding) have been cited as major factor, as well as the complicated nature of transporting "overweight and oversized" loads to Team Blue's 1000-acre site. Workers are set to resume efforts this weekend—starting no later than February 17. Tom's Hardware has kept tabs on the Ohio fab's progress: "The project to move the equipment is expected to last over nine months, meaning this phase of Intel's construction could be done near the end of 2024. There isn't a firm indication of how much work remains to be done at the site after the equipment is delivered." TPU previously covered the leading-edge location's indefinitely postponed groundbreaking ceremony—CHIPS Act subsidies were not delivered in an expected timely manner back in 2022.

A couple of media outlets (Tom's Hardware, Network World, etc.) have received an official statement regarding the slippage of events in New Albany: "While we will not meet the aggressive 2025 production goal that we anticipated when we first announced the selection of Ohio in January, 2022, construction has been underway since breaking ground in late 2022 and our construction has been proceeding on schedule. Typical construction timelines for semiconductor manufacturing facilities are 3-5 years from groundbreaking, depending on a range of factors...We remain fully committed to the project and are continuing to make progress on the construction of the factory and supporting facilities this year. As we said in our January 2022 site-selection announcement, the scope and pace of Intel's expansion in Ohio may depend on various conditions." Industry insiders believe that an "opening ceremony" could occur around late 2026, or even early 2027.

Semiconductor Manufacturing International Corp (SMIC) is preparing new semiconductor production lines at its Shanghai facilities according to a fresh Reuters report—China's largest contract chip maker is linked to next generation Huawei SoC designs, possibly 5 nm-based Kirin models. SMIC's newest Shanghai wafer fabrication site was an expensive endeavor—involving a $8.8 billion investment—but their flagship lines face a very challenging scenario with new phases of mass production. Huawei, a key customer, is expected to "upgrade" to a 5 nm process for new chip designs—their current flagship, Kirin 9000S, is based on a SMIC 7 nm node. Reuter's industry sources believe that the foundry's current stable of "U.S. and Dutch-made equipment" will be deployed to "produce 5-nanometer chips."

Revised trade rulings have prevented ASML shipping advanced DUV machinery to mainland China manufacturing sites—SMIC workers have reportedly already repurposed the existing inventory of lithography equipment for next-gen pursuits. Burn Lin (ex-TSMC), a renowned "chip guru," believes that it is possible to mass produce 5 nm product on slightly antiquated gear (previously used for 7 nm)—but the main caveats being increased expense and low yields. According to a DigiTimes Asia report, mass production of a 5 nm SoC on SMIC's existing DUV lithography would require four-fold patterning in a best case scenario.

Starfield is the first new universe in over 25 years from the award-winning creators behind Skyrim and Fallout 4, Bethesda Game Studios. Gamers from around the world were excited to jump into this interstellar universe rich with adventure, peril, and excitement. But before anyone hops into space, they need something critical: a spacesuit. So, Xbox has partnered up with the European Space Agency (ESA) to give Starfield fans around the world a chance to win the spacesuit of their dreams, in real life, in addition to other incredible Xbox prizes. This is a physical, wearable, one-of-a-kind garment, fabricated for the most intrepid explorers.

Whether using a provided template as a base, or pushing their imagination to the limit with any creative format of their choice, fans will be asked to provide both a visual illustration of the suit from all sides—hand-drawn, 3D-rendered, or however their vision sees fit—as well as a description of the inspiration of the suit. More specifically, Xbox, Bethesda and the ESA want to know what you would wear in outer space - how would your spacesuit reflect your personal style, individuality and vision for space travel?