TrendForce's latest investigations find that the global foundry industry recorded 1Q25 revenue of US$36.4 billion—a 5.4% QoQ decline. The downturn was softened by last-minute rush orders from clients ahead of the U.S. reciprocal tariff exemption deadline, as well as continued momentum from China's 2024 consumer subsidy program. These factors help offset the typical seasonal slump.

Looking ahead to Q2, the effects of tariff-driven early procurement are expected to fade and lead to a general slowdown. However, continued demand from China's subsidy program, along with pre-launch inventory builds for new smartphone models and stable AI HPC demand, are expected to support capacity utilization and drive a revenue rebound for the top 10 foundries.

According to the Financial Times, new restrictions—affecting the supply of Electronic Design Automation (EDA) software suites to Chinese companies—will cause major disruption within the domestic chip design industry. The US government's latest trade amendments are expected to impact Xiaomi and its freshly launched flagship XRING mobile chip family; the first iteration is a compelling first-party effort. Unlike many Chinese tech firms, the popular smartphone specialist can access pretty advanced TSMC node processes. Xiaomi's CEO—Lei Jun—announced his team's 3 nm design during pre-launch preview events.

Days later, closer analysis indicated a selection of TSMC's "N3E" node process. Digital Chat Station—a noted smartphone industry expert—summarized an uncertain future: "under this ban (of EDA tools), XRING chips will not be breaking through a 2 nm barrier, and can only revolve around the (current 'N3E') 3 nm node for a long time. XRING O1 will also be the only time in recent years that it can be on par with current-gen (proprietary) Apple, Qualcomm, and MediaTek mobile chipsets." Crucially, EDA software plays an important role in creating Gate All Around Field Effect Transistor (GAAFET) structures. TSMC's upcoming 2 nm node process is a GAA product. Tom's Hardware believes that several big Chinese tech players, including Huawei, are in the process of developing in-house EDA tools. Not long after unveiling their XRING flagship, Xiaomi outlined an extended Qualcomm chip deal.

This week at the Electronic Components Technology Conference (ECTC), Intel introduced EMIB-T, an important upgrade to its embedded multi-die interconnect bridge packaging. First showcased at the Intel Foundry Direct Connect 2025 event, EMIB-T incorporates through-silicon vias (TSVs) and high-power metal-insulator-metal capacitors into the existing EMIB structure. According to Dr. Rahul Manepalli, Intel Fellow and vice president of Substrate Packaging Development, these changes allow a more reliable power supply and stronger communication between separate chiplets. Conventional EMIB designs have struggled with voltage drops because of their cantilevered power delivery paths. In contrast, EMIB-T routes power directly through TSVs from the package substrate to each chiplet connection. The integrated capacitors compensate for fast voltage fluctuations and preserve signal integrity.

This improvement will be critical for next-generation memory, such as HBM4 and HBM4e, where data rates of 32 Gb/s per pin or more are expected over a UCIe interface. Intel has confirmed that the first EMIB-T packages will match the current energy efficiency of around 0.25 picojoules per bit while offering higher interconnect density. The company plans to reduce the bump pitch below today's standard of 45 micrometers. Beginning in 2026, Intel intends to produce EMIB-based packages measuring 120 by 120 millimeters, roughly eight times the size of a single reticle. These large substrates could integrate up to twelve stacks of high-bandwidth memory alongside multiple compute chiplets, all connected by more than twenty EMIB bridges. Looking further ahead, Intel expects to push package dimensions to 120 by 180 millimeters by 2028. Such designs could accommodate more than 24 memory stacks, eight compute chiplets, and 38 or more EMIB bridges. These developments closely mirror similar plans announced by TSMC for its CoWoS technology. In addition to EMIB-T, Intel also presented a redesigned heat spreader that reduces voids in the thermal interface material by approximately 25%, as well as a new thermal-compression bonding process that minimizes warping in large package substrates.

The Nintendo Switch 2 hybrid console is due to launch globally next Wednesday (June 4). The highly anticipated next-gen handheld is powered by a custom NVIDIA processor. To the surprise of many industry watchdogs, both parties have semi-recently disclosed a couple of technical details regarding their fruitful hardware collaboration. Historically, Nintendo has guarded many aspects of its past generation hardware. Throughout the 2020s, data miners and leakers have unearthed plenty of pre-release information—leading to theories about the Switch 2 chipset's origins. During the Switch 1 era, TSMC was the chosen manufacturing partner. NVIDIA's off-the-shelf Tegra X1 mobile SoC powered the first wave of Nintendo Switch (2017) devices, in 20 nm form. A 2019 revision resulted in Switch Lite and (refreshed) Switch models being equipped with a more efficient 16 nm solution, also present within 2023's premium OLED variant.

Since then, Switch 2's alleged NVIDIA Tegra T239 SoC was linked to a Samsung 8 nm node process. Earlier this month, extremely brave Chinese leakers produced "full die shot" evidence of South Korean foundry origins. Bloomberg insider news articles have implied that Samsung Semi's mature 8 nm FinFET node is better suited—rather than an equivalent TSMC product—for the Switch 2's custom NVIDIA chipset. Unnamed sources have mentioned critical factors; namely stable production and process compatibility. Industry moles reckon that Samsung leadership is actively and aggressively pushing for a longer Switch 2 chipset production deal. Renewed terms could include a future die shrink; pre-launch analysis indicates a sizeable 207 mm² footprint. Beyond foundry biz negotiations, additional murmurs suggest company executives dangling an OLED panel supply agreement. Industry experts have viewed Samsung's key entry—into the gaming console chip market—as a seismic development. A DigiTimes article dives into a so-called "tripartite cooperation"—involving Nintendo, NVIDIA, and the South Korean semiconductor giant. The Samsung Foundry has floundered and struggled in recent times, but is keen to catch up with its arch rival. Fresh rumors have AMD and Sony considering Samsung's chip making channels; possibly with futuristic PlayStation hardware in mind.

South Korean semiconductor insiders and analysts believe that Samsung's Foundry business is catching up with a main rival. Earlier this month, TSMC leadership openly discussed an unprecedented demand for 2 nm wafer products. Industry moles believe that the Taiwan's top chipmaker is still ahead of contenders in nearby nations. As a result of an alleged leading and comfortable position, TSMC is reportedly upgrading its state-of-the-art facilities with brand-new equipment—indicating a push into 1.4 nm fields. According to a fresh Chosun Biz news article, Samsung engineers are in the process of narrowing the gap between their 2 nm Gate-All-Around (GAA)—also known as SF2—manufacturing node process and TSMC's equivalent technology.

Last month, leaks suggested SF2 trial yields passing the ~40% mark—in comparison, a ~60% figure was uttered by TSMC insiders. Chosun Biz's sources claim that the South Korean foundry team is close to getting their "2 nm process performance evaluation" into a crucial final stage. Yesterday's report posits that NVIDIA and Qualcomm are in the equation; these VIP clients are purportedly considering SF2 as a "second channel" option. Chosun Biz reckons that Team Green is sizing up Samsung Foundry flagship tech for next-gen commercial and enterprise GPUs. Meanwhile, the San Diego-based smartphone processor specialist could be eyeing up SF2 (for a future AP). The latest inside track info points to 2 nm GAA trial production runs breaking beyond aforementioned (approximate) 40% yield rates. TSMC 2 nm wafer charges are reportedly greater than expected, so big industry players are allegedly investigating "cheaper" non-Taiwanese production avenues.

According to Chosun Biz, Intel Foundry client acquisition efforts for the 18A node have shifted into high gear, with the latest reports indicating that Microsoft has inked a substantial foundry deal based on the 18A process. Talks with Google are also said to be advancing, suggesting that Intel may soon secure a second cloud giant for a customer of its 18A technology. Intel's flagship 18A node, which entered risk production earlier this year, is slated for full-scale volume manufacturing before the end of 2025. Beyond the baseline 18A offering, the company is already developing two enhanced variants: 18A-P, scheduled for rollout in 2026, and 18A-PT, targeted for 2028. Chosun Biz reports that prototype 18A-P wafers have been produced in Intel's domestic fabs, pointing out the foundry's swift pace of new node production.

Intel has even begun sharing early PDKs for its next-generation 14A node with select partners, paving the way for continued scaling beyond the 18A era. Strategically, Intel's extensive US fab footprint, which includes two under-construction fabs in Arizona (a USD 32 billion investment), expanded packaging facilities in New Mexico, a new 300 mm logic plant in Oregon, and two Ohio fabs earmarked for the early 2030s, could prove advantageous amid ongoing tariff uncertainties. Beyond North America, Intel is gearing up Fab 34 in Ireland for mass production of its Intel 4 node and inaugural 3 nm chips later this year. In Israel, Fab 38 is being outfitted for EUV-based, high-performance wafer manufacturing, while an advanced packaging site in Penang, Malaysia, supports global assembly and testing.

Despite recent whispers of TSMC losing a key 4 nm node process customer, industry analysts reckon that Taiwan's premier foundry business will remain in a comfortable leading position for the foreseeable future. "Optimistic" expert opinion points to "revenue growth for supply chain players," driven by the rapid progress of the firm's 2 nm manufacturing prowess. Naturally, their cutting-edge manufacturing capabilities—supposedly bolstered by GAAFET—are being tracked with keen interest. According to a fairly fresh Ctee Taiwan news piece, the usual big players are reportedly queued up and present within factory order books. The likes of Apple, NVIDIA, AMD, Qualcomm, MediaTek and Broadcom are mentioned. Mid-way through last month, Team Red officially announced a big collaborative milestone: "(our) next-generation AMD EPYC processor—codenamed "Venice"—is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2 nm (N2) process technology."

Ctee's report cites recent statements by C. C. Wei. Apparently, the TSMC CEO has stressed (on multiple occasions) that there is "unprecedented" demand for his company's 2 nm production pipelines—far exceeding previous levels for 3 nm. In addition, TSMC reps—who are currently touring the States; hosting technology symposiums—have revealed 2 nm (N2) defect density trends. Ctee outlined these intriguing details: "(N2's) defect density (D0) performance is comparable to that of the 5 nm family, and even surpasses the 7 nm and 3 nm processes of the same period, making it one of the most technologically mature advanced nodes." Wei's foundry team seems to be well ahead of main competition; insiders reckon that alleged equipment upgrades signal a push into 1.4 nm territories. Crucially, mass production of 2 nm (N2) wafers is expected to begin later this year—a cross-facility push was uttered by industry moles.

AMD has reportedly decided to move its 4 nm chip orders from Samsung to TSMC's facilities in Arizona, United States. This is a significant loss for Samsung, as AMD had been working closely with Samsung on the SF4X process for EPYC server processors, Ryzen APUs, and Radeon graphics cards. It's worth noting that in May 2023, AMD announced the exact opposite—moving from TSMC to Samsung for some of its 4 nm CPUs. This partnership was an important part of AMD's strategy to use multiple manufacturers; however now appears to be failing. Reports indicate that AMD's decision comes from concerns about the stability and consistency of Samsung's manufacturing process, leading AMD to cancel plans for mass production of graphics chips using Samsung's 4 nm technology.

These changes in manufacturing strengthen TSMC's leading position in the chip manufacturing industry, even though relying on a single manufacturer creates geopolitical risks. AMD continues to deepen its relationship with TSMC, committing to use TSMC's advanced 2 nm technology for its upcoming "Venice" processors, which have completed testing at TSMC's Arizona facility and remain on schedule for release in 2026. Meanwhile, Samsung Electronics has reportedly achieved better-than-expected results in testing its SF2 (2 nm) process, with initial yields above 30%. The company plans to stabilize this process in the second half of 2025 to begin mass production of the Exynos 2600 mobile chip. Building on this progress, Samsung is reportedly close to securing an agreement to manufacture Qualcomm's Snapdragon 8 Elite 2 using its new 2 nm process.

Intel is exploring a new way to cool its hottest chips by weaving tiny water channels into the processor package itself. At its Foundry Direct Connect showcase, via HardwareLuxx coverage, the company revealed working prototypes for LGA desktop CPUs, BGA servers, and AI modules. Rather than flood the bare silicon, a slim copper block sits on top of the package, its microchannels precisely etched to carry coolant directly over the hottest areas. Intel engineers cooled Core Ultra desktop chips and high-end Xeon processors in live demonstrations. The system moves standard liquid-cooling fluid through those channels at a rate fast enough to whisk away up to 1,000 watts of heat. In the lab, that level of thermal performance isn't standard for everyday PC use, but it matches the demands of AI training, scientific computing, and professional workstations.

This design stands out because of its attention to every layer between the chip and the coolant. Intel carefully controls the thickness of the silicon die, the solder or liquid-metal thermal interface material, the integrated heat spreader, and the water block itself. By reducing or removing traditional barriers, thermal resistance falls, and engineers report roughly 20% better cooling than a standard water block mounted on a delidded die. Those copper blocks measure only a few millimeters in height yet still deliver strong flow rates. During chip layout, teams space out power-hungry blocks or flag-tight clusters so the cooling channels can target critical hotspots. This co-design of package and cooler goes much deeper than any off-the-shelf solution. While the basic research dates back nearly two decades, Intel has been refining the method for years. Still, with processors growing more powerful and densely packed, package-level liquid cooling could move from laboratory demo to essential tool for data centers and enthusiast rigs.

During Intel's Foundry Direct Connect symposium in San Jose, where Intel confirmed the ramp of the 18A node at the Arizona fab, the company also announced Intel has achieved a significant advancement in its future node development with the announcement of "turbo cell" technology for its upcoming 14A process. Now slated for production in 2027, this progress supports Intel's objective of introducing five process nodes within a four-year period. The 18A node is presently in risk production and incorporates RibbonFET gate-all-around transistors along with PowerVia, Intel's backside power-delivery architecture. Intel anticipates transitioning 18A to full-volume manufacturing later this year, thereby internalizing greater chiplet assembly work that was previously outsourced for designs such as Lunar Lake.

For the upcoming 14A process, it combines second-generation RibbonFET with PowerDirect, the company's enhanced power network. When implemented using High-NA EUV lithography, Intel projects a performance-per-watt gain of between 15 and 20 percent over the 18A process. Of particular interest is the introduction of turbo cells. These specialized standard-cell libraries enable designers to integrate both high-performance and energy-efficient cells within a single design block. Such flexibility permits precise optimization of chip speed, power consumption, and die area to meet diverse application requirements. In practical terms, turbo cells are expected to elevate peak CPU frequencies and accelerate critical GPU pathways without incurring substantial energy penalties. Intel has already distributed its PDK for the 14A node to prospective customers for feedback, with multiple partners already planning test-chip tape-outs. Complementing these advances, the company will employ advanced packaging technologies, including Foveros 3D stacking and EMIB, and a new high-bandwidth EMIB-T variant to integrate 14A and 18A dies within unified hybrid packages.

Samsung Electronics today reported financial results for the first quarter ended March 31, 2025. The Company posted KRW 79.14 trillion in consolidated revenue, an all-time quarterly high, on the back of strong sales of flagship Galaxy S25 smartphones and high-value-added products. Operating profit increased to KRW 6.7 trillion despite headwinds for the DS Division, which experienced a decrease in quarterly revenue.

The Company has allocated its highest-ever annual R&D expenditure for 2024, and in the first quarter of this year, it has also increased its R&D expenditure by 16% compared to the same period last year, amounting to 9 trillion won. Despite the growing macroeconomic uncertainties due to recent global trade tensions and slowing global economic growth, making it difficult to predict future performance, the Company will continue to make various efforts to secure growth. Additionally, assuming that the uncertainties are diminished, it expects its performance to improve in the second half of the year.

Cadence today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence's continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry.

Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs.

Industry watchdogs have held the belief that Samsung's foundry business has lost several key clients due to alleged yield problems—the South Korean megacorp appears to be diligently working on major improvements with currently "in-progress" manufacturing processes; namely 2 nm GAA (aka SF2). Semiconductor industry insiders believe that TSMC is still leading the way with a recently completed trial run of their own 2 nm design, but rumors of elevated prices have reportedly upset certain important customers. According to a fresh Sedaily news article, Qualcomm has conducted negotiations with Samsung Foundry top brass—semiconductor industry moles claim that a "Snapdragon 8 Elite 2nd generation product" was the main topic of discussion. This next-gen flagship mobile chipset was previously linked to a 3 nm TSMC node, but newer rumors point to a possible spin-off that will utilize a "more advanced 2 nm process"—courtesy of Samsung Electronic's prime "Hwaseong S3" facility.

Sedaily and Jukanlosreve reckon that mass production will kick off at this cutting-edge early next year. Earlier today, Jukanlosreve added extra conjecture/context via a long social media bulletin: "the completed chips are expected to be integrated into Samsung Galaxy smartphones slated for launch in H2 2026. Design work is to finish in Q2 2025, after which mass-production preparations will begin and wafer runs will start in Q1 2026. Output is estimated at roughly 1,000 twelve-inch wafers per month. Given that Samsung's current 2 nm capacity is about 7,000 wafers/month, this project would utilize only around 15 % of its available capacity—suggesting this is a modest order rather than a large-scale win." These predictions have surprised many industry observers; Samsung leadership has seemingly tried to prioritize the in-house Exynos mobile processor designs within futuristic flagship Galaxy smartphone devices. Jukanlosreve reckons that the Samsung Foundry is keen to embrace any new "golden opportunities," given the operation's weakened track record across the past half decade. One unnamed insider posited: "this Qualcomm partnership could pave the way for orders from other big tech players." Sedaily sent a query to Samsung HQ, regarding the latest inside talk—a company spokesperson replied with: "we cannot confirm anything related to customer orders."

As revealed during a recent Q1 earnings call, Intel leadership mentioned that "external clients are getting their ASICs designs tested." The company's foundry business is working towards the finalization of its much discussed 18A node process, with alleged trial samples receiving an "impressive performance rating." According to Ctee Taiwan, Team Blue's foundry service has submitted test subjects to the likes of NVIDIA, Broadcom and Faraday Technology. The latter organization has (reportedly) disclosed that the 18A platform tape-out was completed last October—since then, received samples have been "successfully connected." Industry moles believe that NVIDIA and Broadcom are in the middle of conducting manufacturing tests. Additional whispers suggest the delivery of 18A prototypes chez IBM and several other unnamed partner companies. Insiders have indicated impressive/good "verification results." Contrary to reports from other sources, Ctee has picked up on insider chatter about Intel's next-gen Nova Lake compute tile design being "not entirely outsourced." Further conjecture points to Team Blue becoming increasingly confident in its own manufacturing techniques.

According to the latest South Korean semiconductor industry whispers, Samsung's 2 nm GAA node process (aka SF2) development team has hit another pleasing experimental production milestone. An Asia Economy SK news article has sourced insights from inside track players—one unnamed mole posited that: "the 2 nm yield currently under development at Samsung Foundry is much better than previously known...and more positive than the (reportedly abandoned) 3 nm process." A combination of relatively new leadership and a rumored welcoming of first wave High-NA EUV equipment has likely bolstered next-gen efforts, after late 2024's alleged failure of 3 nm prototypes. Leaks from earlier in 2025 indicated SF2 test yields wavering around 20-30%; far from ideal—back then, insider reports suggested that TSMC was well on the way to achieving 60% rates with a competing 2 nm product line. Asia Economy has picked up on mutterings about Samsung's current progress—latest outputs: "have exceeded 40% in the wafer testing stage at a post-processing company."

Industry watchdogs reckon that the South Korean's foundry business is making good progress; perhaps on track to commence speculated mass production by the third quarter of this year—just in time to get finalized flagship "Exynos 2600" mobile chips in the manufacturing pipeline. The Taiwanese rumor mill indicated a major milestone "completion" of TSMC's 2 nm trial phase at some point last month—insiders mentioned excellent yield rates: in the region of 70-80%. Cross-facility mass production could start later this year, but experts propose that the market leader will be implementing price hikes. These "elevated charges" could send loyal TSMC customers in the direction of an alternate source of 2 nm wafers: Samsung. Fresh semicon biz gossip has the likes of Apple, AMD and NVIDIA in the picture.

Samsung's foundry business seems to be busying itself with the rumored refinement of a 2 nm GAA (SF2) manufacturing node process—for possible mass production by the end of 2025, but company leadership will very likely be considering longer term goals. Mid-way through last month, industry moles posited that the megacorporation's semiconductor branch was questioning the future of a further out 1.4 nm (SF1.4) production line. Officially published roadmaps have this advanced technology rolling out by 2027. Despite present day "turmoil," insiders believe that a new team has been established—tasked with the creation of a so-called "dream semiconductor process." According to a fresh Sedaily news article, this fledgling department has started development of a 1 nm foundry process.

Anonymous sources claim that Samsung executives are keeping a watchful eye on a main competitor—as stated in the latest South Korean report: "there is a realistic gap with Taiwan's TSMC in technologies that are close to mass production, such as the 2 nm process, the company plans to speed up the development of the 1 nm process, a future technology, to create an opportunity for a turnaround." A portion of the alleged "1 nm development chip team" reportedly consists of veteran researchers from prior-gen projects. Semiconductor industry watchdogs theorize that a canceled SF1.4 line could be replaced by an even more advanced process. Sedaily outlined necessary hardware upgrades: "the 1.0 nanometer process requires a new technology concept that breaks the mold of existing designs as well as the introduction of next-generation equipment such as high-NA EUV exposure equipment. The company is targeting mass production after 2029." Samsung's current Advanced Technology Roadmap does not extend beyond 2027—inside sources claim that the decision to roll with 1.0 nm was made at some point last month.

Intel and TSMC are reportedly locked in talks to form a semiconductor foundry joint-venture (JV). This sensational piece of news comes from Reuters, which says that the two companies have reached a preliminary agreement to form the JV. Apparently, the move saves TSMC from building any hard infrastructure on U.S. soil, and instead use Intel's semiconductor foundry facilities. This would hence bring TSMC's semiconductor manufacturing IP and workforce to the U.S., however it remains to be seen if the very latest foundry technology would be handed over to the JV. TSMC would hold a 20% stake in the venture, and Intel the rest. Investors of Intel and TSMC reacted very differently to the news, with the TSMC stock falling 6% and Intel gaining 5%. Reuters also reports that it was the Trump Administration that negotiated this joint-venture between TSMC and Intel in a bid to "revitalize Intel."

Intel's Vision 2025 conference ended yesterday—since then, media outlets have spent time poring over a multitude of announcements made during the two-day Las Vegas, Nevada event. Notably, Team Blue leadership confirmed that their Core Ultra 300 "Panther Lake" processor series is built to scale (on) 18A, and is on track for production later this year." Prominently-displayed presentation material indicated a roadmapped 2026 launch of "Panther Lake" client chips. The success of this next-gen mobile processor family is intertwined with Intel's Foundry service making marked progress. As summarized by the company's social media account, production teams are celebrating another milestone: "Intel 18A has entered risk production. This final stage is about stress-testing volume manufacturing before scaling up to high volume in the second half of 2025."

Under Pat Gelsinger's command, Team Blue set off on a "five nodes in four years" (5N4Y) adventure around mid-2021. This plan is set to conclude with the finalization of 18A, at some point this year, under a newly refreshed regime—with Lip-Bu Tan recently established as CEO. During an on-stage Intel Vision 2025 session, Kevin O'Buckley—Senior VP of Foundry Services—explained the meaning of: "risk production, while it sounds scary, is actually an industry standard terminology, and the importance of risk production is we've gotten the technology to a point where we're freezing it...Our customers have validated that; 'Yep, 18A is good enough for my product.' And we have to now do the 'risk' part, which is to scale it from making hundreds of units per day to thousands, tens of thousands, and then hundreds of thousands. So risk production..is scaling our manufacturing up and ensuring that we can meet not just the capabilities of the technology, but the capabilities at scale." By original "5N4Y" decree, top brass demanded that process nodes be (fully) available for production, rather than be stuck in a (not quite there) final high volume manufacturing (HVM) phase.

Industry insiders posit that TSMC's two flagship fabrication facilities are running ahead of schedule with the development of an advanced 2 nm (N2) process node. A cross-facility mass production phase is tipped to begin later this year, which leaves room for next-level experiments. Taiwan's Economic Daily News has heard supply chain whispers about the Baoshan "P2" plant making internal preparations for a truly cutting edge 1.4 nm-class product. According to the report, unnamed sources have claimed that: "TSMC has made a major breakthrough in the advancement of its 1.4 nm process. (The company) has recently notified suppliers to prepare the necessary equipment for 1.4 nm, and plans to install a trial production 'mini-line' at P2 (Baoshan Fab 20)."

Their Hsinchu-adjacent "Fab 20" site is touted as a leading player in the prototyping of this new technology. Industry moles reckon that "1.4 nm expertise" will eventually trickle over to nearby "P3 and P4 plants" for full production phases. Allegedly, these factories were originally going to be involved in the manufacturing of 2 nm (N2) wafers. Additionally, TSMC's "Fab 25" campus could potentially play host to trial 1.4 nm activities—the Economic Daily News article proposes that four plants based in the Central Taiwan Science Park are pitching in with collaborative work. As interpreted by TrendForce, "P1" could begin "risk trial production" by 2027, followed by full-scale output within the following year.

Over the past weekend Jukanlosreve declared via social media that Samsung's: "Exynos 2600 (mobile SoC) is definitely back, and it will be used in the Galaxy S26 series. But the chip volume is so limited that it'll likely be similar to the Exynos 990 situation. I'm not sure if SF2 is actually any good." Mid-way through March, the keen observer of semiconductor industry conditions posited that Samsung's Foundry business could abandon a 1.4 nm (SF1.4) process node. SF2 (aka 2 nm GAA) seems to be in a healthier place, according to insiders—thanks to rumored assistance from an external AI-specialist partner. The development of next-generation flagship Exynos smartphone processors are allegedly closely tied with Samsung Foundry's 2 nm GAA manufacturing process.

As alluded to by Jukanlosreve's recent prediction, the statuses of leaked 2 nm-based "Exynos 2600" and "Exynos 2500" chips were often questioned by industry watchdogs in the past. The latter is purportedly destined for rollout in forthcoming affordable "Galaxy Z Flip FE" models, albeit in mature 4 nm form. Vhsss_God—another source of inside track info—has weighed in on the topic of Samsung's next-gen chipset roadmap. Compared to Jukanlosreve's musings, their similarly-timed weekend projection seemed to be quite fanciful: "exclusive leak...Samsung doesn't want to use Exynos or Qualcomm Snapdragon chips anymore. S26 line is targeted to launch with the new Samsung developed chip (2 nm)—formerly referred to as Exynos 2600. (The company) will try its hardest to ditch Snapdragon on the entire Galaxy line next year." Perhaps there is too much of a negative stigma attached to Samsung's long-running chipset nomenclature, but the majority of foundry moles continue to label incoming designs as Exynos processors.

According to a report produced by semiconductor industry analysts at Kiwoom Securities—a South Korean financial services firm—Semiconductor Manufacturing International Corporation (SMIC) is expected to complete the development of a 5 nm process at some point in 2025. Jukanlosreve summarized this projection in a recent social media post. SMIC is often considered to be China's flagship foundry business; the partially state-owned organization seems to heavily involved in the production of (rumored) next-gen Huawei Ascend 910 AI accelerators. SMIC foundry employees have reportedly struggled to break beyond a 7 nm manufacturing barrier, due to lack of readily accessible cutting-edge EUV equipment. As covered on TechPowerUp last month, leading lights within China's semiconductor industry are (allegedly) developing lithography solutions for cutting-edge 5 nm and 3 nm wafer production.

Huawei is reportedly evaluating an in-house developed laser-induced discharge plasma (LDP)-based machine, but finalized equipment will not be ready until 2026—at least for mass production purposes. Jukanlosreve's short interpretation of Kiwoom's report reads as follows: (SMIC) achieved mass production of the 7 nm (N+2) process without EUV and completed the development of the 5 nm process to support the mass production of the Huawei Ascend 910C. The cost of SMIC's 5 nm process is 40-50% higher than TSMC's, and its yield is roughly one-third." The nation's foundries are reliant on older ASML equipment, thus are unable to produce products that can compete with the advanced (volume and quality) output of "global" TSMC and Samsung chip manufacturing facilities. The fresh unveiling of SiCarrier's Color Mountain series has signalled a promising new era for China's foundry industry.

In a letter addressed to stockholders, Intel's new CEO—Lip-Bu Tan—roadmapped the importance of a couple of major upcoming product launches. Starting off, Team Blue's new chief detailed a fresh approach, with the casting off of old strategies: "achieving the results I know Intel is capable of starts by refocusing on our customers. This has been priority number one since my first day on the job. I am listening carefully to their feedback so that we continue driving the changes needed to delight our customers and strengthen our competitive position. Plain and simple, the time for talk is over. We must turn our words into action and deliver on our commitments. I have been pleased to see the leadership team has already started driving the culture change needed to make this happen. As CEO, I will continue to drive this transformation so that we move faster, work smarter and make it easier for customers to win with Intel."

Tan's mentioning of Core Ultra "Panther Lake" processors arriving within the second half of this year aligns with prior official statements. Insiders posited that Panther Lake-H (PTL-H) mobile CPUs were delayed into 2026 due to issues with the Foundry's 18A process node, but an Intel executive dismissed these claims a few weeks ago. Interestingly, the firm's Chinese office outlined an "early 2026 volume launch" of "Panther Lake (18A)" chips during a mid-March AI PC press event. A presentation slide indicated that an Early Enablement Program (EEP) is expected to start in October; Team Blue's loose terminology likely classes the sending off of samples—to OEMs, for approval—as a "real" product launch.

Intel and SK Hynix have finalized an $8.85 billion transaction involving Intel's NAND flash memory operations, marking the conclusion of a two-phase deal initiated in 2020. In the first phase of the transaction, SK Hynix acquired Intel's SSD division along with a NAND production facility in Dalian, China, for $6.61 billion. The Dalian facility was later rebranded as Solidigm. Notably, this phase transferred only the physical assets and operational facilities, leaving behind critical intellectual property, research and development infrastructure, and specialized technical staff. The second phase, finalized with a payment of $1.9 billion this Tuesday, addressed these remaining components. With this payment, SK Hynix secured full rights to Intel's proprietary NAND technology, R&D resources, and the technical workforce dedicated to NAND operations.

During the transition period, Intel maintained control over these elements, which limited integration between Solidigm and Intel's NAND teams. This separation was designed to manage operational risks and gradually transfer capabilities. Completing this deal helps with a strategic restructuring of Intel's portfolio as it shifts focus toward high-growth areas such as AI chip development, foundry services, and next-generation semiconductor manufacturing. A $1.9 billion financial injection is perfect in time for Intel Foundry business, burning billions per year, to offset some of the losses. For SK Hynix, consolidating the complete range of Intel's NAND operations enhances its competitive position in the global NAND market, providing access to established technologies and key industry expertise. This finalization is part of a broader trend where companies divest from commoditized memory products to concentrate on more advanced semiconductor solutions like AI chips and other accelerators, which are enjoying higher margins and a better business outlook.

According to an investment bank UBS note, two industry titans—NVIDIA and Broadcom—are potential future clients that could significantly enhance Intel's Foundry business revenue. To revitalize Intel, newly appointed CEO Lip-Bu Tan reportedly aims to forge strategic alliances with two AI chip manufacturers. Tan, who assumed leadership earlier this month, is determined to rebuild the company's reputation by focusing on customer satisfaction and accelerating the development of its foundry business. UBS analyst Tim Arcuri suggests that while Broadcom might join the client roster, NVIDIA appears to be the more likely candidate. Rather than initially manufacturing NVIDIA's AI GPUs, Intel is expected to begin production with gaming GPUs. NVIDIA could even move to AI GPU production at Intel's fabs if satisfied.

Despite some early optimism, Intel's new CEO is now committed to addressing issues related to power consumption in Intel's manufacturing processes. UBS analyst Tim Arcuri noted that the firm is pushing hard to introduce a lower-power version of its 18A process, the so-called 18AP, which has reportedly struggled to meet energy requirements. Additionally, Intel is working to improve its advanced packaging techniques to rival Taiwan's TSMC CoWoS (S/L/R variants) technology, aiming to overcome packaging constraints that have slowed AI chip production. Analysts speculate that Intel might also become a secondary supplier to tech giant Apple. A promising partnership with Taiwan's United Microelectronics (UMC) could pave the way for Intel's chips to find their way into future Apple products. Whatever materializes, we are yet to see. Switching foundries from TSMC to Intel entirely is not possible for any of the aforementioned fabless designers, so it will likely be dual-sourcing at first, with some non-flagship SKUs getting the full port to Intel 18A.

Last week, South Korean semiconductor industry moles let slip about the development of an "Exynos 2600" mobile chipset at Samsung Electronics. This speculative flagship processor was linked to the manufacturer's (inevitable) launch of Galaxy S26 smartphone models in early 2026. Despite rumors of the firm's Foundry service making decent progress with their preparation of a cutting-edge 2 nm Gate-All-Around (GAA) node, certain critics reckon that Samsung will be forced into signing another (less than ideal) chip supply deal with Qualcomm. According to The Bell SK's latest news report, Samsung's LSI Division is working with plenty of determination—an alleged main goal being the next wave of top-end Galaxy smartphones deployed next year with in-house tech onboard.

Inside sources propose that Samsung's Exynos 2600 SoC needs to be "finished by the middle of the third quarter of this year," thus ensuring the release of in-house chip-powered Galaxy S26 devices. It is not clear whether this forecast refers to a finalized design or the start of mass production. The latest whispers regarding another proprietary next-gen mobile processor—Exynos 2500—paint a murky picture. Past leaks indicated possible avenues heading towards forthcoming Galaxy Z Flip 7 and Fold 7 smartphone models. The latest reports have linked this design to a mature 4 nm process and eventual fitting inside affordable "Galaxy Z Flip FE" Enterprise Edition SKUs. The Bell contacted one of its trusted sources—the unnamed informant observed that everything is in flux: "Exynos 2500 production plan is constantly changing...I thought it was certain, but I heard that the possibility has recently decreased slightly." Reportedly, Samsung employees have their plates full with plenty of simultaneous projects in 2025.