Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Intel's ambitious fab expansion plans, which are currently facing a temporary halt, are of significant importance. The German government, as reported by HardwareLuxx, is now considering redirecting €10 billion from the Climate and Transformation Fund (KTF) initially allocated to Intel, potentially returning these subsidies to the federal budget. The pause on Intel's investment to 2029-2030 (according to Tom's Hardware) not only threatens Germany's hopes of becoming one of semiconductor industry leaders but has also sparked debate over the intended use of this substantial financial support. Given the rise of geopolitical tensions, the urgency and significance of the German semiconductor industry in the current economic landscape cannot be overstated. The potential negative impact of the halt on Intel's investment is a cause for concern and engagement.

Finance Minister Christian Lindner has proposed that the funds be reallocated to address other economic needs, emphasizing fiscal responsibility amid current challenges. In contrast, Economic Affairs Minister Robert Habeck, whose department manages the KTF, opposes this reallocation, arguing that the fund should continue to support long-term economic growth and environmental initiatives. This disagreement between Lindner and Habeck illustrates the competing priorities within the government over the best use of public funds in uncertain economic times. The urgency of resolving this impasse is clear, as it will require navigating these tricky political waters while weighing the strategic importance of securing significant semiconductor investments in Germany. If Intel continues its Magdeburg expansion by the end of this decade, the terms for state subsidies might be changed. However, that is something to worry about in the distant future, as the blue giant has the priority of getting its financials back in line first.

Today, the Department of Commerce and Natcast, the operator of the National Semiconductor Technology Center (NSTC), announced the expected location for the first CHIPS for America research and development (R&D) flagship facility. The CHIPS for America Extreme Ultraviolet (EUV) Accelerator, an NSTC facility (EUV Accelerator), is expected to operate within NY CREATES' Albany NanoTech Complex in Albany, New York, supported by a proposed federal investment of an estimated $825 million. The EUV Accelerator will focus on advancing state of the art EUV technology and the R&D that relies on it.

As a key part of President Biden's Investing in America agenda, CHIPS for America is driven by the growing need to bolster the U.S. semiconductor supply chain, accelerate U.S. leading-edge R&D, and create good quality jobs around the country. This proposed facility will bring together NSTC members from across the ecosystem to accelerate semiconductor R&D and innovation by providing NSTC members access to technologies, capabilities, and critical resources.

After announcing the world's first 300-millimeter gallium nitride (GaN) power wafer and opening the world's largest 200-millimeter silicon carbide (SiC) power fab in Kulim, Malaysia, Infineon Technologies AG has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.

"The world's thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology," said Jochen Hanebeck, CEO at Infineon Technologies. "Infineon's breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry's innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN."

Nikon Corporation (Nikon) is developing a digital lithography system with resolution of one micron (L/S) and high productivity for advanced semiconductor packaging applications. This product is scheduled to be released in Nikon's fiscal year 2026.

The rapid adoption of artificial intelligence (AI) technology is driving demand for integrated circuits (ICs) for data centers. In the field of advanced packaging, including chiplets, the size of packages is increasing with the miniaturization of wiring patterns. This will lead to heightened demand for panel level packages that use glass and other materials suitable for larger packages, requiring exposure equipment that combines high resolution with a large exposure area. To meet these demands, Nikon is developing digital exposure equipment that combines the high-resolution technology of its semiconductor lithography systems, which has been cultivated over many decades, along with the excellent productivity made possible with the multi-lens technology of its FPD lithography systems.

After Apple, we just learned that AMD is the next company in line for US-based manufacturing in the TSMC Arizona facility. Industry analyst Tim Culpan reports that TSMC's Fab 21 in Arizona will soon be producing AMD's high-performance computing (HPC) processors, with tape out and manufacturing expected to commence on TSMC's 5 nm node next year. This move comes after previously reported Apple's A16 SoC production, which is already in progress at the facility and could see shipments before the end of this year, significantly ahead of the initially projected early 2025 schedule. The production of AMD's HPC chips in Arizona marks a crucial step towards establishing an AI-hardware supply chain operating entirely on American soil, which is expected to further expand with Intel Foundry and Samsung Texas facility.

Making HPC processors domestically serves as a significant milestone in reducing dependence on overseas semiconductor manufacturing and strengthening the US's position in the global chip industry. Adding to the momentum, TSMC and Amkor recently announced a collaboration on advanced packaging technologies, including Integrated Fan-Out (InFO) and Chip-on-Wafer-on-Substrate (CoWoS), which are vital for high-performance AI chips. However, as Amkor facilities are yet to be built, these chips are going to be shipped back to Taiwan for packaging before being integrated into the final product. Once the Amkor facility is up and running, Arizona will become the birthplace of fully manufactured and packaged silicon chips.

Samsung Electronics is grappling with significant challenges in its semiconductor division, particularly in its memory and foundry businesses. The company's top management, led by DS Division Vice Chairman Jeon Young-hyun, recently issued a public apology for the division's underwhelming performance. The tech giant's struggles are best seen in its advanced 3 nm Gate-All-Around (GAA) FET node, which reportedly yields only 10-20% of working silicon. This low yield rate has made potential customers hesitant to partner with Samsung, dealing a blow to its foundry business. Samsung Securities projects a 500 billion won (approximately $385 million) loss this year for Samsung Foundry and the LSI division combined. In the global foundry market, Samsung's position has weakened considerably. The company currently holds just 11.5% of the market share in Q2, while industry leader TSMC dominates with a commanding 62.3%. This disparity has led to speculation about the possible spinoff of Samsung Foundry, as the company reevaluates its strategy in the advanced semiconductor manufacturing sector.

Memory unit, one of Samsung's biggest assets, is slowly being one-upped by SK Hynix, which could overtake Samsung as the number one memory maker thanks to strong HBM demand. The management's apology acknowledges the concerns raised about the company's technological competitiveness and future prospects. Vice Chairman Jeon emphasized the need to restore fundamental competitiveness in technology and quality, which he described as the company's "lifeblood." Despite these challenges, Samsung's leadership remains optimistic about turning the crisis into an opportunity. They have pledged to focus on long-term solutions, invest in pioneering technologies, and foster a culture of innovation and open communication within the organization. As one of only three companies left in the advanced semiconductor manufacturing field, alongside TSMC and Intel, Samsung's ability to overcome these hurdles will be crucial not only for the company but for the entire industry.

Amkor Technology, Inc. and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region's semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC's advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC's front-end fab and Amkor's back-end facility will accelerate overall product cycle times.

The grass isn't always greener on the other side, especially as we're running out of sides in the advanced semiconductor manufacturing sector. A recent report by Business Korea highlights Samsung Securities' July publication titled "Geopolitical Paradigm Shift and Industry," which paints a less-than-optimistic picture of Samsung's current state of affairs. The report even evaluates a possible spinoff of Samsung Foundry. The Korean tech giant has faced various business setbacks related to its state-of-the-art 3 nm Gate-All-Around (GAA) FET node. Reports indicate that this node only manages to yield 10-20% of working silicon, making potential customers reluctant to secure partnerships with Samsung. Samsung Securities projects that Samsung Foundry, along with the LSI division, will suffer a 500 billion won (about $385 million) loss this year.

Poor yields and difficulty securing customers have left Samsung facing tough choices, including the possible sale of its massive Foundry unit, which manufactures logic for external customers. It's noteworthy that Samsung is one of only three companies left in the advanced semiconductor manufacturing field, alongside TSMC and Intel. Many companies struggled to deliver results when transitioning to sub-7 nm nodes. Global Foundries dropped out of the race to focus on mature nodes, while Intel faced delays. TSMC has been the only company so far to consistently set and execute its goals, positioning itself as the industry leader. With low yields on the 3 nm GAA FET node, Samsung currently holds 11.5% of the global foundry market share in Q2, while TSMC dominates with 62.3%.

Canon Inc. announced today that it will ship its most advanced lithography platform, the FPA-1200NZ2C nanoimprint lithography (NIL) system for semiconductor manufacturing, to the Texas Institute for Electronics (TIE), a Texas-based semiconductor consortium. Canon became the first in the world to commercialize a semiconductor manufacturing system that uses NIL technology, which forms circuit patterns in a different method from conventional projection exposure technology, when it released the FPA-1200NZ2C on October 13, 2023.

In contrast to conventional photolithography equipment, which transfers a circuit pattern by projecting it onto the resist coated wafer, the new product does it by pressing a mask imprinted with the circuit pattern into the resist on the wafer like a stamp. Because its circuit pattern transfer process does not go through an optical mechanism, fine circuit patterns on the mask can be faithfully reproduced on the wafer. With reduced power consumption and cost, the new system enables patterning with a minimum linewidth of 14 nm, equivalent to the 5 nm node that is required to produce most advanced logic semiconductors currently available.

Intel's recent financial woes have brought the company into severe cost-cutting measures, including job cuts and project delays. However, a silver lining remains—Intel is reportedly in the final stages of securing $8.5 billion in direct funding from the US government under the CHIPS Act, delivered by the end of the year. The potential financing comes at a crucial time for Intel, which has been grappling with financial challenges. The company reported a $1.6 billion loss in the second quarter of 2024, leading to short-term setbacks. However, thanks to sources close to the Financial Times, we learn that Intel's funding target will represent the CHIPS Act's largest share, leading to a massive boost to US-based semiconductor manufacturing.

Looking ahead, the potential CHIPS Act funding could serve as a catalyst for Intel's resurgence, reassuring both investors and customers about the company's future. A key element of Intel's recovery strategy lies in the ramp-up of production for its advanced 18A node, which should become the primary revenue driver for its foundry unit. This advancement, coupled with the anticipated government backing, positions Intel to potentially capture market share from established players like TSMC and Samsung. The company has already secured high-profile customers such as Amazon and (allegedly) Broadcom, hinting at its growing appeal in the foundry space. Moreover, Intel's enhanced domestic manufacturing capabilities align well with potential US government mandates for companies like NVIDIA and Apple to produce processors locally, a consideration driven by escalating geopolitical tensions.

TSMC and Samsung are reportedly in talks with the United Arab Emirates (UAE) to establish chip factories in the Gulf nation. As reported by the Wall Street Journal, this "desert dream" aligns with the UAE's ambitious plans to diversify its economy beyond oil and become a key player in the AI sector by building chips for AI domestically. The UAE and neighboring Saudi Arabia plan to leverage their oil wealth to invest in cutting-edge manufacturing, with AI emerging as a primary focus due to its high computational demands. Successful implementation of chip factories could significantly boost the region's AI capabilities and impact the global semiconductor supply chain. However, the project faces substantial challenges. Previous attempts to establish semiconductor manufacturing in the Gulf, such as the GlobalFoundries initiative over a decade ago, have yet to progress beyond initial planning.

The current proposal faces even greater obstacles, with estimated costs exceeding $100 billion for a state-of-the-art facility and necessary infrastructure. Geopolitical concerns add another layer of complexity. Recent US export restrictions of certain chips to the Gulf region may complicate the transfer of advanced manufacturing processes to the UAE. Despite these hurdles, the potential benefits are significant. For the UAE, success would represent a major step towards economic diversification and technological leadership. TSMC and Samsung could gain a strategic presence in a region eager for technological advancement. TSMC noted that the company focuses on current expansion projects in the US, Japan, and Germany, while Samsung declined to comment.

The Biden-Harris Administration announced today that Intel Corporation has been awarded up to $3 billion in direct funding under the CHIPS and Science Act for the Secure Enclave program. The program is designed to expand the trusted manufacturing of leading-edge semiconductors for the U.S. government.

The Secure Enclave program builds on previous projects between Intel and the Department of Defense (DoD) such as Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP). As the only American company that both designs and manufactures leading-edge logic chips, Intel will help secure the domestic chip supply chain and collaborate with the DoD to help enhance the resilience of U.S. technological systems by advancing secure, cutting-edge solutions.

Samsung's foundry plans have again hit a major setback. The company notified staff at its Taylor, Texas facility that it was temporarily removing workers from the site because it is still experiencing challenges with 2 nm semiconductor yields, delaying mass production timelines from late 2024 to 2026. The Taylor site had been anticipated as the flagship facility for Samsung's sub-4 nm production, allowing access to potential customers near the facility. While Samsung has moved rapidly in terms of process development, its yields for advanced nodes have outstripped them, the company's yields for sub-3 nm processes hover around 50%, with Gate-All-Around (GAA) technology witnessing yields of only 10-20%, significantly lower than neighboring competitor TSMC's 60-70% for corresponding nodes.

The yield gaps that the company is experiencing have exacerbated the gap in market share, with TSMC capturing 62.3% of the global foundry market share in Q2 versus Samsung's 11.5%. The company is struggling to gain share despite efforts by Chairman Lee Jae-yong - including visits to component suppliers ASML, and Zeiss - and these yields put at risk as much as 9 trillion won in U.S. CHIP Act potential subsidies that are dependent upon operational milestones.

According to a recent report from Bloomberg, Intel is in talks with investment banks about a possible spin-out of its foundry business, as well as scraping some existing expansion plans to cut losses. As the report highlights, sources close to Intel noted that the company is exploring various ways to deal with the recent Q2 2024 earnings report. While Intel's revenues are in decline, they are still high. However, the profitability of running its business has declined so much that the company is now operating on a net loss, with an astonishing $1.61 billion in the red. CEO Pat Gelsinger is now exploring various ways to control these losses and make the 56-year-old giant profitable again. Goldman Sachs and Morgan Stanley are reportedly advising Intel about its future moves regarding the foundry business and overall operations.

The Intel Foundry unit represents the biggest consumer of the company's funds, as the expansion plans across the US and Europe are costing Intel billions of US Dollars. Even though the company receives various state subsidies to build semiconductor manufacturing facilities, it still has to put much of its capital to work. Given that the company is running tight on funds, some of these expansion plans that are not business-critical may get scraped. Additionally, running the foundry business is also turning out to be rather costly, with Q2 2024 recording a negative 65.5% operating margin. Separating Intel Product and Intel Foundry may be an option, or even selling the foundry business as a whole is on the table. Whatever happens next is yet to be cleared up. During the Deutsche Bank Technology Conference on Thursday, Pat Gelsinger also noted that "It's been a difficult few weeks" for Intel, with many employees getting laid off to try to establish new cost-saving measures.

Texas Instruments (TI) (Nasdaq: TXN) and the U.S. Department of Commerce have signed a non-binding Preliminary Memorandum of Terms for up to $1.6 billion in proposed direct funding under the CHIPS and Science Act to support three 300 mm wafer fabs already under construction in Texas and Utah. In addition, TI expects to receive an estimated $6 billion to $8 billion from the U.S. Department of Treasury's Investment Tax Credit for qualified U.S. manufacturing investments. The proposed direct funding, coupled with the investment tax credit, would help TI provide a geopolitically dependable supply of essential analog and embedded processing semiconductors.

"The historic CHIPS Act is enabling more semiconductor manufacturing capacity in the U.S., making the semiconductor ecosystem stronger and more resilient," said Haviv Ilan, president and CEO of Texas Instruments. "Our investments further strengthen our competitive advantage in manufacturing and technology as we expand our 300 mm manufacturing operations in the U.S. With plans to grow our internal manufacturing to more than 95% by 2030, we're building geopolitically dependable, 300 mm capacity at scale to provide the analog and embedded processing chips our customers will need for years to come."

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

Japanese professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has unveiled a revolutionary extreme ultraviolet (EUV) lithography technology that promises to significantly push down semiconductor manufacturing costs. The new technology tackles two previously insurmountable issues in EUV lithography. First, it introduces a streamlined optical projection system using only two mirrors, a dramatic simplification from the conventional six or more. Second, it employs a novel "dual line field" method to efficiently direct EUV light onto the photomask without obstructing the optical path. Prof. Shintake's design offers substantial advantages over current EUV lithography machines. It can operate with smaller EUV light sources, consuming less than one-tenth of the power required by conventional systems. This reduction in energy consumption also reduces operating expenses (OpEx), which are usually high in semiconductor manufacturing facilities.

The simplified two-mirror design also promises improved stability and maintainability. While traditional EUV systems often require over 1 megawatt of power, the OIST model can achieve comparable results with just 100 kilowatts. Despite its simplicity, the system maintains high contrast and reduces mask 3D effects, which is crucial for attaining nanometer-scale precision in semiconductor production. OIST has filed a patent application for this technology, with plans for practical implementation through demonstration experiments. The global EUV lithography market is projected to grow from $8.9 billion in 2024 to $17.4 billion by 2030, when most nodes are expected to use EUV scanners. In contrast, ASML's single EUV scanner can cost up to $380 million without OpEx, which is very high thanks to the power consumption of high-energy light UV light emitters. Regular EUV scanners also lose 40% of the UV light going to the next mirror, with only 1% of the starting light source reaching the silicon wafer. And that is while consuming over one megawatt of power. However, with the proposed low-cost EUV system, more than 10% of the energy makes it to the wafer, and the new system is expected to use less than 100 kilowatts of power while carrying a cost of less than 100 million, a third from ASML's flagship.

Intel Corporation today announced the appointment of Dr. Naga Chandrasekaran as chief global operations officer, executive vice president and general manager of Intel Foundry Manufacturing and Supply Chain organization. Chandrasekaran joins Intel from Micron, where he served as senior vice president for Technology Development. He will be a member of Intel's executive leadership team and report to CEO Pat Gelsinger.

Chandrasekaran succeeds Keyvan Esfarjani, who has decided to retire from Intel after nearly 30 years of dedicated service. Esfarjani's distinguished career set a strong foundation for Intel Foundry, and his leadership in global supply chain resilience and manufacturing excellence has helped to position Intel's business for long-term success. He will remain with Intel through the end of the year to ensure a seamless transition.

A recent report from Taiwan TV News has revealed that TSMC's overseas expansion plans will only contribute around 10% of the company's total silicon production capacity. TSMC's overseas expansion strategy has been a topic of significant interest in the tech industry as the company seeks to diversify its manufacturing capabilities beyond its home base in Taiwan. The company has announced plans to build new fabrication plants in the United States, Japan, and potentially other regions in an effort to mitigate supply chain risks and better serve its global customer base. However, according to the report, these overseas facilities will only account for a small fraction of 10% of TSMC's overall production capacity.

The majority of the company's manufacturing will continue to be centered in Taiwan, where it maintains its most advanced and high-volume fabs. There are also significant challenges and investments required to establish new semiconductor manufacturing facilities overseas. Building a state-of-the-art fab can cost billions of dollars and take several years to complete, making it a complex and capital-intensive undertaking. Despite the relatively small contribution of its overseas facilities, TSMC's global expansion is still seen as a crucial step in diversifying its supply chain and mitigating geopolitical risks. The company's ability to maintain its technological leadership and meet the growing demand for advanced chips will be crucial in the years to come.

To keep pace with unremitting growth in demand for chips, the global semiconductor manufacturing industry is expected to increase capacity by 6% in 2024 and post a 7% gain in 2025, reaching a record capacity high of 33.7 million wafers per month (wpm: 8-inch equivalent), SEMI announced today in its latest quarterly World Fab Forecast report.

Leading-edge capacity for 5 nm nodes and under is expected to grow 13% in 2024, chiefly driven by generative artificial intelligence (AI) for data center training, inference, and leading-edge devices. To increase processing power efficiency, chipmakers including Intel, Samsung, and TSMC are poised to start production of 2 nm Gate-All-Around (GAA) chips, boosting total leading-edge capacity growth by 17% in 2025.

Micron Technology, Inc., one of the world's largest semiconductor companies and the only U.S.-based manufacturer of memory, and the Biden-Harris Administration today announced that they have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York.

The CHIPS and Science Act grants of $6.1 billion will support Micron's plans to invest approximately $50 billion in gross capex for U.S. domestic leading-edge memory manufacturing through 2030. These grants and additional state and local incentives will support the construction of one leading-edge memory manufacturing fab to be co-located with the company's existing leading-edge R&D facility in Boise, Idaho and the construction of two leading-edge memory fabs in Clay, New York.

As a part of its Q1 earnings call discussion, one of the largest semiconductor manufacturers, TSMC, has unveiled a strategic move to charge a premium for chips manufactured at its newly established overseas fabrication plants. During an earnings call, TSMC's CEO, C.C. Wei, announced that the company will impose higher pricing for chips produced outside Taiwan to offset the higher operational costs associated with these international locations. This move aims to maintain TSMC's target gross margin of 53% amidst rising expenses such as inflation and elevated electricity costs. This decision comes as TSMC expands its global footprint with new facilities in the United States, Germany, and Japan (JAMS) to meet the increasing demand for semiconductor chips worldwide. The company's new US-based Arizona facility, known as Fab 21, has faced delays due to equipment installation issues and labor negotiations.

Chips produced at this site, utilizing TSMC's advanced N5 and N4 nodes, could cost between 20% to 30% more than those manufactured in Taiwan. TSMC's strategy to manage the cost disparities across different geographic locations involves strategic pricing, securing government support, and leveraging its manufacturing technology leadership. This approach reflects the company's commitment to maintaining its competitive edge while navigating the complexities of global semiconductor manufacturing in today's fragmented market. Introducing a location premium is expected to impact American semiconductor designers, who may need to pass these costs on to specific market segments, particularly those with lower price sensitivity, such as government-related projects. Despite these challenges, TSMC's overseas expansion underscores its adaptive strategies in the face of global economic pressures and industry demands, ensuring its continued position as a leading player in the semiconductor industry.

On March 29th, the United States announced another round of updates to its export controls, targeting advanced computing, supercomputers, semiconductor end-uses, and semiconductor manufacturing products. These new regulations, which took effect on April 4th, are designed to prevent certain countries and businesses from circumventing U.S. restrictions to access sensitive chip technologies and equipment. Despite these tighter controls, TrendForce believes the practical impact on the industry will be minimal.

The latest updates aim to refine the language and parameters of previous regulations, tightening the criteria for exports to Macau and D:5 countries (China, North Korea, Russia, Iran, etc.). They require a detailed examination of all technology products' Total Processing Performance (TPP) and Performance Density (PD). If a product exceeds certain computing power thresholds, it must undergo a case-by-case review. Nevertheless, a new provision, Advanced Computing Authorized (ACA), allows for specific exports and re-exports among selected countries, including the transshipment of particular products between Macau and D:5 countries.

At 07:58 local time, Taiwan was rocked by a magnitude 7.4 earthquake on the east coast which was felt nationwide and as far as to the southeastern parts of China and southern Japan. It caused some major damage in the east coast city of Hualien where the epicentre of the quake was located, as well as surrounding areas. The earthquake reportedly left nine people dead and over 900 people injured islandwide. TSMC, UMC, PSMC and Innolux all halted some of their production lines in the Hsinchu Science Park on the west coast of the island, although this is said to have been as a preventive step, rather than caused by actual damage from the earthquake.

All the above-mentioned companies also evacuated their staff from their factories due to the intensity of the quake, as it reached a magnitude of around four or five almost island wide. The semiconductor manufacturers are all inspecting their fabs now to make sure none of the equipment was damaged by the earthquake. Innolux also has a factory in the southern city of Kaohsiung and has reported that it has suspended production in Hsinchu, but that production in Kaohsiung wasn't affected. Local media in Taiwan hasn't made any mention of the likes of Micron or other chip manufacturers, but it's likely that the situation is similar, since all of these companies are located in the same areas on the island. Aftershocks have continued throughout the day and there's a risk for further big earthquakes to follow in the coming days.Images courtesy of the Taiwan Central Weather Administration (CWA).

Update 15:11 UTC: Updated with an official statement from Micron below.