On Feb. 28, 2025, Naga Chandrasekaran, executive vice president, chief global operations officer and general manager of Intel Foundry Manufacturing, sent a message to Intel employees in Ohio updating them on the latest planned construction completion dates for Ohio One Mod 1 and Mod 2 that are under construction in New Albany, Licking County, Ohio. I continue to be impressed by the progress you are driving on our Ohio One campus. We have come a long way since construction began, and I am grateful for all that you've accomplished to lay the groundwork for our future as we make Ohio one of the world's leading hubs of advanced semiconductor manufacturing.

Last quarter, we achieved our "go vertical" milestone when the "basement" level of the fab was completed - and work on the above-ground structure is now underway. The campus has been transformed in ways that bring Ohio's natural beauty to the site. You are also doing so much beyond our campus to support Ohioans in our neighborhood and across the state by creating education and workforce development initiatives, building local business partnerships, and volunteering and investing in the community. I am proud of the impact you are making.

Intel has unveiled some interesting advances in semiconductor manufacturing at the International Solid-State Circuits Conference (ISSCC), showcasing the capabilities of its highly anticipated Intel 18A process technology. The presentation highlighted significant improvements in SRAM bit cell density. The PowerVia system, coupled with RibbonFET (GAA) transistors, is at the heart of Intel's node. The company demonstrated solid progress with their high-performance SRAM cells, achieving a reduction from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A. High-density cells showed similar improvement, shrinking to 0.021 µm². These advancements represent scaling factors of 0.77 and 0.88 respectively, which are significant achievements in SRAM technology, once thought to be done with scaling benefits.

Implementing PowerVia technology is an Intel-first approach to addressing voltage drops and interference in processor logic areas. Using an "around the array" scheme, Intel strategically applies PowerVias to I/O, control, and decoder elements while optimizing bit cell design without a frontal power supply. The macro bit density of 38.1 MBit/mm² achieved by Intel 18A puts the company in a strong competitive position. While TSMC reported matching figures with their N2 process, Intel's comprehensive approach with 18A, combining PowerVia and GAA transistors, could challenge Smausng and TSMC, with long-term aspirations to compete for premium clients currently served by TSMC, including giants like NVIDIA, Apple, and AMD.

The global semiconductor manufacturing industry closed 2024 with strong fourth quarter results and solid year-on-year (YoY) growth across most of the key industry segments, SEMI announced today in its Q4 2024 publication of the Semiconductor Manufacturing Monitor (SMM) Report, prepared in partnership with TechInsights. The industry outlook is cautiously optimistic at the start of 2025 as seasonality and macroeconomic uncertainty may impede near-term growth despite momentum from strong investments related to AI applications.

After declining in the first half of 2024, electronics sales bounced back later in the year resulting in a 2% annual increase. Electronics sales grew 4% YoY in Q4 2024 and are expected to see a 1% YoY increase in Q1 2025 impacted by seasonality. Integrated circuit (IC) sales rose by 29% YoY in Q4 2024 and continued growth is expected in Q1 2025 with a 23% increase YoY as AI-fueled demand continues boosting shipments of high-performance computing (HPC) and datacenter memory chips.

IndiaTimes reports that Tata Projects announced on Tuesday that Micron Technology's semiconductor assembly and test facility at Sanand near Ahmedabad (India) will be ready by December 2025. Amit Agrawal, Project Director at Tata Projects, said workers have finished 60 percent of India's first semiconductor plant, the rest will be done by year's end. The plant covers about 50 acres in the Sanand industrial area and the building started in July last year. Tata Projects is putting up this semiconductor Assembly, Testing, Marking and Packaging (ATMP) facility for Micron.

"An ATMP facility is essentially a backend fab facility where testing, packaging and marking of semiconductors are carried out. This is perhaps the largest back-end semiconductor fab unit in the world. So far, 60 percent of work has been completed on Phase-1 with the help of a total workforce of 3,500," Agrawal told reporters. "We will hand over this facility to Micron by December 2025 after finishing civil work, mechanical, electrical and plumbing work along with engineering-related tasks as per the designs given by Micron. The final call to commence the plant will be taken by Micron" added Amit Agrawal, Project Director at Tata Projects.

In the early hours of Tuesday, a magnitude 6.4 earthquake struck near a remote mountainous region roughly 24 miles southeast of Chiayi in Taiwan, causing temporary operational halts at multiple TSMC facilities. The tremor occurred at 12:17 AM local time and was felt in Tainan, home to four of TSMC's manufacturing sites. Workers in both Central and Southern Taiwan were evacuated as a precaution, following standard company protocols designed to ensure employee safety. TSMC initiated thorough structural inspections immediately after the quake. According to company representatives, all crucial infrastructure, such as water supply and power systems, remained fully functional. With no significant damage detected during safety assessments, TSMC has gradually restarted its production lines, minimizing any long-term impact on its global client base.

Despite the relatively brief disruption, the incident exposes the fragility of the semiconductor manufacturing process. Taiwan's frequent seismic activity has the potential to affect the complex manufacturing processes crucial for producing silicon. Given the company's massive consumption of chemicals and silicon ingots, any significant production setbacks at TSMC can resonate through global supply chains. To reduce these geographical and nature-inspired risks, TSMC is investing heavily in new manufacturing facilities elsewhere, notably in Arizona. Although these sites are expected to enhance the company's resilience, they will only account for around 10% of TSMC's total production capacity. Additionally, as TSMC doesn't plan to bring state-of-the-art production to other sites, the company must implement safety features against earthquake protection in its Taiwan facilities to continue production. A minor manufacturing hiccup can equate to billions of losses across the supply chain.

Multiple sources say an unidentified corporation is exploring the complete acquisition of Intel Corporation, according to tech publication SemiAccurate. The report points to an internal memo shared among a small group of top executives at the unnamed firm. A high-level insider confirmed the memo's legitimacy last week, reinforcing speculation that a purchase of Intel may be under serious consideration. SemiAccurate's report indicates that the prospective buyer has enough financial resources to acquire Intel outright, considering the company's current market valuation. Notably, this potential buyer has not been publicly identified in previous discussions about Intel's future, suggesting that planning has occurred behind closed doors. The memo's limited circulation hints that executives treat the proposal cautiously rather than engaging in casual exploratory talks.

Any attempt to purchase Intel would require extensive regulatory review, given the company's role in producing semiconductors for both commercial and government applications. Regulators would likely evaluate issues related to national security, supply chain stability, and competitive impact in the global chip market. While neither Intel nor the unidentified acquirer has issued an official statement on the rumor, we are watching for any signals of formal negotiations. Intel has long been a strategic source of the US semiconductor sector, and its potential ownership change would have to be domestic. If a deal does materialize, it would stand among the largest transactions in the technology field.

Intel Foundry has announced the onboarding of new defense industrial base (DIB) customers, Trusted Semiconductor Solutions and Reliable MicroSystems, as part of the third phase of the Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) efforts under the Trusted & Assured Microelectronics (T&AM) Program in the Office of the Under Secretary of Defense for Research and Engineering (OUSD (R&E)). The RAMP-C project, awarded through the Strategic & Spectrum Missions Advanced Resilient Trusted Systems (S²MARTS) Other Transaction Authority (OTA), allows DIB customers to take advantage of Intel Foundry's leading-edge Intel 18A process technology and advanced packaging for prototypes and high-volume manufacturing of commercial and DIB products for the U.S. Department of Defense (DoD).

"We are very excited to welcome Trusted Semiconductor Solutions and Reliable MicroSystems to the RAMP-C project we are engaged in with the DoD. The collaboration will drive cutting-edge, secure semiconductor solutions essential for our nation's security, economic growth and technological leadership. We are proud of the pivotal role Intel Foundry plays in supporting U.S. national defense and look forward to working closely with our newest DIB customers to enable their innovations with our leading-edge Intel 18A technology," said Kapil Wadhera, vice president of Intel Foundry and general manager of Aerospace, Defense and Government Business Group.

Today, the U.S. Department of Commerce has announced that CHIPS National Advanced Packaging Manufacturing Program (NAPMP) has finalized $1.4 billion in award funding to bolster U.S. leadership in advanced packaging and enable new technologies to be validated and transitioned at scale to U.S. manufacturing. These awards will help establish a self-sustaining, high-volume, domestic, advanced packaging industry where advanced node chips are both manufactured and packaged in the United States.

These awards include:

• A total of $300 million under the CHIPS NAPMP's first Notice of Funding Opportunity (NOFO) for advanced substrates and material research to Absolics Inc., Applied Materials Inc., and Arizona State University. This follows the previously announced intent to enter negotiations on November 21, 2024
• $1.1 billion to Natcast to operate the advanced packaging capabilities of the CHIPS for America NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility (PPF). This follows the previously announced CHIPS R&D Facilities Model on July 12, 2024, and planned site selection for the PPF on January 6, 2025

TSMC's new semiconductor manufacturing facility in Phoenix, Arizona, will face production costs approximately 30% higher than its Taiwan-based operations when it begins mass production in early 2025. The increased expenses stem from higher tariffs and transportation costs associated with importing necessary materials from Taiwan. The Arizona facility will start producing 10,000 12-inch wafers monthly using a 4 nm node, with plans to double output to 20,000 wafers at full capacity. Four major technology companies—Apple, NVIDIA, AMD, and Qualcomm—have committed to purchasing chips from the plant for their AI and high-performance computing needs. The 445-hectare facility highlights ongoing challenges in America's semiconductor industry. Despite the aim to strengthen domestic chip manufacturing, the plant must import materials from Taiwan to maintain production quality, revealing gaps in the US semiconductor supply chain.

This overseas dependency drives up operational costs significantly. While TSMC's investment marks an essential step in rebuilding domestic capacity, the substantial cost difference between US and Taiwanese production raises questions about long-term viability. TSMC has already begun trial production at the site and plans to expand operations with additional phases. The company's Phase 2 facility is completed, and equipment is being installed, while future expansions aim to produce 2 nm chips by 2028. However, unless the cost gap narrows, the higher production expenses could impact the plant's competitiveness in the global semiconductor market, even competing with its own Taiwanese facilities, where customers could decide to use Taiwanese fabs due to lower costs. Meanwhile, TSMC continues to expand its Taiwan operations, with plans to build new 2 nm facilities in Kaohsiung's Science Park starting next year.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced the delivery and installation of ASML's EUV lithography equipment at its Innovative Integration for Manufacturing (IIM-1) foundry, an advanced semiconductor development and manufacturing fab currently under construction in Chitose, Hokkaido. To commemorate the installation, a ceremony was held at Portom Hall in the New Chitose Airport.

This is a significant milestone for Japan's semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. In addition to the EUV lithography machinery, Rapidus will install additional complementary advanced semiconductor manufacturing equipment, as well as full automated material handling systems in its IIM-1 foundry to optimize 2 nm generation gate-all-around (GAA) semiconductor manufacturing.

The U.S. Department of Commerce will award GlobalWafers America and MEMC, LLC, U.S. subsidiaries of Taiwan-based GlobalWafers Co., Ltd., up to $406 million in direct funding under the CHIPS Incentives Program's Funding Opportunity for Commercial Fabrication Facilities.

The award will support planned investments of $4 billion in advanced semiconductor wafer manufacturing facilities in Sherman, Texas and St. Peters, Missouri. The Department will disburse the funds based on GWA's and MEMC's completion of project milestones over a multi-year timeframe.

The pilot line for "Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems" (APECS) marks a major leap forward in strengthening Europe's semiconductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. By providing large industry players, SMEs, and start-ups with a facilitated access to cutting-edge technology, the APECS pilot line will establish a strong foundation for resilient and robust European semiconductor supply chains. Within APECS, the institutes collaborating in the Research Fab Microelectronics Germany (FMD) will work closely with European partners, to make a significant contribution to the European Union's goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the "Chips for Europe" initiative. The overall funding for APECS amounts to €730 million over 4.5 years.

Europe is home to a vibrant ecosystem of (hidden) champions, from traditional enterprises in vertical markets, to SMEs and start-ups the competitive advantages of which lie in superior semiconductor-based solutions. Nevertheless, many of these companies are currently confronted with limited access to advanced semiconductor technologies, while at the same time these technologies are increasingly becoming the most important factor for innovation and market growth.

Dai Nippon Printing Co., Ltd. (DNP) has successfully achieved the fine pattern resolution required for photomasks for logic semiconductors of the beyond 2 nm (nm: 10-9 meter) generation that support Extreme Ultra-Violet (EUV) lithography, a cutting-edge process in semiconductor manufacturing.

DNP has also completed the criteria evaluation for photomasks compatible with High-Numerical Aperture, the application being considered for next-generation semiconductors beyond the 2 nm generation, and has commenced the supply of evaluation photomasks. High-NA EUV lithography makes it possible to form fine patterns on silicon wafers with a higher resolution than previously possible, and is expected to lead to the realization of high-performance, low-power semiconductors.

Quobly, a leading French quantum computing startup, has reported that FD-SOI technology can serve as a scalable platform for commercial quantum computing, leveraging traditional semiconductor manufacturing fabs and CEA-Leti's R&D pilot line.

The semiconductor industry has played a pivotal role in enabling classical computers to scale at cost; it has the same transformative potential for quantum computers, making them commercially scalable and cost competitive. Silicon spin qubits are excellent for achieving fault-tolerant, large-scale quantum computing, registering clock speeds in the µsec range, fidelity above 99% for one and two-qubit gate operations and incomparably small unit cell sizes (in the hundredths of 100 nm²).

Global sales of total semiconductor manufacturing equipment by original equipment manufacturers (OEMs) are forecast to set a new industry record, reaching $113 billion in 2024, growing 6.5% year-on-year, SEMI announced today in its Year-End Total Semiconductor Equipment Forecast - OEM Perspective at SEMICON Japan 2024. Semiconductor manufacturing equipment growth is expected to continue in the following years, reaching new records of $121 billion in 2025 and $139 billion in 2026, supported by both the front-end and back-end segments.

"Three consecutive years of projected growth in investments in semiconductor manufacturing reflect the vital role our industry plays in underpinning the global economy and advancing technology innovation," said Ajit Manocha, SEMI president and CEO. "Since our July 2024 forecast, the outlook for 2024 semiconductor equipment sales has brightened, especially with stronger-than-expected investments from China and in AI-related sectors. Together with our forecast extension through 2026, it highlights the robust growth drivers across segments, applications, and regions."

A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

When Intel announced the completion of its $7.86 billion CHIPS Act grant from the Biden-Harris administration on Tuesday, we assumed some special terms were tied to the grant. Intel is essentially making a law-abiding promise to the US government that it will not sell its stake in the Intel Foundry unit under any circumstances, even if it manages to become an independent entity. This ensures that Intel is the major voting party in any event. Intel disclosed in a regulatory document that if Intel Foundry becomes its own private entity, Intel must maintain majority control with at least 50.1% ownership to keep its subsidy agreements. Additionally, if Intel Foundry goes public in the future, no single investor would be allowed to acquire more than 35% of shares unless Intel remains the largest shareholder, as this would trigger control-change clauses.

This essentially positions Intel Foundry as too big and too important of a unit to fail, both for Intel and the US government. Given Intel's ties with the US Department of Defense, with up to $3 billion in direct funding under the CHIPS and Science Act for the Secure Enclave program, Intel is vital for providing the US government with advanced semiconductor manufacturing. Strategically, Intel Foundry is the sole US-based company that competes with advanced manufacturing companies such as TSMC and Samsung. Even with TSMC and Samsung driving investments on US soil with advanced fabs, Intel's work with the government requires additional safety and secrecy clearances that only a US firm could provide. In the latest Q3 2024 financial results, Intel Foundry recorded a revenue of $4.4 billion with $5.8 billion in losses. While the operating marking of negative 134.3% seems like a disaster, upcoming quarters will bring it to a positive with more customers and using already developed nodes like 18A.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Intel's ambitious fab expansion plans, which are currently facing a temporary halt, are of significant importance. The German government, as reported by HardwareLuxx, is now considering redirecting €10 billion from the Climate and Transformation Fund (KTF) initially allocated to Intel, potentially returning these subsidies to the federal budget. The pause on Intel's investment to 2029-2030 (according to Tom's Hardware) not only threatens Germany's hopes of becoming one of semiconductor industry leaders but has also sparked debate over the intended use of this substantial financial support. Given the rise of geopolitical tensions, the urgency and significance of the German semiconductor industry in the current economic landscape cannot be overstated. The potential negative impact of the halt on Intel's investment is a cause for concern and engagement.

Finance Minister Christian Lindner has proposed that the funds be reallocated to address other economic needs, emphasizing fiscal responsibility amid current challenges. In contrast, Economic Affairs Minister Robert Habeck, whose department manages the KTF, opposes this reallocation, arguing that the fund should continue to support long-term economic growth and environmental initiatives. This disagreement between Lindner and Habeck illustrates the competing priorities within the government over the best use of public funds in uncertain economic times. The urgency of resolving this impasse is clear, as it will require navigating these tricky political waters while weighing the strategic importance of securing significant semiconductor investments in Germany. If Intel continues its Magdeburg expansion by the end of this decade, the terms for state subsidies might be changed. However, that is something to worry about in the distant future, as the blue giant has the priority of getting its financials back in line first.

Today, the Department of Commerce and Natcast, the operator of the National Semiconductor Technology Center (NSTC), announced the expected location for the first CHIPS for America research and development (R&D) flagship facility. The CHIPS for America Extreme Ultraviolet (EUV) Accelerator, an NSTC facility (EUV Accelerator), is expected to operate within NY CREATES' Albany NanoTech Complex in Albany, New York, supported by a proposed federal investment of an estimated $825 million. The EUV Accelerator will focus on advancing state of the art EUV technology and the R&D that relies on it.

As a key part of President Biden's Investing in America agenda, CHIPS for America is driven by the growing need to bolster the U.S. semiconductor supply chain, accelerate U.S. leading-edge R&D, and create good quality jobs around the country. This proposed facility will bring together NSTC members from across the ecosystem to accelerate semiconductor R&D and innovation by providing NSTC members access to technologies, capabilities, and critical resources.

After announcing the world's first 300-millimeter gallium nitride (GaN) power wafer and opening the world's largest 200-millimeter silicon carbide (SiC) power fab in Kulim, Malaysia, Infineon Technologies AG has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.

"The world's thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology," said Jochen Hanebeck, CEO at Infineon Technologies. "Infineon's breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry's innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN."

Nikon Corporation (Nikon) is developing a digital lithography system with resolution of one micron (L/S) and high productivity for advanced semiconductor packaging applications. This product is scheduled to be released in Nikon's fiscal year 2026.

The rapid adoption of artificial intelligence (AI) technology is driving demand for integrated circuits (ICs) for data centers. In the field of advanced packaging, including chiplets, the size of packages is increasing with the miniaturization of wiring patterns. This will lead to heightened demand for panel level packages that use glass and other materials suitable for larger packages, requiring exposure equipment that combines high resolution with a large exposure area. To meet these demands, Nikon is developing digital exposure equipment that combines the high-resolution technology of its semiconductor lithography systems, which has been cultivated over many decades, along with the excellent productivity made possible with the multi-lens technology of its FPD lithography systems.

After Apple, we just learned that AMD is the next company in line for US-based manufacturing in the TSMC Arizona facility. Industry analyst Tim Culpan reports that TSMC's Fab 21 in Arizona will soon be producing AMD's high-performance computing (HPC) processors, with tape out and manufacturing expected to commence on TSMC's 5 nm node next year. This move comes after previously reported Apple's A16 SoC production, which is already in progress at the facility and could see shipments before the end of this year, significantly ahead of the initially projected early 2025 schedule. The production of AMD's HPC chips in Arizona marks a crucial step towards establishing an AI-hardware supply chain operating entirely on American soil, which is expected to further expand with Intel Foundry and Samsung Texas facility.

Making HPC processors domestically serves as a significant milestone in reducing dependence on overseas semiconductor manufacturing and strengthening the US's position in the global chip industry. Adding to the momentum, TSMC and Amkor recently announced a collaboration on advanced packaging technologies, including Integrated Fan-Out (InFO) and Chip-on-Wafer-on-Substrate (CoWoS), which are vital for high-performance AI chips. However, as Amkor facilities are yet to be built, these chips are going to be shipped back to Taiwan for packaging before being integrated into the final product. Once the Amkor facility is up and running, Arizona will become the birthplace of fully manufactured and packaged silicon chips.

Samsung Electronics is grappling with significant challenges in its semiconductor division, particularly in its memory and foundry businesses. The company's top management, led by DS Division Vice Chairman Jeon Young-hyun, recently issued a public apology for the division's underwhelming performance. The tech giant's struggles are best seen in its advanced 3 nm Gate-All-Around (GAA) FET node, which reportedly yields only 10-20% of working silicon. This low yield rate has made potential customers hesitant to partner with Samsung, dealing a blow to its foundry business. Samsung Securities projects a 500 billion won (approximately $385 million) loss this year for Samsung Foundry and the LSI division combined. In the global foundry market, Samsung's position has weakened considerably. The company currently holds just 11.5% of the market share in Q2, while industry leader TSMC dominates with a commanding 62.3%. This disparity has led to speculation about the possible spinoff of Samsung Foundry, as the company reevaluates its strategy in the advanced semiconductor manufacturing sector.

Memory unit, one of Samsung's biggest assets, is slowly being one-upped by SK Hynix, which could overtake Samsung as the number one memory maker thanks to strong HBM demand. The management's apology acknowledges the concerns raised about the company's technological competitiveness and future prospects. Vice Chairman Jeon emphasized the need to restore fundamental competitiveness in technology and quality, which he described as the company's "lifeblood." Despite these challenges, Samsung's leadership remains optimistic about turning the crisis into an opportunity. They have pledged to focus on long-term solutions, invest in pioneering technologies, and foster a culture of innovation and open communication within the organization. As one of only three companies left in the advanced semiconductor manufacturing field, alongside TSMC and Intel, Samsung's ability to overcome these hurdles will be crucial not only for the company but for the entire industry.