Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced the delivery and installation of ASML's EUV lithography equipment at its Innovative Integration for Manufacturing (IIM-1) foundry, an advanced semiconductor development and manufacturing fab currently under construction in Chitose, Hokkaido. To commemorate the installation, a ceremony was held at Portom Hall in the New Chitose Airport.

This is a significant milestone for Japan's semiconductor industry, marking the first time that an EUV lithography tool will be used for mass production in the country. In addition to the EUV lithography machinery, Rapidus will install additional complementary advanced semiconductor manufacturing equipment, as well as full automated material handling systems in its IIM-1 foundry to optimize 2 nm generation gate-all-around (GAA) semiconductor manufacturing.

The U.S. Department of Commerce will award GlobalWafers America and MEMC, LLC, U.S. subsidiaries of Taiwan-based GlobalWafers Co., Ltd., up to $406 million in direct funding under the CHIPS Incentives Program's Funding Opportunity for Commercial Fabrication Facilities.

The award will support planned investments of $4 billion in advanced semiconductor wafer manufacturing facilities in Sherman, Texas and St. Peters, Missouri. The Department will disburse the funds based on GWA's and MEMC's completion of project milestones over a multi-year timeframe.

The pilot line for "Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems" (APECS) marks a major leap forward in strengthening Europe's semiconductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. By providing large industry players, SMEs, and start-ups with a facilitated access to cutting-edge technology, the APECS pilot line will establish a strong foundation for resilient and robust European semiconductor supply chains. Within APECS, the institutes collaborating in the Research Fab Microelectronics Germany (FMD) will work closely with European partners, to make a significant contribution to the European Union's goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the "Chips for Europe" initiative. The overall funding for APECS amounts to €730 million over 4.5 years.

Europe is home to a vibrant ecosystem of (hidden) champions, from traditional enterprises in vertical markets, to SMEs and start-ups the competitive advantages of which lie in superior semiconductor-based solutions. Nevertheless, many of these companies are currently confronted with limited access to advanced semiconductor technologies, while at the same time these technologies are increasingly becoming the most important factor for innovation and market growth.

Dai Nippon Printing Co., Ltd. (DNP) has successfully achieved the fine pattern resolution required for photomasks for logic semiconductors of the beyond 2 nm (nm: 10-9 meter) generation that support Extreme Ultra-Violet (EUV) lithography, a cutting-edge process in semiconductor manufacturing.

DNP has also completed the criteria evaluation for photomasks compatible with High-Numerical Aperture, the application being considered for next-generation semiconductors beyond the 2 nm generation, and has commenced the supply of evaluation photomasks. High-NA EUV lithography makes it possible to form fine patterns on silicon wafers with a higher resolution than previously possible, and is expected to lead to the realization of high-performance, low-power semiconductors.

Quobly, a leading French quantum computing startup, has reported that FD-SOI technology can serve as a scalable platform for commercial quantum computing, leveraging traditional semiconductor manufacturing fabs and CEA-Leti's R&D pilot line.

The semiconductor industry has played a pivotal role in enabling classical computers to scale at cost; it has the same transformative potential for quantum computers, making them commercially scalable and cost competitive. Silicon spin qubits are excellent for achieving fault-tolerant, large-scale quantum computing, registering clock speeds in the µsec range, fidelity above 99% for one and two-qubit gate operations and incomparably small unit cell sizes (in the hundredths of 100 nm²).

Global sales of total semiconductor manufacturing equipment by original equipment manufacturers (OEMs) are forecast to set a new industry record, reaching $113 billion in 2024, growing 6.5% year-on-year, SEMI announced today in its Year-End Total Semiconductor Equipment Forecast - OEM Perspective at SEMICON Japan 2024. Semiconductor manufacturing equipment growth is expected to continue in the following years, reaching new records of $121 billion in 2025 and $139 billion in 2026, supported by both the front-end and back-end segments.

"Three consecutive years of projected growth in investments in semiconductor manufacturing reflect the vital role our industry plays in underpinning the global economy and advancing technology innovation," said Ajit Manocha, SEMI president and CEO. "Since our July 2024 forecast, the outlook for 2024 semiconductor equipment sales has brightened, especially with stronger-than-expected investments from China and in AI-related sectors. Together with our forecast extension through 2026, it highlights the robust growth drivers across segments, applications, and regions."

A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

When Intel announced the completion of its $7.86 billion CHIPS Act grant from the Biden-Harris administration on Tuesday, we assumed some special terms were tied to the grant. Intel is essentially making a law-abiding promise to the US government that it will not sell its stake in the Intel Foundry unit under any circumstances, even if it manages to become an independent entity. This ensures that Intel is the major voting party in any event. Intel disclosed in a regulatory document that if Intel Foundry becomes its own private entity, Intel must maintain majority control with at least 50.1% ownership to keep its subsidy agreements. Additionally, if Intel Foundry goes public in the future, no single investor would be allowed to acquire more than 35% of shares unless Intel remains the largest shareholder, as this would trigger control-change clauses.

This essentially positions Intel Foundry as too big and too important of a unit to fail, both for Intel and the US government. Given Intel's ties with the US Department of Defense, with up to $3 billion in direct funding under the CHIPS and Science Act for the Secure Enclave program, Intel is vital for providing the US government with advanced semiconductor manufacturing. Strategically, Intel Foundry is the sole US-based company that competes with advanced manufacturing companies such as TSMC and Samsung. Even with TSMC and Samsung driving investments on US soil with advanced fabs, Intel's work with the government requires additional safety and secrecy clearances that only a US firm could provide. In the latest Q3 2024 financial results, Intel Foundry recorded a revenue of $4.4 billion with $5.8 billion in losses. While the operating marking of negative 134.3% seems like a disaster, upcoming quarters will bring it to a positive with more customers and using already developed nodes like 18A.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Intel's ambitious fab expansion plans, which are currently facing a temporary halt, are of significant importance. The German government, as reported by HardwareLuxx, is now considering redirecting €10 billion from the Climate and Transformation Fund (KTF) initially allocated to Intel, potentially returning these subsidies to the federal budget. The pause on Intel's investment to 2029-2030 (according to Tom's Hardware) not only threatens Germany's hopes of becoming one of semiconductor industry leaders but has also sparked debate over the intended use of this substantial financial support. Given the rise of geopolitical tensions, the urgency and significance of the German semiconductor industry in the current economic landscape cannot be overstated. The potential negative impact of the halt on Intel's investment is a cause for concern and engagement.

Finance Minister Christian Lindner has proposed that the funds be reallocated to address other economic needs, emphasizing fiscal responsibility amid current challenges. In contrast, Economic Affairs Minister Robert Habeck, whose department manages the KTF, opposes this reallocation, arguing that the fund should continue to support long-term economic growth and environmental initiatives. This disagreement between Lindner and Habeck illustrates the competing priorities within the government over the best use of public funds in uncertain economic times. The urgency of resolving this impasse is clear, as it will require navigating these tricky political waters while weighing the strategic importance of securing significant semiconductor investments in Germany. If Intel continues its Magdeburg expansion by the end of this decade, the terms for state subsidies might be changed. However, that is something to worry about in the distant future, as the blue giant has the priority of getting its financials back in line first.

Today, the Department of Commerce and Natcast, the operator of the National Semiconductor Technology Center (NSTC), announced the expected location for the first CHIPS for America research and development (R&D) flagship facility. The CHIPS for America Extreme Ultraviolet (EUV) Accelerator, an NSTC facility (EUV Accelerator), is expected to operate within NY CREATES' Albany NanoTech Complex in Albany, New York, supported by a proposed federal investment of an estimated $825 million. The EUV Accelerator will focus on advancing state of the art EUV technology and the R&D that relies on it.

As a key part of President Biden's Investing in America agenda, CHIPS for America is driven by the growing need to bolster the U.S. semiconductor supply chain, accelerate U.S. leading-edge R&D, and create good quality jobs around the country. This proposed facility will bring together NSTC members from across the ecosystem to accelerate semiconductor R&D and innovation by providing NSTC members access to technologies, capabilities, and critical resources.

After announcing the world's first 300-millimeter gallium nitride (GaN) power wafer and opening the world's largest 200-millimeter silicon carbide (SiC) power fab in Kulim, Malaysia, Infineon Technologies AG has unveiled the next milestone in semiconductor manufacturing technology. Infineon has reached a breakthrough in handling and processing the thinnest silicon power wafers ever manufactured, with a thickness of only 20 micrometers and a diameter of 300 millimeters, in a high-scale semiconductor fab. The ultra-thin silicon wafers are only a quarter as thick as a human hair and half as thick as current state-of-the-art wafers of 40-60 micrometers.

"The world's thinnest silicon wafer is proof of our dedication to deliver outstanding customer value by pushing the technical boundaries of power semiconductor technology," said Jochen Hanebeck, CEO at Infineon Technologies. "Infineon's breakthrough in ultra-thin wafer technology marks a significant step forward in energy-efficient power solutions and helps us leverage the full potential of the global trends decarbonization and digitalization. With this technological masterpiece, we are solidifying our position as the industry's innovation leader by mastering all three relevant semiconductor materials: Si, SiC and GaN."

Nikon Corporation (Nikon) is developing a digital lithography system with resolution of one micron (L/S) and high productivity for advanced semiconductor packaging applications. This product is scheduled to be released in Nikon's fiscal year 2026.

The rapid adoption of artificial intelligence (AI) technology is driving demand for integrated circuits (ICs) for data centers. In the field of advanced packaging, including chiplets, the size of packages is increasing with the miniaturization of wiring patterns. This will lead to heightened demand for panel level packages that use glass and other materials suitable for larger packages, requiring exposure equipment that combines high resolution with a large exposure area. To meet these demands, Nikon is developing digital exposure equipment that combines the high-resolution technology of its semiconductor lithography systems, which has been cultivated over many decades, along with the excellent productivity made possible with the multi-lens technology of its FPD lithography systems.

After Apple, we just learned that AMD is the next company in line for US-based manufacturing in the TSMC Arizona facility. Industry analyst Tim Culpan reports that TSMC's Fab 21 in Arizona will soon be producing AMD's high-performance computing (HPC) processors, with tape out and manufacturing expected to commence on TSMC's 5 nm node next year. This move comes after previously reported Apple's A16 SoC production, which is already in progress at the facility and could see shipments before the end of this year, significantly ahead of the initially projected early 2025 schedule. The production of AMD's HPC chips in Arizona marks a crucial step towards establishing an AI-hardware supply chain operating entirely on American soil, which is expected to further expand with Intel Foundry and Samsung Texas facility.

Making HPC processors domestically serves as a significant milestone in reducing dependence on overseas semiconductor manufacturing and strengthening the US's position in the global chip industry. Adding to the momentum, TSMC and Amkor recently announced a collaboration on advanced packaging technologies, including Integrated Fan-Out (InFO) and Chip-on-Wafer-on-Substrate (CoWoS), which are vital for high-performance AI chips. However, as Amkor facilities are yet to be built, these chips are going to be shipped back to Taiwan for packaging before being integrated into the final product. Once the Amkor facility is up and running, Arizona will become the birthplace of fully manufactured and packaged silicon chips.

Samsung Electronics is grappling with significant challenges in its semiconductor division, particularly in its memory and foundry businesses. The company's top management, led by DS Division Vice Chairman Jeon Young-hyun, recently issued a public apology for the division's underwhelming performance. The tech giant's struggles are best seen in its advanced 3 nm Gate-All-Around (GAA) FET node, which reportedly yields only 10-20% of working silicon. This low yield rate has made potential customers hesitant to partner with Samsung, dealing a blow to its foundry business. Samsung Securities projects a 500 billion won (approximately $385 million) loss this year for Samsung Foundry and the LSI division combined. In the global foundry market, Samsung's position has weakened considerably. The company currently holds just 11.5% of the market share in Q2, while industry leader TSMC dominates with a commanding 62.3%. This disparity has led to speculation about the possible spinoff of Samsung Foundry, as the company reevaluates its strategy in the advanced semiconductor manufacturing sector.

Memory unit, one of Samsung's biggest assets, is slowly being one-upped by SK Hynix, which could overtake Samsung as the number one memory maker thanks to strong HBM demand. The management's apology acknowledges the concerns raised about the company's technological competitiveness and future prospects. Vice Chairman Jeon emphasized the need to restore fundamental competitiveness in technology and quality, which he described as the company's "lifeblood." Despite these challenges, Samsung's leadership remains optimistic about turning the crisis into an opportunity. They have pledged to focus on long-term solutions, invest in pioneering technologies, and foster a culture of innovation and open communication within the organization. As one of only three companies left in the advanced semiconductor manufacturing field, alongside TSMC and Intel, Samsung's ability to overcome these hurdles will be crucial not only for the company but for the entire industry.

Amkor Technology, Inc. and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region's semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC's advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC's front-end fab and Amkor's back-end facility will accelerate overall product cycle times.

The grass isn't always greener on the other side, especially as we're running out of sides in the advanced semiconductor manufacturing sector. A recent report by Business Korea highlights Samsung Securities' July publication titled "Geopolitical Paradigm Shift and Industry," which paints a less-than-optimistic picture of Samsung's current state of affairs. The report even evaluates a possible spinoff of Samsung Foundry. The Korean tech giant has faced various business setbacks related to its state-of-the-art 3 nm Gate-All-Around (GAA) FET node. Reports indicate that this node only manages to yield 10-20% of working silicon, making potential customers reluctant to secure partnerships with Samsung. Samsung Securities projects that Samsung Foundry, along with the LSI division, will suffer a 500 billion won (about $385 million) loss this year.

Poor yields and difficulty securing customers have left Samsung facing tough choices, including the possible sale of its massive Foundry unit, which manufactures logic for external customers. It's noteworthy that Samsung is one of only three companies left in the advanced semiconductor manufacturing field, alongside TSMC and Intel. Many companies struggled to deliver results when transitioning to sub-7 nm nodes. Global Foundries dropped out of the race to focus on mature nodes, while Intel faced delays. TSMC has been the only company so far to consistently set and execute its goals, positioning itself as the industry leader. With low yields on the 3 nm GAA FET node, Samsung currently holds 11.5% of the global foundry market share in Q2, while TSMC dominates with 62.3%.

Canon Inc. announced today that it will ship its most advanced lithography platform, the FPA-1200NZ2C nanoimprint lithography (NIL) system for semiconductor manufacturing, to the Texas Institute for Electronics (TIE), a Texas-based semiconductor consortium. Canon became the first in the world to commercialize a semiconductor manufacturing system that uses NIL technology, which forms circuit patterns in a different method from conventional projection exposure technology, when it released the FPA-1200NZ2C on October 13, 2023.

In contrast to conventional photolithography equipment, which transfers a circuit pattern by projecting it onto the resist coated wafer, the new product does it by pressing a mask imprinted with the circuit pattern into the resist on the wafer like a stamp. Because its circuit pattern transfer process does not go through an optical mechanism, fine circuit patterns on the mask can be faithfully reproduced on the wafer. With reduced power consumption and cost, the new system enables patterning with a minimum linewidth of 14 nm, equivalent to the 5 nm node that is required to produce most advanced logic semiconductors currently available.

Intel's recent financial woes have brought the company into severe cost-cutting measures, including job cuts and project delays. However, a silver lining remains—Intel is reportedly in the final stages of securing $8.5 billion in direct funding from the US government under the CHIPS Act, delivered by the end of the year. The potential financing comes at a crucial time for Intel, which has been grappling with financial challenges. The company reported a $1.6 billion loss in the second quarter of 2024, leading to short-term setbacks. However, thanks to sources close to the Financial Times, we learn that Intel's funding target will represent the CHIPS Act's largest share, leading to a massive boost to US-based semiconductor manufacturing.

Looking ahead, the potential CHIPS Act funding could serve as a catalyst for Intel's resurgence, reassuring both investors and customers about the company's future. A key element of Intel's recovery strategy lies in the ramp-up of production for its advanced 18A node, which should become the primary revenue driver for its foundry unit. This advancement, coupled with the anticipated government backing, positions Intel to potentially capture market share from established players like TSMC and Samsung. The company has already secured high-profile customers such as Amazon and (allegedly) Broadcom, hinting at its growing appeal in the foundry space. Moreover, Intel's enhanced domestic manufacturing capabilities align well with potential US government mandates for companies like NVIDIA and Apple to produce processors locally, a consideration driven by escalating geopolitical tensions.

TSMC and Samsung are reportedly in talks with the United Arab Emirates (UAE) to establish chip factories in the Gulf nation. As reported by the Wall Street Journal, this "desert dream" aligns with the UAE's ambitious plans to diversify its economy beyond oil and become a key player in the AI sector by building chips for AI domestically. The UAE and neighboring Saudi Arabia plan to leverage their oil wealth to invest in cutting-edge manufacturing, with AI emerging as a primary focus due to its high computational demands. Successful implementation of chip factories could significantly boost the region's AI capabilities and impact the global semiconductor supply chain. However, the project faces substantial challenges. Previous attempts to establish semiconductor manufacturing in the Gulf, such as the GlobalFoundries initiative over a decade ago, have yet to progress beyond initial planning.

The current proposal faces even greater obstacles, with estimated costs exceeding $100 billion for a state-of-the-art facility and necessary infrastructure. Geopolitical concerns add another layer of complexity. Recent US export restrictions of certain chips to the Gulf region may complicate the transfer of advanced manufacturing processes to the UAE. Despite these hurdles, the potential benefits are significant. For the UAE, success would represent a major step towards economic diversification and technological leadership. TSMC and Samsung could gain a strategic presence in a region eager for technological advancement. TSMC noted that the company focuses on current expansion projects in the US, Japan, and Germany, while Samsung declined to comment.

The Biden-Harris Administration announced today that Intel Corporation has been awarded up to $3 billion in direct funding under the CHIPS and Science Act for the Secure Enclave program. The program is designed to expand the trusted manufacturing of leading-edge semiconductors for the U.S. government.

The Secure Enclave program builds on previous projects between Intel and the Department of Defense (DoD) such as Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP). As the only American company that both designs and manufactures leading-edge logic chips, Intel will help secure the domestic chip supply chain and collaborate with the DoD to help enhance the resilience of U.S. technological systems by advancing secure, cutting-edge solutions.

Samsung's foundry plans have again hit a major setback. The company notified staff at its Taylor, Texas facility that it was temporarily removing workers from the site because it is still experiencing challenges with 2 nm semiconductor yields, delaying mass production timelines from late 2024 to 2026. The Taylor site had been anticipated as the flagship facility for Samsung's sub-4 nm production, allowing access to potential customers near the facility. While Samsung has moved rapidly in terms of process development, its yields for advanced nodes have outstripped them, the company's yields for sub-3 nm processes hover around 50%, with Gate-All-Around (GAA) technology witnessing yields of only 10-20%, significantly lower than neighboring competitor TSMC's 60-70% for corresponding nodes.

The yield gaps that the company is experiencing have exacerbated the gap in market share, with TSMC capturing 62.3% of the global foundry market share in Q2 versus Samsung's 11.5%. The company is struggling to gain share despite efforts by Chairman Lee Jae-yong - including visits to component suppliers ASML, and Zeiss - and these yields put at risk as much as 9 trillion won in U.S. CHIP Act potential subsidies that are dependent upon operational milestones.

According to a recent report from Bloomberg, Intel is in talks with investment banks about a possible spin-out of its foundry business, as well as scraping some existing expansion plans to cut losses. As the report highlights, sources close to Intel noted that the company is exploring various ways to deal with the recent Q2 2024 earnings report. While Intel's revenues are in decline, they are still high. However, the profitability of running its business has declined so much that the company is now operating on a net loss, with an astonishing $1.61 billion in the red. CEO Pat Gelsinger is now exploring various ways to control these losses and make the 56-year-old giant profitable again. Goldman Sachs and Morgan Stanley are reportedly advising Intel about its future moves regarding the foundry business and overall operations.

The Intel Foundry unit represents the biggest consumer of the company's funds, as the expansion plans across the US and Europe are costing Intel billions of US Dollars. Even though the company receives various state subsidies to build semiconductor manufacturing facilities, it still has to put much of its capital to work. Given that the company is running tight on funds, some of these expansion plans that are not business-critical may get scraped. Additionally, running the foundry business is also turning out to be rather costly, with Q2 2024 recording a negative 65.5% operating margin. Separating Intel Product and Intel Foundry may be an option, or even selling the foundry business as a whole is on the table. Whatever happens next is yet to be cleared up. During the Deutsche Bank Technology Conference on Thursday, Pat Gelsinger also noted that "It's been a difficult few weeks" for Intel, with many employees getting laid off to try to establish new cost-saving measures.

Texas Instruments (TI) (Nasdaq: TXN) and the U.S. Department of Commerce have signed a non-binding Preliminary Memorandum of Terms for up to $1.6 billion in proposed direct funding under the CHIPS and Science Act to support three 300 mm wafer fabs already under construction in Texas and Utah. In addition, TI expects to receive an estimated $6 billion to $8 billion from the U.S. Department of Treasury's Investment Tax Credit for qualified U.S. manufacturing investments. The proposed direct funding, coupled with the investment tax credit, would help TI provide a geopolitically dependable supply of essential analog and embedded processing semiconductors.

"The historic CHIPS Act is enabling more semiconductor manufacturing capacity in the U.S., making the semiconductor ecosystem stronger and more resilient," said Haviv Ilan, president and CEO of Texas Instruments. "Our investments further strengthen our competitive advantage in manufacturing and technology as we expand our 300 mm manufacturing operations in the U.S. With plans to grow our internal manufacturing to more than 95% by 2030, we're building geopolitically dependable, 300 mm capacity at scale to provide the analog and embedded processing chips our customers will need for years to come."