"Navi 4C" is a future high-end GPU from AMD that will likely not see the light of day, as the company is pivoting away from the high-end GPU segment with its next RDNA4 generation. For AMD to continue investing in the development of this GPU, the gaming graphics card segment should have posted better sales, especially in the high-end, which it didn't. Moore's Law is Dead scored details of what could have been a fascinating technological endeavor for AMD, in building a highly disaggregated GPU.

AMD's current "Navi 31" GPU sees a disaggregation of the main logic components of the GPU that benefit from the latest 5 nm foundry node to be located in a central Graphics Compute Die; surrounded by up to six little chiplets built on the older 6 nm foundry node, which contain segments of the GPU's Infinity Cache memory, and its memory interface—hence the name memory cache die. With "Navi 4C," AMD had intended to further disaggregate the GPU, identifying even more components on the GCD that can be spun out into chiplets; as well as breaking up the shader engines themselves into smaller self-contained chiplets (smaller dies == greater yields and lower foundry costs).

Phison Electronics, a global leader in NAND flash and storage solutions, announces a technology demonstration of unique customer-based solutions fully realized through the IMAGIN+ customization service at Flash Memory Summit 2023.

Phison has expanded its IMAGIN+ design service to include AI computational models and AI services solutions. Customers work with specialized Phison teams to design and engineer custom flash deployments that precisely address the data performance and endurance requirements of next generation products including those highly optimized for aiDAPTIV AI+ML workloads. With IMAGIN+ design services, Phison teams work hand-in-hand with customers to deliver AI-boosted SSD solutions that address demanding requirements.

TSMC (TWSE: 2330, NYSE: TSM), Robert Bosch GmbH, Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY), and NXP Semiconductors N.V. (NASDAQ: NXPI) today announced a plan to jointly invest in European Semiconductor Manufacturing Company (ESMC) GmbH, in Dresden, Germany to provide advanced semiconductor manufacturing services. ESMC marks a significant step towards construction of a 300 mm fab to support the future capacity needs of the fast-growing automotive and industrial sectors, with the final investment decision pending confirmation of the level of public funding for this project. The project is planned under the framework of the European Chips Act.

The planned fab is expected to have a monthly production capacity of 40,000 300 mm (12-inch) wafers on TSMC's 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology, further strengthening Europe's semiconductor manufacturing ecosystem with advanced FinFET transistor technology and creating about 2,000 direct high-tech professional jobs. ESMC aims to begin construction of the fab in the second half of 2024 with production targeted to begin by the end of 2027.

The escalating challenges in acquiring high-performance x86 servers have prompted Chinese data center companies to accelerate the shift to Arm-based system-on-chips (SoCs). Investment banking firm Bernstein reports that approximately 40% of all Arm-powered servers globally are currently being used in China. While most servers operate on x86 processors from AMD and Intel, there's a growing preference for Arm-based SoCs, especially in the Chinese market. Several global tech giants, including AWS, Ampere, Google, Fujitsu, Microsoft, and Nvidia, have already adopted or developed Arm-powered SoCs. However, Arm-based SoCs are increasingly favorable for Chinese firms, given the difficulty in consistently sourcing Intel's Xeon or AMD's EPYC. Chinese companies like Alibaba, Huawei, and Phytium are pioneering the development of these Arm-based SoCs for client and data center processors.

However, the US government's restrictions present some challenges. Both Huawei and Phytium, blacklisted by the US, cannot access TSMC's cutting-edge process technologies, limiting their ability to produce competitive processors. Although Alibaba's T-Head can leverage TSMC's latest innovations, it can't license Arm's high-performance computing Neoverse V-series CPU cores due to various export control rules. Despite these challenges, many chip designers are considering alternatives such as RISC-V, an unrestricted, rapidly evolving open-source instruction set architecture (ISA) suitable for designing highly customized general-purpose cores for specific workloads. Still, with the backing of influential firms like AWS, Google, Nvidia, Microsoft, Qualcomm, and Samsung, the Armv8 and Armv9 instruction set architectures continue to hold an edge over RISC-V. These companies' support ensures that the software ecosystem remains compatible with their CPUs, which will likely continue to drive the adoption of Arm in the data center space.

Without fanfare, Intel has launched two new mobile GPUs in the shape of the Arc A570M and the A530M. The Arc A570M gets 16 Xe Cores and 256 execution units, as well as four render slices and 16 RT units. The lower-end Arc A530M gets to make do with 12 Xe cores, 192 execution units, three render slices and 12 RT units, which is a smaller cut than the model name suggests. What's interesting to note here is that the Arc A570M appears to have identical hardware specs to the Arc A550M that launched in the second quarter of 2022, although as we'll see, the clock speeds and TGP differ between the parts. The Arc A570M supports 8 GB of GDDR6 memory, the same as the Arc A550M, with the Arc A530M supports 4 or 8 GB of GDDR6.

Both the Arc A570M and the A530M will get a GPU clock speed of 1,300 MHz, which is a significant boost from the Arc A550M which is plodding along at a mere 900 MHz in comparison. This makes the two newcomers Intel's third highest clocked mobile GPUs, with only the Arc A770M and Arc A370M being clocked higher. The downside of this is an increase in TGP, where the Arc A550M had a fairly reasonable TGP of 60 Watts, the Arc A530M has a TGP range of 65 to 95 Watts, while the Arc A570M extends this to 75-95 Watts. The rest of the specs appear to carry over from the Arc A550M, so the new GPUs will support up to four displays via eDP, DP 2.0 or HDMI 2.1 and the full set of video encoders and decoders are also supported. The new additions are still made using TSMC's N6 node, so what we're looking at are most likely just optimised silicon here, which has led Intel to be able to boost the clock speeds while maintaining acceptable thermals.

TSMC today held an inauguration ceremony for its global Research and Development Center in Hsinchu, Taiwan, celebrating the Company's newest hub for bringing the next generations of semiconductor technology into reality with customers, R&D partners in industry and academia, design ecosystem partners, and senior government leaders.

The R&D Center will serve as the new home for TSMC's R&D Organization, including the researchers who will develop TSMC's leading-edge process technology at the 2-nanometer generation and beyond, as well as scientists and scholars blazing the trail with exploratory research into fields such as novel materials and transistor structures. With R&D employees already relocating to their workplaces in the new building, it will be ready for its full complement of more than 7,000 staff by September 2023.

Stan Shih, the co-founder & honorary chairman of Acer Inc., thinks that the USA will have hard time catching up with Asian semiconductor production facilities. Yahoo Taiwan managed to extract some choice comments from the multi-faceted businessman—he believes that the US government's initiative to boost native chip making will not be enough to match existing overseas strongholds. A key area of focus was volume output—Shih reckons that North America is already too far behind Asian counterpart industries, with Acer's home base of Taiwan being particularly strong (in his opinion). Workplace culture and state of the art equipment are cited as the main pillars for success.

Shih observed that that US chip industry has historically been far too reliant on outsourcing (going back many decades) production to foreign facilities, and Asia's position has been fortified thanks to long established and optimized supply chains—he thinks that the American system is not mature enough to reach parity. On a semi-related note, TSMC is reportedly struggling to get its new US facility fully operational—company chairman Mark Liu (according to Tom's Hardware): "said that the Taiwanese company would delay mass production of its Arizona fab from early 2024 to 2025, partly due to a lack of cleanroom tools necessary to produce chips at scale." TSMC has been transferring staff from its home turf to plug staffing gaps at the Phoenix facility—Liu divulged his latest batch of complaints during an earnings conference (last Thursday): "We are encountering certain challenges, as there is an insufficient number of skilled workers with the specialized expertise required for equipment installation in a semiconductor-grade facility."

Micron Technology, Inc. today announced it has begun sampling the industry's first 8-high 24 GB HBM3 Gen2 memory with bandwidth greater than 1.2 TB/s and pin speed over 9.2 Gb/s, which is up to a 50% improvement over currently shipping HBM3 solutions. With a 2.5 times performance per watt improvement over previous generations, Micron's HBM3 Gen2 offering sets new records for the critical artificial intelligence (AI) data center metrics of performance, capacity and power efficiency. These Micron improvements reduce training times of large language models like GPT-4 and beyond, deliver efficient infrastructure use for AI inference and provide superior total cost of ownership (TCO).

The foundation of Micron's high-bandwidth memory (HBM) solution is Micron's industry-leading 1β (1-beta) DRAM process node, which allows a 24Gb DRAM die to be assembled into an 8-high cube within an industry-standard package dimension. Moreover, Micron's 12-high stack with 36 GB capacity will begin sampling in the first quarter of calendar 2024. Micron provides 50% more capacity for a given stack height compared to existing competitive solutions. Micron's HBM3 Gen2 performance-to-power ratio and pin speed improvements are critical for managing the extreme power demands of today's AI data centers. The improved power efficiency is possible because of Micron advancements such as doubling of the through-silicon vias (TSVs) over competitive HBM3 offerings, thermal impedance reduction through a five-time increase in metal density, and an energy-efficient data path design.

According to a report published by Bloomberg, the German government has formed plans to create €20 billion ($22 billion) of investments to aid in the growth of local semiconductor manufacturing. The article proposes that the organization is racing to bolster the country's technology sector, and is attempting to secure essential supplies of components. Various geopolitical issues have complicated matters in recent times. Funding will be made available to German and international companies, from Germany's (now diversified) Climate and Transformation reserve, over the next four years. The finance ministry responded to Bloomberg's query, and stated: "The draft for the economic plan 2024 and the financial plan until 2027 for the Climate and Transformation Fund are currently being prepared...This process has not yet been completed." Germany's economy ministry did not provide a statement/response to Bloomberg's queries.

Around 75% of the fund is reportedly set aside for multinational semiconductor firms including Intel Corporation (USA) and Taiwan Semiconductor Manufacturing Company Limited (TSMC). Bloomberg believes that Team Blue is due an allocation of €10 billion for investments in its new production facility, located close to Magdeburg, Germany. The government is allegedly deep into talks with TSMC regarding the foundation of a proposed €10 billion production base in the Dresden area—the likes of BMW, Mercedes-Benz and Volkswagen AG would benefit greatly with quicker access to (localized) microcontrollers manufacturing facilities. The government could subsidize half of that total investment (€5 billion). Infineon is possibly in line to receive a €1 billion aid package, since it is building a new fab location in Dresden.

According to news out of Korea, NVIDIA is considering Samsung as a partner not only for HBM3 memory, but also as a potential partner when it comes to 2.5D chip packaging. The latter is due to TSMC having limited capacity when it comes to handling all of its customers advanced chip packaging needs, although Samsung is apparently not the only potential partner NVIDIA is looking at. Taiwan based SPIL and US based Amkor Technology are two alternative candidates for the 2.5D chip packaging according to the Elec.

As far as HBM3 memory goes, NVIDIA doesn't have as many potential options, with SK Hynix being its current partner, who NVIDIA will continue to work with when it comes to HBM memory for its high-end AI accelerators and GPUs. It's likely that Samsung is trying to win NVIDIA back as a foundry customer, by proving that it's capable of handling the chip packaging for NVIDIA. Samsung will likely use its I-Cube 2.5D packaging technology and the Elec suggests that Samsung would still be using TSMC made GPU wafers which will be mated with Samsung HMB3 memory. Samsung has as yet not started its mass production of HMB3 memory, but have sampled customers with evaluation samples that are said to have received very positive feedback. For now, nothing has been agreed and TSMC is, as we know, looking to expand its 2.5D packaging business by over 40 percent, but the question is how quickly TSMC can move before its customers consider other competitors.

Competition between Samsung and TSMC in the 4 nm and 3 nm foundry process markets is about to heat up, with the Korean foundry claiming yields competitive to those of TSMC, according to a report in the Kukmin Ilbo, a Korean daily newspaper. 4 nm is the final silicon fabrication process to use the FinFET technology that powered nodes ranging between 16 nm to 4 nm. Samsung Foundry is claiming 4 nm wafer yields of 75%, against the 80% yields figure put out by TSMC. 4 nm powers several current-generation mobile SoCs, PC processors, and more importantly, the GPUs driving the AI gold-rush.

Things get very interesting with 3 nm, the node that debuts GAA-FET (gates all around FET) technology. Here, Samsung claims to offer higher yields than TSMC, with its 3 nm GAA node clocking 60% yields, against 55% put out by TSMC. Samsung was recently bitten by a scandal where its engineers allegedly falsified yields figures to customers to score orders, which had a cascading effect on the volumes and competitiveness of their customers. We're inclined to think that Samsung has taken lessons and is more careful with the yields figures being reported in the press. Meanwhile, Intel Foundry Services competes with the Intel 3 node, which is physically 7 nm FinFET, but with electrical characteristics comparable to those of 3 nm.

China announced on Monday (June 3) that it would restrict exports of two rare metals——both crucial materials in the computer chip manufacturing process. The nation's Ministry of Commerce stated that their new measures were necessary to "safeguard national security and interests". The Chinese government is contending with several sanctions from Western countries—most notably their access to advanced semiconductor manufacturing equipment is now heavily controlled. Reuters has contacted a number of foundries about the potential impact of rare material shipment limitations. Taiwan Semiconductor Manufacturing Company (TSMC) has shrugged it off as a minor inconvenience, their spokesperson stated: "After evaluation, we do not expect the export restrictions on raw materials gallium and germanium will have any direct impact on TSMC's production. We will continue to monitor the situation closely."

WIN Semiconductors Corp—a Taiwanese firm that specializes in the provision of gallium arsenide wafers—informed the news agency about its low-level reliance on Chinese mineral sources. They are able to sidestep and procure gallium and germanium from suppliers located in Germany, Japan, and North America. The Japanese Semiconductor Equipment Association stated that it was too early to tell whether China's export restrictions will result in material shortages. Supply chains could be disrupted to some degree due to China controlling over 90% of the world's gallium and germanium production, but DigiTimes Asia proposes that new sanctions will not prohibit production and export activities. According to experts in the field supply lines will continue to operate, with buyers required to jump through some extra hoops in order to gain approval for certain market segments. The purification of gallium and germanium is mostly controlled by American and Japanese entities—the processed form of these metals is used in semiconductor production—DigiTimes reckons that these firms will probably feel the initial impact of new trade restrictions.

The Financial Times believes that Apple is running into major production issues related to its Vision Pro mixed reality headset—insider sources claim that the mega-sized multinational technology company is adjusting internal sales goals for the $3499 AR/VR "spatial computer." Leadership had set an ambitious internal target of 1 million units sold in 2024, but the complexity of the system's design has apparently caused major setbacks for manufacturing partners. Apple is reported to have signed up with Luxshare, a Chinese contract manufacturer, to assemble Vision Pro headsets—insiders within both organizations reckon that only 400,000 units will be ready for sale throughout 2024. This number seems to be fairly optimistic given that Trendforce predicted that a mere 200,000 would be shipped next year.

FT gathered information from two other sources placed within the Chinese supply chain—they claim that Apple and Luxshare could encounter major component shortages in 2024, resulting in a production shortfall—with an estimated 130,000 to 150,000 finalized units. The article points out that the most complex (and costly) aspect of the headset lies in its micro-OLED display setup, that also includes outward facing lenses. TSMC and Sony are reported to be the suppliers of these parts (as featured on the prototypes), but Apple is allegedly not satisfied with low production numbers, and not enough batches are "free of defects." A cheaper version of the Vision Pro is apparently now on the backburner, since Apple is unlikely to recoup—factoring in R&D expenses—within the first year of the intial product's launch.

According to Taiwanese media, TSMC will start production of its first 1.4 nm fab in 2026, with chip production in the fab said to start sometime in 2027 or 2028. The new fab will be located in Longtan Science Park outside of Hsinchu in Taiwan, where many of TSMC's current fabs are located. TSMC is currently constructing a 2 nm and below node R&D facility at a nearby plot of land to where the new fab is expected to be built. This facility is expected to be finished in 2025 and TSMC has been allocated a total area of just over 158 hectares of land for future expansion in the area.

In related news, TSMC is expected to be charging US$25,000 per 2 nm GAA wafer, which is an increase of about a fifth compared to its 3 nm wafers which are going for around US$20,000. This is largely due to the nodes being fully booked and TSMC being able to charge a premium for its cutting edge nodes. TSMC is also expanding in CoWoS packaging facilities due to increased demand from both AMD and NVIDIA for AI related products. Currently TSMC is said to be able to output 12,000 CoWoS wafers per month and this is twice as much as last year, yet TSMC is unable to meet demand from its customers.

TrendForce reports that explosive growth in generative AI applications like chatbots has spurred significant expansion in AI server development in 2023. Major CSPs including Microsoft, Google, AWS, as well as Chinese enterprises like Baidu and ByteDance, have invested heavily in high-end AI servers to continuously train and optimize their AI models. This reliance on high-end AI servers necessitates the use of high-end AI chips, which in turn will not only drive up demand for HBM during 2023~2024, but is also expected to boost growth in advanced packaging capacity by 30~40% in 2024.

TrendForce highlights that to augment the computational efficiency of AI servers and enhance memory transmission bandwidth, leading AI chip makers such as Nvidia, AMD, and Intel have opted to incorporate HBM. Presently, Nvidia's A100 and H100 chips each boast up to 80 GB of HBM2e and HBM3. In its latest integrated CPU and GPU, the Grace Hopper Superchip, Nvidia expanded a single chip's HBM capacity by 20%, hitting a mark of 96 GB. AMD's MI300 also uses HBM3, with the MI300A capacity remaining at 128 GB like its predecessor, while the more advanced MI300X has ramped up to 192 GB, marking a 50% increase. Google is expected to broaden its partnership with Broadcom in late 2023 to produce the AISC AI accelerator chip TPU, which will also incorporate HBM memory, in order to extend AI infrastructure.

AMD on Tuesday (June 13) launched the EPYC 9004 "Bergamo" 128-core/256-thread high density compute server processor, and with it, debuted the new "Zen 4c" CPU microarchitecture. A lot had been made out about Zen 4c in the run up to yesterday's launch, such as rumors that it is a Zen 4 "lite" core that has lesser number-crunching muscle, and hence lower IPC, and that Zen 4c is AMD's answer to Intel's E-core architectures, such as "Gracemont" and "Crestmont." It turns out that it's neither a lite version of Zen 4, nor is it an E-core, but a physically compacted version of the Zen 4 core, with identical number crunching machinery.

First things first—Zen 4c has the same exact IPC as Zen 4 (that's performance at a given clock-speed). This is because its front-end, execution stage, load/store component, and internal cache hierarchy is exactly the same. It has the same 88-deep load queue, 64-deep store queue, the same 675,000 µop cache, the exact same INT+FP issue width of 10+6, the same exact INT register file, the same scheduler, and cache latencies. The L1I and L1D caches are the same 32 KB in size as "Zen 4," and so is the dedicated L2 cache, at 1 MB.

TrendForce reports that the global top 10 foundries witnessed a significant 18.6% QoQ decline in revenue during the first quarter of 2023. This decline—amounting to approximately US$27.3 billion—can be attributed to sustained weak end-market demand and the compounded effects of the off-peak season. The rankings also underwent notable changes, with GlobalFoundries surpassing UMC to secure the third position, and Tower Semiconductor surpassing PSMC and VIS to claim the seventh spot.

Declining capacity utilization rate and shipment volume contribute to widened revenue decline
The revenue decline in Q1 was primarily influenced by declining capacity utilization rates and shipment volume across the top 10 foundries. For instance, TSMC generated US$16.74 billion in revenue—marking a 16.2% QoQ drop in revenue. Weakened demand for mainstream applications such as laptops and smartphones led to a significant decline in the utilization rates and revenue of the 7/6 nm and 5/4 nm processes, falling over 20% and 17%, respectively. While the second quarter may see temporary relief coming from rush orders, the persistently low capacity utilization rate indicates that revenue is likely to continue declining, albeit at a slower pace compared to Q1.

The United States government has imposed sanctions on companies exporting their goods to China with the aim of limiting the country's technological advancements. This forced many companies to reduce their shipments of the latest technologies; however, according to the latest information from The Wall Street Journal, the Biden administration will allow companies to keep expanding their production capacities in China. As the source notes, quoting statements from government officials, the top semiconductor makers such as Samsung, SK Hynix, and TSMC, all of which have a chip production facility in China, will be allowed to expand the production capacity without any US backlash.

Of course, this does not contradict the plan of a US export-control policy, which the administration plans to continue. Alan Estevez, undersecretary of commerce for industry and security, noted last week in the industry gathering that the US plans to continue these restrictions for another year. Reportedly, all manufacturers of wafer fab equipment (WFE) from the US must acquire an export license from the Department of Commerce before exporting any tools for making either logic of memory chip indented for customers in China. Chipmakers Samsung, SK Hynix, and TSMC all received their licenses to export from October 2022 to October 2023. However, the US government now allows these companies to continue upgrading their Chinese plans beyond the renewed license expiry date of October 2024.

According to the report coming from Bloomberg, European Union has approved as much as 8.1 billion Euros (about 8.6 billion USD) for research of advanced semiconductors. Accompanied by the 13.7 billion Euros in private funds, the total investment for boosting domestic semiconductor manufacturing in the EU is almost 22 billion Euros. As part of the European CHIPS Act, the project aims to develop Europe as the world's semiconductor powerhouse, with as much as 20% of all semiconductors produced in the EU by 2030. This ambitious goal is backed by state subsidies, as well as investors creating private pools of funds to aid companies in creating semiconductor manufacturing facilities on European soil.

This Important Project of Common European Interest (IPCEI) on Microelectronics and Communication Technologies is an essential step for Europe's semiconductor independence. Internal Market Commissioner Thierry Breton noted, "In a geopolitical context of de-risking, Europe is taking its destiny into its own hands. By mastering the most advanced semiconductors, the EU will become an industrial powerhouse in markets of the future." Companies like Intel, Infineon, STMicroelectronics, GlobalFoundries, and Wolfspeed announced European investments, with TSMC considering a production facility in Germany. German Economy Minister Robert Habeck has noted that Germany has 31 projects in 11 regions, adding, "We can thus increase resilience across Europe in this important field and secure value creation and jobs."

Mark Liu, the executive Chairman of TSMC, has responded to recent reports released by the North American media about supposedly challenging workplace conditions. Current and former employees of the company's U.S operation have taken anonymously to Glassdoor to complain about "brutal" treatment on behalf of TSMC leadership—resulting in a 27% overall approval rating, which sits unfavorably next to the scores of nearby competitors—for example Intel gets 85%, albeit from far more user submissions. Liu has made comments to a Taiwanese news outlet (Focus Taiwan) where he suggests that: "those who are unwilling to take shifts should not enter the industry, since this field isn't just about lucrative wages but rather a passion for (semiconductors)."

TSMC is trying to meet staffing targets for its Phoenix, Arizona operation, but early feedback and difficult residential living could stifle this recruitment drive. Liu thinks that his North American division will offer potential employees a workplace culture that is unlike the one set for crew back in Taiwan. He told the local reporter that American TSMC team members will have an easier time, relative to how things are run at the company's native facilities. He also states that leadership is open to discussions with NA workers, as long as company values are followed (to a tee).

TSMC is quickly reacting to a surge in demand for NVIDIA hardware following an AI industry boom - the Taiwanese semiconductor contract manufacturer is reportedly planning to further expand its advanced packaging capabilities, due to current production lines hitting maximum capacity. News outlets have also cited the growth of 5G technology and Internet of Things (IoT) device markets as contributing factors. DigiTimes Asia reports that clients are snapping up chip-on-wafer-on-substrate (CoWoS) at an increased and unprecedented rate. TSMC has decided to provide NVIDIA - an extremely high profile customer - with an extra 10,000 CoWoS wafers. The article sourced information from a recent company shareholder meeting, where chairman Mark Liu discussed these expansions plans. He outlined improved factory facilities that will result in an additional output of 1,000 to 2,000 wafers per month. TSMC is set to upgrade equipment at its existing facilities in order to meet increasing demand.

Trendforce has also published its evaluation from the same TSMC shareholding meeting: "Due to the generative AI trend initiated by ChatGPT, the demand for advanced packaging orders for TSMC has increased, forcing an increase in advanced packaging capacity. TSMC also pointed out that the demand for TSMC's advanced packaging capacity far exceeds the existing capacity, and it is forced to increase production as quickly as possible. Chairman Mark Liu stated that the current investment in R&D focuses on two legs, namely 3D IC (chip stacking) and advanced packaging...At present, three-quarters of TSMC's R&D expenditure is used for advanced processes, and one quarter for mature and special processes, with advanced packaging falling under mature and special processes."

TSMC is having a tough time establishing itself in the United States with new manufacturing facilities - the Taiwanese multinational semiconductor contract manufacturing and design company is putting a great deal of effort into finishing its new Arizona foundry, located in the greater Phoenix area. A minor fire incident occurred at one of their construction sites in late April, and North American news outlets last week reported on the company's struggle to recruit enough staff - approximately 4500 positions - for its upcoming Arizona plants. Current and former employees of TSMC in the U.S. have taken to the Glassdoor review website - user feedback has so far awarded the company a 27% approval rating via 91 submissions, thus warning potential candidates to stay away. Apparently American staffers have found it difficult to adjust to TSMC's corporate culture, and the company could face further challenges when transferring staff from Taiwan.

The latest news from Arizona points to problems encountered at the so-called "TSMC Village" - actually two residential locations divided into "A" and "B" categories. Taiwan's Economic Daily released a video report late last month covering crime-related incidents - this information has since been picked up by Western news outlets. Perpetrators have targeted houses and cars within these new build communities - UDN's footage indicates that seven vehicles located in Village A were damaged with a portion of them broken into. A single Village B property was accessed by possible squatters, and an unspecified number of TSMC engineers have been "robbed" throughout May. Several residents were contacted by UDN - interviewees expressed frustrations with the lack of security in the area, and blamed a local management company for not bolstering prevention measures.

When TSMC introduced its N3 lineup of nodes, the company only talked about the logic scaling of the two new semiconductor manufacturing steps. However, it turns out that there was a reason for it, as WikiChip confirms that the SRAM bit cells of N3 nodes are almost identical to the SRAM bit cells of N5 nodes. At TSMC 2023 Technology Symposium, TSMC presented additional details about its N3 node lineup, including logic and SRAM density. For starters, the N3 node is TSMC's "3 nm" node family that has two products: a Base N3 node (N3B) and an Enhanced N3 node (N3E). The base N3B uses a new (for TSMC) self-aligned contact (SAC) scheme that Intel introduced back in 2011 with a 22 nm node, which improves the node's yield.

Regardless of N3's logic density improvements compared to the "last-generation" N5, the SRAM density is almost identical. Initially, TSMC claimed N3B SRAM density was 1.2x over the N5 process. However, recent information shows that the actual SRAM density is merely a 5% difference. With SRAM taking a large portion of the transistor and area budget of a processor, N3B's soaring manufacturing costs are harder to justify when there is almost no area improvement. For some time, SRAM scaling wasn't following logic scaling; however, the two have now completely decoupled.

Mobile devices touch every aspect of our digital lives. In the palm of your hand is the ability to both create and consume increasingly immersive, AI-accelerated experiences that continue to drive the need for more compute. Arm is at the heart of many of these, bringing unlimited delight, productivity and success to more people than ever. Every year we build foundational platforms designed to meet these increasing compute demands, with a relentless focus on high performance and efficiency. Working closely with our broader ecosystem, we're delivering the performance, efficiency and intelligence needed on every generation of consumer device to expand our digital lifestyles.

Today we are announcing Arm Total Compute Solutions 2023 (TCS23), which will be the platform for mobile computing, offering our best ever premium solution for smartphones. TCS23 delivers a complete package of the latest IP designed and optimized for specific workloads to work seamlessly together as a complete system. This includes a new world-class Arm Immortalis GPU based on our brand-new 5th Generation GPU architecture for ultimate visual experiences, a new cluster of Armv9 CPUs that continue our performance leadership for next-gen artificial intelligence (AI), and new enhancements to deliver more accessible software for the millions of Arm developers.

During the European Technology Symposium 2023, TSMC presented additional details regarding the upcoming complementary FET (CFET) technology to power the next generation of silicon-based devices. With Nanosheet replacing FinFET, the CFET technology will do the same to the Gate All Around FET (GAAFET) Nanosheet nodes. As the company notes, CFET transistors are now in the TSMC labs and are being tested for performance, efficiency, and density. Compared to GAAFET, CFET will provide greater design in all of those areas, but it will require some additional manufacturing steps to get the chip working as intended. Integrating both p-type and n-type FETs into a single device, CFET will require the use of High NA EUV scanners with high precision and high power to manufacture it.

The use of CFET, as the roadmap shows, is one of the last steps in the world of silicon. It will require the integration of new materials into the manufacturing process, resulting in a greater investment into research and development that is in charge of node creation. Kevin Zhang, senior vice president at TSMC, responsible for technology roadmap and business development, notes: "Let me make a clarification on that roadmap, everything beyond the Nanosheet is something we will put on our [roadmap] to tell you there is still future out there. We will continue to work on different options. I also have the add on to the one-dimensional material-[based transistors] […], all of those are being researched on being investigated on the future potential candidates right now, we will not tell you exactly the transistor architecture will be beyond the Nanosheet."