Last week at the IEEE International Electron Devices Meeting, the world's top-three semiconductor foundries, TSMC, Intel (Intel Foundry Services or IFS), and Samsung Electronics, demonstrated their respective approaches to an evolutionary new transistor device called the CFET, or complementary field-effect transistors. A CFET is a kind of 3-D transistor that stacks both kinds of FETs needed for CMOS logic. All three fabs are transitioning from FinFET to nanosheets, or GAAFETs (gates all-around FETs).

While FinFETs use vertical silicon fins, with gates controlling the flow of current through them; while in a nanosheet, the vertical fin is cut into a set of ribbons, each surrounded by the gate. A CFET is essentially a taller nanosheet device in which uses half of the available ribbons for one device, and the other half for another. This device builds the two types of transistor, nFETs and pFETs on top of each other, in an integrated process. CFETs are the evolutionary next step to conventional GAAFETs, and it's predicted to enter mass production only 7-10 years from now. By that time, the industry will begin to feel the pushback from technological barriers preventing development beyond 10 angstrom-class nodes.At IEDM 2023, each of the big three foundries showcased their latest developments in the field of CFETs. Intel Foundry Services showed off the simplest device made with CFETs, an inverter. In semiconductor jargon, a CMOS inverter sends the same input voltage to both of the ribbon devices in the stack, producing a logical inverse of the input. Intel achieved to pull off an inverter on a single "fin" (i.e. a single CFET, with its single fin cut into ribbons). The company comments that at maximum scaling, this is half the size of a regular CMOS inverter made using current technology. Such a stacked transistor inverter loses some of its die area advantage because of the interconnects needed. Intel is attempting to mitigate this by reducing some of the congestions from the interconnects, and an upcoming new tech called backside power delivery, allowing interconnects to exists both above and below the surface of the silicon. With this, Intel hopes for a contacted poly-pitch or CPP (distance between two transistors) of 60 nm. Today's 5 nm-class foundry nodes have a CPP of 50 nm, but that's using simple FinFETs with one-sided interconnects.

Samsung refers to its CFET as "3DSFET" or 3D stacked FET. Without divulging too many technical details, the company is claiming a CPP of 48 nm to 45 nm, or practically the same as the 50 nm CPP of FinFETs (but with around 2x the density increase since it's 2 transistors per device). Samsung is betting big on a method of electrically isolating the sources and drains of the stacked pFET and nFET, without which the device leaks current. The sauce behind this isolation is a new dry type etching technology instead of a wet chemical-based one, leading to an 80% boost in yields of good devices. Samsung is using a single nanosheet in each of the paired devices, instead of Intel's three. TSMC too is claiming a CPP of 48 nm, which is similar to that of Samsung. The Taiwanese fab is innovating a new form of dielectric layer between the top- and bottom devices, to keep them electrically isolated.