The EUV lithography machine from ASML ordered by Rapidus is expected to arrive in Japan in mid-December, according to information from Nikkei cited by TrendForce. This marks the first deployment of EUV technology in Japan, an important step for the country's semiconductor industry as it seeks to establish itself as a major player. Rapidus is currently building a factory in Chitose, Hokkaido, and plans to start mass production of 2 nm chips in 2027. The company also plans to purchase several EUV devices if the 2-nanometer chip production is successful, and intends to build a second production facility specifically for 1.4 nm chips. To support these operations, ASML will establish a service center in Chitose City.

NVIDIA CEO Jensen Huang hinted at the possibility of outsourcing AI chip production to Rapidus. As of October, construction progress on the Rapidus facility, which began in September 2023, is up to 63% and remains on track. In addition to Rapidus, Micron's Hiroshima plant is scheduled to install EUV equipment in 2025, allowing for mass production in 2026. JASM, a TSMC subsidiary in Japan, plans to integrate EUV lithography with a second wafer plant in 2027 that will have a 6 nm production line.

TSMC has reportedly postponed the opening ceremony of its Arizona Fab 21 facility, initially planned for December 6, amidst the changing US political landscape. The ceremony is now expected to take place after President-elect Donald Trump's inauguration in early 2025, showing that the chipmaker is taking a cautious approach to geopolitical shifts. The delay comes as TSMC finds itself at the intersection of global semiconductor politics. The company has invested heavily in its Arizona operations (estimated at $65 billion total), with Wang Yinglang, deputy general manager of wafer factory operations, leading the project. Despite initial skepticism, Wang's team has maintained an ambitious timeline, with mass production scheduled to begin in the first half of 2025.

Rumors also suggest that TSMC's decision stems from broader concerns about the incoming administration's semiconductor policies. However, TSMC maintains a strong position due to its unmatched technological capabilities, particularly in advanced manufacturing processes, which competitors like Intel and Samsung struggled to achieve. The Arizona facility represents a crucial piece of TSMC's global expansion strategy, which includes new factories in Japan and Germany. While the company faces challenges, including labor issues and rising costs in the US, its strategic importance to the global semiconductor supply chain remains unchanged. The only thing that is changing is the timeline of the opening ceremony, while high-volume production stays on track.

According to Taiwanese media Commercial Times, Intel is significantly increasing its outsourcing of "Arrow Lake" CPU production to TSMC, a strategic move as it grapples with persistent issues in its own foundry division. This decision to outsource a substantial portion of Arrow Lake's production is a significant shift in Intel's strategy, showing the company's rising reliance on external partners to meet quality and performance demands. The Arrow Lake Core Ultra 200 series is Intel's first major outsourcing initiative, in which Intel gave its core IP to third-party foundries, more specifically for a 3 nm node at TSMC. However, it clearly indicates the performance gaps in Intel's own Intel Foundry and the high demand expectations for the new CPUs. Originally intended to use Intel 20A node, Intel shifted focus of 18A node for its products and upcoming foundry customers.

Intel's recent orders with TSMC extend to its upcoming Lunar Lake chips and next-generation Falcon Shores AI GPUs, both of which will use TSMC's 3 nm process. Although Intel's 18A node remains promising, the company relies on current products to sustain its revenue streams, making TSMC's support crucial in ensuring timely shipments. This increased outsourcing reflects Intel's need to maintain competitive performance in the short term. Once its Foundry division meets performance and capacity targets, Intel aims to bring more CPU manufacturing back in-house. However, if anything goes wrong, Intel could face challenges securing sufficient volume from TSMC, as the foundry has longstanding commitments with major clients like Apple, NVIDIA, Qualcomm, and AMD.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

Even with billions of US dollars being invested overseas, TSMC cannot legally manufacture its most advanced nodes outside of Taiwan. According to Taiwan's Minister of Economic Affairs J.W. Kuo, "Since Taiwan has regulations to protect its own technologies, TSMC cannot produce 2-nanometer chips overseas currently." He added, "Although TSMC plans to make 2-nanometer chips [abroad] in the future, its core technology will stay in Taiwan." This provides crucial insight into TSMC's strategic positioning, both in its US expansion plans and in navigating global geopolitical waters, especially with Taiwan being the major hub of silicon innovation. Taiwan's semiconductor industry follows strict regulations regarding overseas production capabilities, requiring companies to maintain their most advanced manufacturing processes within Taiwan.

The company's international expansion strategy includes significant developments in the United States. TSMC's Arizona facilities are central to these plans, with multiple fabs in different stages of development. The initial Arizona facility will begin producing 4 nm chips imminently, while a second facility, scheduled to open in 2028, will manufacture then mature 3 nm and 2 nm chips. A third planned facility aims to produce 2 nm or more sophisticated chips. Meanwhile, Taiwan-based facilities will produce more advanced chips at the same time, with volume production of A-16 chips planned for late 2026, following the rollout of 2 nm chip production in 2025. Furthermore, Taiwan-US semiconductor cooperation will continue regardless of political changes. Taiwan Semiconductor Industry Association (TSIA) Chairman and TSMC Senior Vice President Cliff Hou noted that historical evidence suggests US electoral outcomes have not significantly impacted this technological partnership, though some adjustments may occur.

AMD Ryzen AI MAX 300-series processors, codenamed "Strix Halo," have been on in the news for close to a year now. These mobile processors combine "Zen 5" CPU cores with an oversized iGPU that offers performance rivaling discrete GPUs, with the idea behind these chips being to rival the Apple M3 Pro and M3 Max processors powering MacBook Pros. The "Strix Halo" mobile processor is an MCM that combines one or two "Zen 5" CCDs (some ones featured on "Granite Ridge" desktop processors and "Turin" server processors), with a large SoC die. This die is built either on the 5 nm (TSMC N5) or 4 nm (TSMC N4P) node. It packs a large iGPU based on the RDNA 3.5 graphics architecture, with 40 compute units (CU), and a 50 TOPS-class XDNA 2 NPU carried over from "Strix Point." The memory interface is a 256-bit wide LPDDR5X-8000 for sufficient memory bandwidth for the up to 16 "Zen 5" CPU cores, the 50 TOPS NPU, and the large 40 CU iGPU.

Golden Pig Upgrade leaked what looks like a company slide from a notebook OEM, which reveals the iGPU model names for the various Ryzen AI MAX 300-series SKUs. Leading the pack is the Ryzen AI MAX+ 395. This is a maxed out SKU with a 16-core/32-thread "Zen 5" CPU that uses two CCDs. All 16 cores are full-sized "Zen 5." The CPU has 64 MB of L3 cache (32 MB per CCD), each of the 16 cores has 1 MB of dedicated L2 cache. The iGPU is branded Radeon 8060S, it comes with all 40 CU (2,560 stream processors) enabled, besides 80 AI accelerators, and 40 Ray accelerators. The Ryzen AI MAX 390 is the next processor SKU, it comes with a 12-core/24-thread "Zen 5" CPU. Like the 395, the 390 is a dual-CCD processor, all 12 cores are full-sized "Zen 5." There's 64 MB of L3 cache, and 1 MB of L2 cache per core. The Radeon 8060S graphics solution is the same as the one on the Ryzen AI MAX+ 395, it comes with all 40 CU enabled.

M31 Technology Corporation, a leading global provider of silicon intellectual property (IP), today announced that its cutting-edge USB4 IP has achieved silicon validation on TSMC's 5 nm (N5) process. The newly validated IP enhances data transfer capabilities for a new wave of mobile and portable devices. The announcement coincides with M31's participation in TSMC's 2024 Open Innovation Platform (OIP) Ecosystem Forum in Taiwan. This milestone underscores the close collaboration between M31 and TSMC, reflecting M31's commitment to advancing high-performance IP solutions by leveraging TSMC's innovative platform to drive next-generation connectivity.

M31's USB4 IP is built on the latest USB4 specification and represents a major leap in the evolution of USB architecture. It supports multi-protocol tunneling, enabling simultaneous transmission of multiple data types—such as USB, DisplayPort, and PCIe—over a single connection. The USB4 IP achieves 40 Gbps data transfer rates, significantly enhancing bandwidth associated with previous USB standards. The IP is fully compatible with USB 3.2, USB 2.0, and Thunderbolt 3, ensuring seamless integration with existing and future devices.

According to a recent Reuters report, OpenAI is continuing with its moves in the custom silicon space, expanding beyond its reported talks with Broadcom to include a broader strategy involving multiple industry leaders. Broadcom is a fabless chip designer known for a wide range of silicon solutions spanning from networking, PCIe, SSD controllers, and PHYs all the way up to custom ASICs. The company behind ChatGPT is actively working with both Broadcom and TSMC to develop its first proprietary AI chip, specifically focused on inference operations. Getting a custom chip to do training runs is a bit more complex task, and OpenAI leaves that to its current partners until the company figures out all details. Even with an inference chip, the scale at which OpenAI works and serves its models makes financial sense for the company to develop custom solutions tailored to its infrastructure needs.

This time, the initiative represents a more concrete and nuanced approach than previously understood. Rather than just exploratory discussions, OpenAI has assembled a dedicated chip team of approximately 20 people, led by former Google TPU engineers Thomas Norrie and Richard Ho. The company has secured manufacturing capacity with TSMC, targeting a 2026 timeline for its first custom-designed chip. While Broadcom's involvement leverages its expertise in helping companies optimize chip designs for manufacturing and manage data movement between chips—crucial for AI systems running thousands of processors in parallel—OpenAI is simultaneously diversifying its compute strategy. This includes adding AMD's Instinct MI300X chips to its infrastructure alongside its existing NVIDIA deployments. Similarly, Meta has the same approach, where it now trains its models on NVIDIA GPUs and serves them to the public (inferencing) using AMD Instinct MI300X.

According to a recent Reuters report, TSMC has decided to cut off Chinese firm Sophgo following the discovery of TSMC-manufactured components in Huawei's advanced AI processor. The suspension came after technology research firm TechInsights identified a TSMC-manufactured chip within Huawei's Ascend 910B processor during a detailed analysis. This discovery raised significant concerns, as Huawei has been restricted from accessing such technology under US export controls since 2020. TSMC promptly notified US authorities upon learning of the situation and launched an internal investigation. While being sanctioned by the US, Huawei needed to use a proxy firm to get access to high-end silicon manufacturing to produce its Ascend accelerators.

Sophgo, which has ties to cryptocurrency mining equipment manufacturer Bitmain, strongly denies any business relationship with Huawei. The company states it has provided TSMC with a detailed investigation report asserting its compliance with all applicable laws, saying: "SOPHGO has never been engaged in any direct or indirect business relationship with Huawei. SOPHGO has been conducting business in strict compliance with applicable laws and regulations, including but not limited to all the applicable US national export control laws and regulations, and has never been in violation of any of such laws and regulations. SOPHGO has provided detailed investigation report to TSMC to prove that SOPHGO is not related to the Huawei investigation."

The American semiconductor landscape reached a significant milestone as TSMC's new Arizona manufacturing facility demonstrated remarkable production efficiency, exceeding its Taiwanese counterparts by 4% in yield rates. This achievement, revealed at a recent industry webinar by the company's US division chief, represents a major step forward in America's push to strengthen domestic chip manufacturing capabilities. Since initiating its 4 nm node production operations this spring, the Phoenix-based facility has demonstrated impressive technical proficiency, achieving production standards that match and surpass TSMC's established Taiwanese facilities. The project, backed by substantial federal support, including $11.6 billion in combined grants and loans plus significant tax incentives, aims to establish three cutting-edge manufacturing plants in Arizona.

The company's global leadership praised the facility's performance, noting its strategic importance in demonstrating TSMC's ability to maintain exceptional manufacturing standards across international locations. This success carries particular weight given the project's earlier hurdles, which included workforce challenges and timeline adjustments that shifted the entire production schedule by approximately one year. This development gains additional significance against industry-wide challenges, particularly as competitors like Intel and Samsung face operational and financial obstacles. The semiconductor giant's plans now extend to potential further expansion, with the Phoenix site capable of hosting up to six manufacturing facilities. Future growth prospects could be enhanced by proposed additional government initiatives supporting domestic chip production.

Details of what is claimed to be Google's upcoming Tensor G5 and G6 SoCs have popped up over on Notebookcheck.net and the site claims to have found the specs on a public platform, without going into any further details. Those that were betting on the Tensor G5—codenamed Laguna—delivering vastly improved performance over the Tensor G4, are likely to be disappointed, at least on the CPU side of things. As previous rumours have suggested, the chip is expected to be manufactured by TSMC, using its N3E process node, but the Tensor G5 will retain the single Arm Cortex-X4 core, although it will see a slight upgrade to five Cortex-A725 cores vs. the three Cortex-A720 cores of the Tensor G4. The G5 loses two Cortex-A520 cores in favour of the extra Cortex-A725 cores. The Cortex-X4 will also remain clocked at the same peak 3.1 GHz as that of the Tensor G4.

Interestingly it looks like Google will drop the Arm Mali GPU in favour of an Imagination Technologies DXT GPU, although the specs listed by Notebookcheck doesn't add up with any of the specs listed by Imagination Technologies. The G5 will continue to support 4x 16-bit LPDDR5 or LPDDR5X memory chips, but Google has added support for UFS 4.0 memory, something that's been a point of complaint for the Tensor G4. Other new additions is support for 10 Gbps USB 3.2 Gen 2 and PCI Express 4.0. Some improvements to the camera logic has also been made, with support for up to 200 Megapixel sensors or 108 Megapixels with zero shutter lag, but if Google will use such a camera or not is anyone's guess at this point in time.

Last time we reported on Samsung Foundry, the company publicly apologized for its setbacks in the memory and foundry divisions, especially as its 3 nm GAA FET node has failed to attract new customers. On the other hand, Intel has also been struggling with its Foundry unit bleeding billions of Dollars in a bid to secure its spot as one of the best foundries for companies to manufacture their chips. There is no better pair than two struggling foundries looking for customers and new ways to conduct research than Intel and Samsung. According to an exclusive by South Korean media outlet "MK," it has reportedly been confirmed that Intel approached Samsung to form a "Foundry Alliance" to boost their foundry business units.

According to the source, Intel CEO Pat Gelsinger is reportedly eager to meet with Samsung Electronics Chairman Lee Jae-yong face-to-face to discuss "comprehensive collaboration in the foundry sector." What exactly will happen between the two is still unclear. Back in 2014, GlobalFoundries and Samsung formed a partnership for 14 nm FinFET offerings, and that was a wide success. Jointly developing a node and offering it in their foundry units could be the target goal for Intel and Samsung. At some level, research and development, as well as sharing valuable manufacturing information on yield improvements, should be beneficial for both to put together the final pieces of the semiconductor puzzle.

At TSMC's earnings call on the 17th, the company revealed that its CoWoS (Chip-on-Wafer-on-Substrate) capacity will double each year in 2024 and 2025, but demand will continue to outpace supply. According to a report from Money DJ, the CoWoS expansion wave is expected to extend into 2026, promising strong growth for equipment suppliers for at least the next two to three years.

TSMC stated that advanced packaging currently accounts for approximately 7-9% of its revenue, and growth in this segment is expected to outpace the company's average over the next five years. While the gross margin for advanced packaging is slightly below the company average, it is steadily approaching it. Regarding CoWoS capacity, customer demand significantly exceeds TSMC's ability to supply, even with production capacity doubling year-on-year in both 2024 and 2025.

TSMC today announced consolidated revenue of NT$759.69 billion (US$23.50 billion), net income of NT$325.26 billion (US$10.08 billion), and diluted earnings per share of NT$12.54 (US$1.94 per ADR unit) for the third quarter ended September 30, 2024. Year-over-year, third quarter revenue increased 39.0% while net income and diluted EPS both increased 54.2%. Compared to second quarter 2024, third quarter results represented a 12.8% increase in revenue and a 31.2% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, third quarter revenue was $23.50 billion, which increased 36.0% year-over-year and increased 12.9% from the previous quarter. Gross margin for the quarter was 57.8%, operating margin was 47.5%, and net profit margin was 42.8%. In the third quarter, shipments of 3-nanometer accounted for 20% of total wafer revenue; 5-nanometer accounted for 32%; 7-nanometer accounted for 17%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 69% of total wafer revenue.

According to TechNews Taiwan, Intel has made significant progress in implementing ASML's cutting-edge High-NA EUV lithography technology. The company has successfully completed the assembly of its second High-NA "Twinscan EXE" EUV system at its Portland facility, as confirmed by Mark Phillips, Intel's Director of Lithography Hardware. Christophe Fouquet, CEO of ASML, highlighted that the new assembly process allows for direct installation at the customer's site, eliminating the need for disassembly and reassembly, thus saving time and resources. Phillips expressed enthusiasm about the technology, noting that the improvements offered by High-NA EUV machines have surpassed expectations compared to standard EUV systems. Given the massive $380 million price point of these High-NA systems, any savings are valuable in the process.

The rapid progress in installation and implementation of High-NA EUV technology at Intel's facilities positions the company strongly for production transition. With all necessary infrastructure in place and inspections of High-NA EUV masks already underway, Intel aims to have its Intel 14A process in mass production by 2026-2027. As Intel leads in High-NA EUV adoption, other industry giants are following suit. ASML plans to deliver High-NA EUV systems to TSMC by year-end, with rumors suggesting that TSMC's first system will possibly arrive in September. Samsung has also committed to the technology, although recent reports indicate a potential reduction in their procurement plans. Additionally, this development has sparked discussions about the future of photoresist technology, with Phillips suggesting that while Chemically Amplified Resist (CAR) is currently sufficient, future advancements may require metal oxide photoresists. This provides a small insight into Intel's future nodes.

GPU chip packages of the "Navi 4x" generation of GPUs could be generationally smaller than their predecessors, according to leaked package dimensions of the "Navi 44" chip put out by Olrak29_. With its next-generation Radeon RX gaming GPUs based on the RDNA 4 graphics architecture, AMD has decided to focus on gaining market-share in the performance and mainstream segments, ceding the enthusiast segment to NVIDIA. As part of its effort, the company is making RDNA 4 efficient at every level—architecture, process, and package.

At the architecture level, RDNA 4 is expected to improve performance, particularly the performance cost of ray tracing, through a more specialized ray tracing hardware stack. At the process level, AMD is expected to switch to a more efficient foundry node, with some reports suggesting the TSMC 4 nm, such as the N4P or N4X. For a mid-range GPU like the "Navi 44," which succeeds the "Navi 23" and "Navi 33," these mean a rather big leap from the 7 nm or 6 nm DUV nodes. The leak suggests a smaller package, measuring 29 mm x 29 mm. In comparison, the "Navi 23" package measures 35 mm x 35 mm. The smaller package could make these GPUs friendlier with gaming notebooks, where mainboard PCB real-estate is at a premium.

Credo Technology Group Holding Ltd (Credo), an innovator in providing secure, high-speed connectivity solutions that deliver improved energy efficiency as data rates and corresponding bandwidth requirements increase throughout the data infrastructure market, is excited to announce the company's first Toucan PCI Express (PCIe) 6, Compute Express Link (CXL) 3.x and Magpie PCIe 7, CXL 4.x retimers and OSFP-XD 16x 64GT/s (1 Tb) PCIe 6/CXL HiWire AECs. Credo will demonstrate the Toucan PCIe 6 retimers and HiWire AECs at the upcoming Open Compute Project (OCP) Summit October 15-17 in Booth 31 and the OCP Innovation Center.

Building on Credo's renowned Serializer/Deserializer (SerDes) technology, the new PCIe 6 and PCIe 7 retimers deliver industry-leading performance and power efficiency while being built on lower cost, more mature process nodes than competing devices. Credo will also include enhanced diagnostic tools, including an embedded logic analyzer and advanced SerDes tools driven by a new GUI designed to enable rapid bring up and debug of customer systems.

TSMC announced that its revenue for September 2024 reached NT$251.87 billion (US$7.80 billion), representing a 39% increase compared to the same month last year. The cumulative revenue for the first three quarters of 2024 climbed to NT$2,025.85 billion (US$62.72 billion), showing a 32% year-over-year growth. The company's third-quarter revenue amounted to NT$759.7 billion (US$23.52 billion), exceeding TSMC's own guidance of NT$706.6 billion to NT$731.5 billion (US$22.4 billion to US$23.2 billion). TSMC will report full third-quarter earnings on Oct. 17.

A report from Data Center Dynamics quotes sources saying that, due to increasing demand from NVIDIA and others, TSMC has been forced to change its CoWoS capacity expansion plan several times. In response, TSMC is building two more fabs, named P4 and P5, in Kaohsiung, Taiwan, raising the company's total number of facilities in the region to five. Four months ago, the company announced that it would build a third 2 nm fab at Nanzih Technology Industrial Park in Kaohsiung. The company's P1 fab, which started in August 2022, is expected to begin mass production next year, while P2 and P3 are still in the construction phase. TSMC's CoWoS monthly capacity is expected to reach more than 40,000 wafers by the end of 2024, 65,000 wafers in 2025, and at least 80,000 wafers in 2026.

NVIDIA's "Blackwell" series of GPUs, including B100, B200, and GB200, are reportedly sold out for 12 months or an entire year. This directly means that if a new customer is willing to order a new Blackwell GPU now, there is a 12-month waitlist to get that GPU. Analyst from Morgan Stanley Joe Moore confirmed that in a meeting with NVIDIA and its investors, NVIDIA executives confirmed that the demand for "Blackwell" is so great that there is a 12-month backlog to fulfill first before shipping to anyone else. We expect that this includes customers like Amazon, META, Microsoft, Google, Oracle, and others, who are ordering GPUs in insane quantities to keep up with the demand from their customers.

The previous generation of "Hopper" GPUs was ordered in 10s of thousands of GPUs, while this "Blackwell" generation was ordered in 100s of thousands of GPUs simultaneously. For NVIDIA, that is excellent news, as that demand is expected to continue. The only one standing in the way of customers is TSMC, which manufactures these GPUs as fast as possible to meet demand. NVIDIA is one of TSMC's largest customers, so wafer allocation at TSMC's facilities is only expected to grow. We are now officially in the era of the million-GPU data centers, and we can only question at what point this massive growth stops or if it will stop at all in the near future.

Samsung Electronics is speeding up its work on 2 nm production facilities, industry sources say. The company has started to install advanced equipment at its "S3" foundry line in Hwaseong to set up a 2 nm production line. This line aims to produce 7,000 wafers each month by the first quarter of next year. Also, Samsung plans to create a 1.4 nm production line at its "S5" foundry in Pyeongtaek Plant 2 by the second quarter of next year. This line has a goal to make 2,000 to 3,000 wafers each month. By the end of next year, Samsung will change all the remaining 3 nm production lines at "S3" to 2 nm.

As we reported earlier, Samsung has pushed back the start date for its Tyler, Texas foundry. The plant set to open by late 2024, won't install equipment until after 2026. Also, Samsung has changed its plans for the Pyeongtaek Fab 4 foundry line. Because of lower demand, it will now make DRAM instead, moreover, at Pyeongtaek Fab 3, which has a 4 nm line, Samsung has cut back production. These changes are part of Samsung's plan to make 2 nm chips next year and 1.4 nm chips by 2027. The company wants to catch up with its rival TSMC, right now, Samsung has 11.5% of the global foundry market in Q2, while TSMC leads with 62.3%. An industry expert stressed how crucial this is saying, "With the delay in 3 nm Exynos production and other issues, getting the 2 nm process right could make or break Samsung Foundry". The struggle for Samsung is real, with the company's top management, led by DS Division Vice Chairman Jeon Young-hyun, having recently issued a public apology for the division's underwhelming performance.

TSMC, the world leader in semiconductor manufacturing, is moving to production with NVIDIA's computational lithography platform, called cuLitho, to accelerate manufacturing and push the limits of physics for the next generation of advanced semiconductor chips. A critical step in the manufacture of computer chips, computational lithography is involved in the transfer of circuitry onto silicon. It requires complex computation - involving electromagnetic physics, photochemistry, computational geometry, iterative optimization and distributed computing. A typical foundry dedicates massive data centers for this computation, and yet this step has traditionally been a bottleneck in bringing new technology nodes and computer architectures to market.

Computational lithography is also the most compute-intensive workload in the entire semiconductor design and manufacturing process. It consumes tens of billions of hours per year on CPUs in the leading-edge foundries. A typical mask set for a chip can take 30 million or more hours of CPU compute time, necessitating large data centers within semiconductor foundries. With accelerated computing, 350 NVIDIA H100 Tensor Core GPU-based systems can now replace 40,000 CPU systems, accelerating production time, while reducing costs, space and power.

After Apple, we just learned that AMD is the next company in line for US-based manufacturing in the TSMC Arizona facility. Industry analyst Tim Culpan reports that TSMC's Fab 21 in Arizona will soon be producing AMD's high-performance computing (HPC) processors, with tape out and manufacturing expected to commence on TSMC's 5 nm node next year. This move comes after previously reported Apple's A16 SoC production, which is already in progress at the facility and could see shipments before the end of this year, significantly ahead of the initially projected early 2025 schedule. The production of AMD's HPC chips in Arizona marks a crucial step towards establishing an AI-hardware supply chain operating entirely on American soil, which is expected to further expand with Intel Foundry and Samsung Texas facility.

Making HPC processors domestically serves as a significant milestone in reducing dependence on overseas semiconductor manufacturing and strengthening the US's position in the global chip industry. Adding to the momentum, TSMC and Amkor recently announced a collaboration on advanced packaging technologies, including Integrated Fan-Out (InFO) and Chip-on-Wafer-on-Substrate (CoWoS), which are vital for high-performance AI chips. However, as Amkor facilities are yet to be built, these chips are going to be shipped back to Taiwan for packaging before being integrated into the final product. Once the Amkor facility is up and running, Arizona will become the birthplace of fully manufactured and packaged silicon chips.

High-resolution die-shots of the AMD "Zen 5" 8-core CCD were released and annotated by Nemez, Fitzchens Fitz, and HighYieldYT. These provide a detailed view of how the silicon and its various components appear, particularly the new "Zen 5" CPU core with its 512-bit FPU. The "Granite Ridge" package looks similar to "Raphael," with up to two 8-core CPU complex dies (CCDs) depending on the processor model, and a centrally located client I/O die (cIOD). This cIOD is carried over from "Raphael," which minimizes product development costs for AMD at least for the uncore portion of the processor. The "Zen 5" CCD is built on the TSMC N4P (4 nm) foundry node.

The "Granite Ridge" package sees the up to two "Zen 5" CCDs snuck up closer to each other than the "Zen 4" CCDs on "Raphael." In the picture above, you can see the pad of the absent CCD behind the solder mask of the fiberglass substrate, close to the present CCD. The CCD contains 8 full-sized "Zen 5" CPU cores, each with 1 MB of L2 cache, and a centrally located 32 MB L3 cache that's shared among all eight cores. The only other components are an SMU (system management unit), and the Infinity Fabric over Package (IFoP) PHYs, which connect the CCD to the cIOD.

Amkor Technology, Inc. and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region's semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC's advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC's front-end fab and Amkor's back-end facility will accelerate overall product cycle times.

According to a recent Reuters report, the US government, under Biden's administration, will allow a few criteria-matching semiconductor fabs to circumvent environmental protection laws. On Wednesday, President Joe Biden signed legislation that effectively enables these fabs to not follow the strict regulations designed for maximum preservation of the environment. The Semiconductor Industry Association has noted that without this new legislation, companies that are extending facilities on US soil would be significantly slowed down due to the National Environmental Policy Act (NEPA) of 1969. The CHIPS Act's primary force driver isn't just domestic production but near-future completion so that future geopolitical shifts don't impact US companies. The speed of getting permits to manufacture advanced chips is essential for every CHIPS Act recipient company, like Intel, Samsung, TSMC, and Micron.