With more countries creating initiatives to develop homegrown processors capable of powering powerful supercomputing facilities, India has just presented its development milestone with Aum HPC. Thanks to information from the report by The Next Platform, we learn that India has developed a processor for powering its exascale high-performance computing (HPC) system. Called Aum HPC, the CPU was developed by the National Supercomputing Mission of the Indian government, which funded the Indian Institute of Science, the Department of Science and Technology, the Ministry of Electronics and Information Technology, and C-DAC to design and manufacture the Aum HPC processors and create strong, strong technology independence.

The Aum HPC is based on Armv8.4 CPU ISA and represents a chiplet processor. Each compute chiplet features 48 Arm Zeus Cores based on Neoverse V1 IP, so with two chiplets, the processor has 96 cores in total. Each core gets 1 MB of level two cache and 1 MB of system cache, for 96 MB L2 cache and 96 MB system cache in total. For memory, the processor uses 16-channel 32-bit DDR5-5200 with a bandwidth of 332.8 GB/s. To expand on that, HBM memory is present, and there is 64 GB of HBM3 with four controllers capable of achieving a bandwidth of 2.87 TB/s. As far as connectivity, the Aum HPC processor has 64 PCIe Gen 5 Lanes with CXL enabled. It is manufactured on a 5 nm node from TSMC. With a 3.0 GHz typical and 3.5+ GHz turbo frequency, the Aum HPC processor is rated for a TDP of 300 Watts. It is capable of producing 4.6+ TeraFLOPS per socket. Below are illustrations and tables comparing Aum HPC to Fujitsy A64FX, another Arm HPC-focused design.

Thanks to the latest release of the Power On newsletter from Mark Gurman, we have additional information about Apple's upcoming M3 Pro chip. Currently in testing and reported on by an App Store developer, Apple is looking to upgrade the microarchitecture of the forthcoming chip and add additional cores to the system for more performance. As the report notes, the entry-level M3 Pro chip currently in testing will have 12 CPU cores, six for efficiency and six for performance tasks, with 18 graphics cores, all manufactured on TSMC's 3 nm node. The current baseline for M2 Pro is 10 CPU cores, where four are dedicated to efficiency, and six are dedicated to performance. The current generation entry-level M2 Pro also features a 16-core GPU, which is two cores fewer than the upcoming model.

Generally, the M3 Pro chip will boost integrated memory across the board, as the sample spotted in testing shows 36 GB of memory. The M2 Pro offered 32 GB in that memory tier, so a four GB increase is inbound there. Presumably, the 16 GB version (if it exists) and 64 GB version will also get memory bumps by going the M3 Pro route. Of course, we have to wait for more information as these chips become more widely available to developers.

Samsung has invested heavily in semiconductor manufacturing technology to provide clients with a viable alternative to TSMC and its portfolio of nodes spanning anything from mobile to high-performance computing (HPC) applications. Today, we have information that Samsung will present its SF4X node to the public in this year's VLSI Symposium. Previously known as a 4HPC node, it is designed as a 4 nm-class node with a specialized use case for HPC processors, in contrast to the standard SF4 (4LPP) node that uses 4 nm transistors designed for low-power standards applicable to mobile/laptop space. According to the VLSI Symposium schedule, Samsung is set to present more info about the paper titled "Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells."

As the brief introduction notes, "In this paper, the most upgraded 4nm (SF4X) ensuring HPC application was successfully demonstrated. Key features are (1) Significant performance +10% boosting with Power -23% reduction via advanced SD stress engineering, Transistor level DTCO (T-DTCO) and [middle-of-line] MOL scheme, (2) New HPC options: Ultra-Low-Vt device (ULVT), high speed SRAM and high Vdd operation guarantee with a newly developed MOL scheme. SF4X enhancement has been proved by a product to bring CPU Vmin reduction -60mV / IDDQ -10% variation reduction together with improved SRAM process margin. Moreover, to secure high Vdd operation, Contact-Gate breakdown voltage is improved by >1V without Performance degradation. This SF4X technology provides a tremendous performance benefits for various applications in a wide operation range." While we have no information on the reference for these claims, we suspect it is likely the regular SF4 node. More performance figures and an in-depth look will be available on Thursday, June 15, at Technology Session 16 at the symposium.

MediaTek has been unveiling some new mobile chipsets this week, but keen-eyed news outlets have noticed that the Taiwanese fabless semiconductor company is simply renaming and relaunching hardware from last year, with some tweaks here and there. Today's announcement of the Dimensity 8050 SoC was almost immediately questioned - GSMArena noticed that this "new" model was a near dead ringer, in terms of specifications, for last year's mid-range Dimensity 1300 and 1200 smartphone chipsets. There are some upgrades in terms of memory bandwidth, and MediaTek boasts that the 8050 has been updated with its sixth generation HyperEngine technology.

Alarm bells were ringing when folks realized that the much older Dimensity 8000 SoC was built on a 5 nm process - the supposedly superior (in terms of model number hierarchy) 8005 is a 6 nm chip. Last week the mobile specialist site also spotted that MediaTek's Dimensity 7050 chipset was yet another example of the smartphone tech company rolling out a "rebranding phase." The news outlet pointed out that this newly revealed mobile CPU was just a renamed Dimensity 1080 - with the original model having hit the market in November 2022. MediaTek seems to renaming several older chipsets based on TSMC's 6 nm process - it is possible that this effort is part of a company drive to clear surplus silicon.

TSMC, a Taiwanese semiconductor giant, is reportedly talking to its partners to develop an $11 billion (€10 billion) factory in Germany with the help of a few European partners. Currently assessing the plant location for Saxony in Germany, the fab wouldn't only be exclusively made by TSMC but will bring in NXP, Bosch, and Infineon that, will create a budget of around 7 billion Euros, including state subsidies, while the total budget is leaning closer to 10 billion Euros in total. However, it is essential to note that TSMC is still assessing the possibility of a Europe-based plant altogether.

Asking for as much as 40% of the total investment to be European-backed subsidies, TSMC wants to create a European facility that will be focused on a growing sector--automotive. If approved in August, the TSMC plant will become the company's first European facility and will first focus on manufacturing 28 nm chips. As one of the first significant EU Chips Act €43 billion investment, it will heavily boost European semiconductor manufacturing.

Intel Graphics employees inadvertently revealed that the company's Xe2 "Battlemage" graphics architecture is being designed for the 4 nm silicon fabrication node, which would give Intel's GPU designers a leap in transistor density and power headroom, given that TSMC 4 nm is an EUV node compared to the current 6 nm DUV node the company builds its Arc "Alchemist" GPUs on. The leak also seems to confirm that its succeeding "Celestial" graphics architecture is being designed for 3 nm. An enthusiast named gamma0burst sifted through public profiles of several Intel employees, and scored these details in their professional profile pages.

We are almost certain that Xe2 "Battlemage" is going to be built on the TSMC 4 nm node, and to a slightly lesser degree, about Xe3 "Celestial" being designed for TSMC's 3 nm N3X node. Intel roadmaps pin the debut of "Battlemage" to a 2023-2024 timeline, although this could also be a reference to the iGPU of the upcoming Core "Meteor Lake" processors that debut in the second half of 2023. Intel is highly likely to deliver "Meteor Lake" within its 2H-2023 timeline, which would mean that the mention of "2024" in the graphics technology roadmap could mean that discrete GPUs based on "Battlemage" only arrive next year.

It appears it's not only AMD that is eyeing a move to Samsung, when it comes to fabricating upcoming chips, as reports are now suggesting that Qualcomm is considering a second attempt at making flagship mobile SoCs at Samsung's foundry. However, in this case, we're talking 3 nm chips in the shape of the Snapdragon 8 Gen 4, which is expected to launch in devices sometime in 2024. This is said to be Qualcomm's first chip based on cores built by Nuvia, a company that Qualcomm acquired in 2021.

That said, Qualcomm will apparently not rely on Samsung alone, but will also be making the Snapdragon 8 Gen 4 at TSMC. This might be because of past experience with Samsung, but the report out of Taiwan, suggests that the chips made by Samsung's foundry business will be used in Samsung branded phones, whereas the TSMC made chips might end up in devices by Qualcomm's other customers. It could also be a bet for Qualcomm to try and get better pricing by both foundries or a means of hedging their bets, to see which foundry produces the better chips. Then there's the situation between the PRC and the ROC, which could potentially put Qualcomm in a situation where it has no chips, so going with Samsung could be a means of covering for all potential risk scenarios.

AMD has reportedly signed up with Samsung Electronics to shift some of its 4 nm processor silicon fabrication from TSMC. The apex Taiwan-based foundry is reportedly operating at capacity for its 4 nm-class nodes, with customers such as Apple and Qualcomm sourcing 4 nm mobile SoCs on the node, leaving AMD with limited allocation and/or bargaining power with TSMC. The company relies on 4 nm for its Ryzen 7040 series "Phoenix" mobile processors, and is in the process of adapting its design for Samsung's 4 nm-class nodes (of which there are five types for AMD to choose from).

Switching to Samsung probably gives AMD more scalability, particularly given that "Phoenix" has missed its release timeline, leaving AMD with the 5 nm + 6 nm Ryzen 7045 series "Dragon Range" MCM in the premium segments, and older 6 nm 7035 series "Rembrandt-R" in the mainstream and ultraportable segments, but nothing "apt" to compete against Intel "Raptor Lake-U" and "Raptor Lake-P." AMD has a limited window in which to ramp up "Phoenix," as Intel readies "Meteor Lake" for a 2H-2023 debut, with a focus on mobile variants.

DigiTimes has been informed that many of TSMC's customers are likely to postpone usage of the foundry's 3 nm process node into 2024 or beyond, due to a slowdown in the PC hardware market - insider sources suggest that AMD will be sticking with 4 nm and 6 nm nodes for many of its future CPU lineups. The next generation Zen 5-based family is expected to launch in 2024 - which aligns with information issued by AMD via financial reports - a roadmap (based on DigiTime's findings) points to AMD offering a range of mainstream desktop (Granite Ridge) and laptop/mobile CPUs (Fire Range).

No high-end desktop (HEDT) options are marked for release in 2024, and DigiTimes reckons that AMD is planning to release Zen 5-based Ryzen Threadripper processors in the following year. The codename for the Ryzen Threadripper 8000-series seems to be "Shimada Peak" and industry experts think that these HEDT CPUs will eventually succeed the Threadripper "Storm Peak" 7000 family (due for launch later in 2023) - a shared socket design is also a likelihood due to AMD wanting to stretch out the lifespan of mounting connection standards by avoiding costly decisions - their sTRX4/SP3r3 socket only survived for one generation.

Samsung Electronics is engaged in stiff competition with TSMC for chip manufacturing orders for 3 nm, its first semiconductor foundry node to implement GAA-FET technology, after nearly a decade of FinFET-based nodes. SF3, a 3 nm GAA-FET node, enters mass-production later this year. Samsung is claiming wafer yields in the range of 60-70% in the development phases of the node. This number is crucial to attract customers as they base their wafer orders squarely on yields first, and cost-per-wafer next.

Samsung is trying to rebuild confidence among chip designers after the 2022 controversy over its engineering "fabricating" yield numbers to customers to win their business. Samsung also stated that with 2023-2024 being dominated by 3 nm-class nodes, namely SF3 (3GAP), and its refinement the SF3P (3GAP+), the company will begin introducing its 2 nm class nodes in 2025-2026. Samsung's current customers for its 3 nm node include unnamed HPC processor designer, and a mobile AP (application processor) designer.

TSMC has confirmed to Taiwan News this weekend that a fire at its Phoenix-general area, Arizona semiconductor plant was only "limited to an outside trash chute and immediately extinguished" - the chipmaker was responding to an afternoon incident from Friday (April 28). A worker took photos of black smoke rising from a section of the brand new factory, the employee then proceeded to share their snaps online via a discussion board. A local firefighting crew extinguished the blaze soon after evacuating workers from the affected area, a preliminary investigation conducted by the emergency responders found that the fire originated from a waste/refuse chute. A root cause has not yet been identified according to the newspaper's article.

The Arizona plant was not the only TSMC location to play host to an unexpected incident this week - reports from Wednesday (April 26) state that a fire broke out during the (preceding) evening/night at a company facility in North Taiwan. No injuries or casualties were reported following a response by firefighters who had the situation under control soon after 9 pm - TSMC believes that the fire started at around 19:30. The incomplete factory is situated within Taiwan's Hsinchu Science Park, and is set to bolster the company's existing advanced 3D IC package manufacturing efforts. Part of the facility will also be setup as a component testing lab. TSMC has declared that it is conducting an investigation into the incident at its Zhunan, Miaoli County location.

Ansys and TSMC continue their long-standing technology collaboration to announce the certification of Ansys' power integrity software for TSMC's N2 process technology. The TSMC N2 process, which adopts nanosheet transistor structure, represents a major advancement in semiconductor technology with significant speed and power advantages for high performance computing (HPC), mobile chips, and 3D-IC chiplets. Both Ansys RedHawk-SC and Ansys Totem are certified for power integrity signoff on N2, including the effects of self-heat on long-term reliability of wires and transistors. This latest collaboration builds on the recent certification of the Ansys platform for TSMC's N4 and N3E FinFLEX processes.

"TSMC works closely with our Open Innovation Platform (OIP) ecosystem partners to help our mutual customers achieve the best design results with the full stack of design solutions on TSMC's most advanced N2 process," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our latest collaboration with Ansys RedHawk-SC and Totem analysis tools allows our customers to benefit from the significant power and performance improvements of our N2 technology while ensuring predictively accurate power and thermal signoff for the long-term reliability of their designs."

TSMC today showcased its latest technology developments at its 2023 North America Technology Symposium, including progress in 2 nm technology and new members of its industry-leading 3 nm technology family, offering a range of processes tuned to meet diverse customer demands. These include N3P, an enhanced 3 nm process for better power, performance and density, N3X, a process tailored for high performance computing (HPC) applications, and N3AE, enabling early start of automotive applications on the most advanced silicon technology.

With more than 1,600 customers and partners registered to attend, the North America Technology Symposium in Santa Clara, California is the first of the TSMC's Technology Symposiums around the world in the coming months. The North America symposium also features an Innovation Zone spotlighting the exciting technologies of 18 emerging start-up customers.

Cadence Design Systems, Inc. today announced that it has collaborated with TSMC to optimize the Cadence Virtuoso platform for the 79 GHz mmWave design reference flow on TSMC's N16 process. With this latest development in Cadence and TSMC's long history of collaboration, joint customers now have access to a complete 79 GHz mmWave design reference flow on the N16 process for developing optimized, highly reliable, next-generation RFIC designs for use in radar, 5G and other wireless applications for the mobile, automotive, healthcare and aerospace markets. Customers have already started using the corresponding TSMC PDKs for RFIC design work.

The Cadence RFIC solution that supports TSMC's N16 process technology features automation capabilities to help customers spend less time integrating critical RF functionality into their designs. The solution supports all aspects of RF design, including passive device modeling, assisted layout automation, block-level optimization and EM signoff simulations.

Accelerating the integration of heterogeneous dies to enable the next level of system scalability and functionality, Synopsys, Inc. (Nasdaq: SNPS) has strengthened its collaboration with TSMC and Ansys for multi-die system design and manufacturing. Synopsys provides the industry's most comprehensive EDA and IP solutions for multi-die systems on TSMC's advanced 7 nm, 5 nm and 3 nm process technologies with support for TSMC 3DFabric technologies and 3Dblox standard. The integration of Synopsys implementation and signoff solutions and Ansys multi-physics analysis technology on TSMC processes allows designers to tackle the biggest challenges of multi-die systems, from early exploration to architecture design with signoff power, signal and thermal integrity analysis.

"Multi-die systems provide a way forward to achieve reduced power and area and higher performance, opening the door to a new era of innovation at the system-level," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "Our long-standing collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys and Ansys gives mutual customers a faster path to multi-die system success through a full spectrum of best-in-class EDA and IP solutions optimized for our most advanced technologies."

TSMC today announced consolidated revenue of NT$508.63 billion, net income of NT$206.99 billion, and diluted earnings per share of NT$7.98 (US$1.31 per ADR unit) for the first quarter ended March 31, 2023. Year-over-year, first quarter revenue increased 3.6% while net income and diluted EPS both increased 2.1%. Compared to fourth quarter 2022, first quarter results represented an 18.7% decrease in revenue and a 30.0% decrease in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, first quarter revenue was $16.72 billion, which decreased 4.8% year-over-year and decreased 16.1% from the previous quarter. Gross margin for the quarter was 56.3%, operating margin was 45.5%, and net profit margin was 40.7%. In the first quarter, shipments of 5-nanometer accounted for 31% of total wafer revenue; 7-nanometer accounted for 20%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 51% of total wafer revenue.

EdgeCortix Inc., the innovative Edge Artificial Intelligence (AI) Platform company, focused on delivering class-leading compute efficiency and ultra-low latency for AI inference; announced, it is shipping its industry leading, energy-efficient, turn-key, AI co-processor, branded as the EdgeCortix SAKURA-I, to its global Early Access Program members.

"We are very pleased to be announcing the fulfillment of our first-generation semiconductor solution, the EdgeCortix SAKURA-I AI co-processor. Designed and engineered in Japan, SAKURA-I features up to 40 trillion operations per second (TOPs) of dedicated AI performance at sub-10 watts of power consumption.", said Sakyasingha Dasgupta, CEO and Founder of EdgeCortix, "We are delivering a complete Edge AI platform to our Early Access Program members, comprising both software and hardware solutions, which includes our recently updated MERA software suite. Program members include numerous global industry leading enterprise customers across both the commercial and defense sectors. We developed the EdgeCortix Early Access Program (EAP) with a focus on offering customers the opportunity to assess EdgeCortix's products and services at scale, by deploying them within their own complex, heterogeneous environments. The goal of the EAP offering is three-fold: showcasing the ease of integration into customer's existing heterogeneous systems, enabling customers to prove-out the effectiveness and efficiency of EdgeCortix solutions versus competing products and facilitating a direct dialog with EdgeCortix product management, enabling tailor-made fit in certain cases."

A technology tipster has been dropping multiple tidbits this week about Qualcomm's upcoming Snapdragon 8 Gen 3 mobile chipset - this follows a leak (from a different source, going back to mid-April) about the next generation Adreno 750 GPU getting tuned up for a battle against Apple's Bionic A17 in terms of graphics benchmarks. The latest leak points to the GPU being clocked at 900 MHz, rather than the rumored higher figure of 1.0 GHz speed (garnered from tests at Qualcomm's labs). The focus has now turned to the next generation flagship Snapdragon's CPU aspect, with information emerging about core clock speeds and multiple cluster configurations.

Revegnus suggests that the Snapdragon 8 Gen 3 (SD8G3) chipset will be packing a large primary core in the shape of Arm's Cortex-X4 CPU with a reported maximum clock speed of 3.40 GHz. Leaks from the past have posited that the SD8G3 would feature a fairly standard 1x Large + 5x Big + 2x Small CPU core layout (with clocks predicted to be: large Cortex X4 at 3.2 GHz, big Cortex-A720 at 3.0 GHz, and small Cortex-A520 at 2.0 GHz). An insider source has provided Revegnus with additional information about two different CPU core configurations - 1+5+2 and 2+4+2 - it is theorized that smartphone manufacturers will be offered the latter layout as an exclusive option for special edition flagship phones. The more powerful 2+4+2 variant is said to sacrifice a big core (A720) in favor of a dual Cortex X4 headliner, although the resultant thermal output of twin large cores could prove to be problematic.

Ace investor Warren Buffett held a US $4 billion stake in TSMC as of January, and has reportedly sold all of it over a period between February to April, 2023. The sale has triggered alarm bells in some circles over the possible reasons someone like Buffett—who wrote the book on long-term strategic investments—would liquidate their holdings. The ongoing slump in the semiconductor industry, and economic recession in the West, seem to cut it as valid reasons. Fortune Magazine has a more grim theory.

Fortune writes that the possibility of a cross-straits conflict between Taiwan and China is at an all-time high, and this could have been a consideration for Buffett to sell his TSMC stake. It is assessed that a Chinese invasion of Taiwan now—with global chip supply chains not yet having attained "resilience"—would minimize economic reprisals on China from the West. The other side of the story could be that the economic slump, in combination with semiconductor manufacturing facing its biggest technological challenges as it approaches the 20-angstrom realm, may have soured TSMC's long-term prospects for Buffett.

Early details of MediaTek's next generation mobile chipset have emerged this week, courtesy of renowned leaker Digital Chat Station via their blog on Weibo. The successor to MediaTek's current flagship Dimensity 9200 mobile chipset will likely be called "Dimensity 9300" - a very imaginative bump up in numbering - with smartphone brand Vivo involved as a collaborator. The tipster thinks that the fabless semiconductor company has contracted with TSMC for fabrication of the Dimensity 9300 chipset - and the foundry's N4P process has been selected by MediaTek, which could provide a bump in generational performance when compared to the older 4 nm and 5 nm standards used for past Dimensity SoC ranges. It should be noted that the current generation Dimensity 9200 chipset is presently manufactured via TSMC's N4P process.

MediaTek is seeking to turnaround its fortunes in the area of flagship mobile chipsets - industry watchdogs have cited a limited uptake of the Taiwanese company's Dimensity 9200 SoC as a motivating factor in the creation of a very powerful successor. Digital Chat Station suggests that the upcoming 9300 model will pack enough of a hardware punch to rival Qualcomm's forthcoming Snapdragon 8 Gen 3 SoC - both chipsets are touted to release within the same time period of late 2023. According to previous speculation, Qualcomm has also contracted with TSMC's factory to pump out the Snapdragon 8 Gen 3 via the N4P (4 nm) process.

According to The Information, Microsoft has been working on creating custom processors for processing AI with a project codenamed Athena. Based on TSMC's 5 nm process, these chips are designed to accelerate AI workloads and scale to hundreds or even thousands of chips. With the boom of Large Language Models (LLMs) that require billions of parameters, training them requires a rapid increase of computational power to a point where companies purchase hundreds of thousands of GPUs from the likes of NVIDIA. However, creating custom processors is a familiar feat for a company like Microsoft. Hyperscalers like AWS, Google, and Meta are already invested in the creation of processors for AI training, and Microsoft is just joining as well.

While we don't have much information about these processors, we know that Microsoft started the project in 2019, and today these processors are in the hands of select employees of Microsoft and OpenAI that work with AI projects and need computational horsepower. Interestingly, some projections assume that if Microsoft could match NVIDIA's GPU performance, the cost would only be a third of NVIDIA's offerings. However, it is challenging to predict that until more information is provided. Microsoft plans to make these chips more widely available as early as next year; however, there is no specific information on when and how, but Azure cloud customers would be the most logical place to start.

TrendForce reports that the US Department of Commerce recently released details regarding its CHIPS and Science Act, which stipulates that beneficiaries of the act will be restricted in their investment activities—for more advanced and mature processes—in China, North Korea, Iran, and Russia for the next ten years. The scope of restrictions in this updated legislation will be far more extensive than the previous export ban, further reducing the willingness of multinational semiconductor companies to invest in China for the next decade.

CHIPS Act will mainly impact TSMC; and as the decoupling of the supply chain continues, VIS and PSMC capture orders rerouted from Chinese foundries
In recent years, the US has banned semiconductor exports and passed the CHIPS Act, all to ensure supply chains decoupling from China. Initially, bans on exports were primarily focused on non-planar transistor architecture (16/14 nm and more advanced processes). However, Japan and the Netherlands have also announced that they intend to join the sanctions, which means key DUV immersion systems, used for producing both sub-16 nm and 40/28 nm mature processes, are likely to be included within the scope of the ban as well. These developments, in conjunction with the CHIPS Act, mean that the expansion of both Chinese foundries and multinational foundries in China will be suppressed to varying degrees—regardless of whether they are advanced or mature processes.

An online tipster, posting on the Chinese blog site Weibo, has let slip that Qualcomm's upcoming Snapdragon 8 Gen 3 mobile chipset is touted to pack some hefty graphical capabilities. The suggested Adreno "750" smartphone and tablet GPU is touted to offer a 50% increase over the present generation Adreno 740 - as featured on the recently released and cutting-edge Snapdragon 8 Gen 2 chipset. The current generation top-of-the-range Snapdragon is no slouch when it comes to graphics benchmarks, where it outperforms Apple's prime contender - the Bionic A16 SoC.

The Snapdragon 8 Gen 3 SoC is expected to launch in the last quarter of 2023, but details of the flagship devices that it will power are non-existent at the time of writing. The tipster suggests that Qualcomm has decided to remain on TSMC's 4 nm process for its next generation mobile chipset - perhaps an all too safe decision when you consider that Apple has upped the stakes with the approach of its Bionic A17 SoC. It has been reported that the Cupertino, California-based company has chosen to fabricate via TSMC's 3 nm process, although the Taiwanese foundry is said to be struggling with its N3 production line. The engineers at Qualcomm's San Diego headquarters are alleged to be experimenting with increased clock speeds running on the next gen Adreno GPU - as high as 1.0 GHz - in order to eke out as much performance as possible, in anticipation of besting the Bionic A17 in graphics benchmarks. The tipster theorizes that Qualcomm will still have a hard time matching Apple in terms of pure CPU throughput, so the consolation prize will lie with a superior GPU getting rigged onto the Snapdragon 8 Gen 3.

Reports from supply chain partners suggests that Apple cut off production of their current generation M2 SoC lineup in the months of January and February following significantly decreased demand for Mac computers containing the chips. The details trace back to partners in Outsourced Semiconductor Package Test, or OSAT, which is many different companies in the supply chain that contribute to assembly and testing of the final packaged SoC. OSAT partners claim they received zero M2 wafers from TSMC during both months, and that shipments have only resumed at half of the previous capacity in the month of March. The breadth of this shutdown touched many different suppliers, from the packaging facilities in Korea, to the solder ball suppliers in Taiwan, the TIM suppliers in Germany, and die underfill material suppliers from Japan. Many of these parts can be specific to the type of chip being produced, as M2 features a different packaging method to Apple's normal A-Series mobile SoCs; a lack of M2 silicon led to a full shutdown of this supply chain. An industry insider for Amcona states, "It is impossible to do other packaging work on the M2 line, the so-called 'Apple line' installed in Amcona chip packs."

In their Q1 2023 earnings conference Apple reported a sharp revenue drop in Mac sales from $10.85B down to $7.74B. "The PC market is facing a very challenging situation," stated Tim Cook, Apple's CEO, "I think we have an advantage with silicon but it will be very difficult in the short term." Apple began production of M2 well over a year ago when demand for Apple silicon equipped MacBooks was still sky high, and likely had large reserves of finished chips and machines stockpiled for the launch of M2 Pro and M2 Max in January. With demand dipping up to the launch of the new MacBook models it would certainly justify slowing down production, but outright halting it for multiple months suggests demand far undershot Apple's expectation.

Intel has awarded TSMC with some big contracts for future manufacturing of next generation GPUs, according to Taiwan's Commercial Times. As previously covered on TPU, the second generation Battlemage graphics processing units will get fabricated via a 4 nm process. According to insider sources at both partnering companies, Intel is eyeing a release date in the second half of 2024 for this Xe2-based architecture. The same sources pointed to the third generation Celestial graphics processing units being ready in time for a second half of 2026 launch window. Arc Celestial, which is based on the Xe3 architecture, is set for manufacture in the coming years courtesy of TSMC's N3X (3 nm) process node.

One of the sources claim that Intel is quietly confident about its future prospects in the GPU sector, despite mixed critical and commercial reactions to the first generation line-up of Arc Alchemist discrete graphics cards. The company is said to be anticipating great demand for more potent versions of its graphics products in the future, and internal restructuring efforts have not dulled the will of a core team of engineers. The restructuring process resulted in the original AXG graphics division being divided into two sub-groups - CCG and DCAI. The pioneer of the entire endeavor, Raja Koduri, departed Intel midway through last month, to pursue new opportunities with an AI-focused startup.