TSMC today announced that its Chairman Dr. Mark Liu has decided not to seek the nomination of TSMC board membership for the next term and will retire from the Company after the 2024 Annual Shareholders Meeting. TSMC's Nominating, Corporate Governance and Sustainability Committee of the board recommends vice chairman Dr. C.C. Wei succeed as the company's next Chairman, subject to the election of the incoming board in June 2024.

Dr. Mark Liu joined TSMC in 1993 and assumed the role of chairman after Founder Dr. Morris Chang's retirement since June 2018. During his tenure, Dr. Mark Liu has reaffirmed the Company's commitment to its mission and focused on enhancing corporate governance and competitiveness particularly in technology leadership, digital excellence, and global footprint.

Last week at the IEEE International Electron Devices Meeting, the world's top-three semiconductor foundries, TSMC, Intel (Intel Foundry Services or IFS), and Samsung Electronics, demonstrated their respective approaches to an evolutionary new transistor device called the CFET, or complementary field-effect transistors. A CFET is a kind of 3-D transistor that stacks both kinds of FETs needed for CMOS logic. All three fabs are transitioning from FinFET to nanosheets, or GAAFETs (gates all-around FETs).

While FinFETs use vertical silicon fins, with gates controlling the flow of current through them; while in a nanosheet, the vertical fin is cut into a set of ribbons, each surrounded by the gate. A CFET is essentially a taller nanosheet device in which uses half of the available ribbons for one device, and the other half for another. This device builds the two types of transistor, nFETs and pFETs on top of each other, in an integrated process. CFETs are the evolutionary next step to conventional GAAFETs, and it's predicted to enter mass production only 7-10 years from now. By that time, the industry will begin to feel the pushback from technological barriers preventing development beyond 10 angstrom-class nodes.

AMD's upcoming server processor, the 5th Gen EPYC "Turin," has been pictured as an engineering sample is probably being evaluated by the company's data-center or cloud customers. The processor has a mammoth core-count of 192-core/384-thread in its high-density cloud-focused variant that uses "Zen 5c" CPU cores. Its regular version that uses larger "Zen 5" cores that can sustain higher clock speeds, also comes with a fairly high core-count of 128-core/256-thread, up from the 96-core/192-thread of the "Zen 4" based EPYC "Genoa."

The EPYC "Turin" server processor based on "Zen 5" comes with an updated sIOD (server I/O die), surrounded by as many as 16 CCDs (CPU complex dies). AMD is expected to build these CCDs on the TSMC N4P foundry node, which is a more advanced version of the TSMC N4 node the company currently uses for its "Phoenix" client processors, and the TSMC N5 node it uses for its "Zen 4" CCD. TSMC claims that the N4P node offers an up to 22% improvement in power efficiency over N5, as well as a 6% increase in transistor density. Each of the "Zen 5" CCDs is confirmed to have 8 CPU cores sharing 32 MB L3 cache memory. A total of 16 such CCDs add up to the processor's 128-core/256-thread number. The high-density "Turin" meant for cloud data-centers, is a whole different beast.

TSMC's 2 nm-class foundry node, dubbed N2, will enter mass production only in 2025, a report by the Financial Times says. The premier Taiwan-based foundry has been reportedly showcasing TSMC N2 to its biggest customer for advanced nodes, Apple. The node will likely power Apple's in-house silicon that drives the iPhone 17 Pro and Pro Max devices that are slated for 2025. This implies that the current 3 nm class nodes from TSMC will continue to power Apple silicon into 2024 and its iPhone 16 Pro/Pro Max.

The current Apple A17 Pro and M3 chips powering the iPhone 15 Pro/Max and the H2-2023 Macs are based on TSMC's N3 node, with a 183 MTr/mm² transistor density. TSMC has four other 3 nm-class nodes, with the N3E node that just entered mass production to offer a jump to 215.6 MTr/mm², and its 2024 successor, the N3P, pushing transistor densities further up to 224 MTr/mm². TSMC's first 2 nm-class node, the N2, offers a jump to around 259 MTr/mm², which makes the N3P a nice halfway point for Apple between the N3 and N2, for its 2024 silicon.

Sony is developing the PlayStation 5 Pro console that targets higher refresh-rate gaming at 4K Ultra HD, or higher in-game eye-candy, given its faster hardware. Details about the console are few and far between, given its late-2024 tentative release, but by now the company would have co-developed its semi-custom SoC, so it could spend the next year extensively testing and optimizing it, before mass production in the 2-3 quarters leading up to the launch. Kepler_L2 and Tom Henderson on Twitter are fairly reliable sources for PlayStation hardware leaks, and piecing their recent posts together, VideoCardz compiled the most probable specs of the SoC at the heart of the PlayStation 5 Pro.

The semi-custom SoC powering the PlayStation 5 Pro is co-developed by Sony Computer Entertainment (SCE) and AMD; and is codenamed "Viola." The monolithic chip is built on the TSMC N4P foundry node (4 nm EUV), which is a big upgrade from the 7 nm DUV node on which the "Oberon" SoC powering the original PlayStation 5, and 6 nm DUV node powering the "Oberon Plus" SoC of the refreshed PS5, are based on. Sony is leaving the CPU component largely untouched, it is an 8-core/16-thread unit based on the "Zen 2" microarchitecture, spread across two 4-core CCXs. The CPU has a maximum boost frequency of 4.40 GHz, dialed up from the 3.50 GHz maximum boost of "Oberon." The iGPU is where all the magic happens.

Huawei's subsidiary HiSilicon has made significant strides in the independent R&D of AI chips, launching the next-gen Ascend 910B. These chips are utilized not only in Huawei's public cloud infrastructure but also sold to other Chinese companies. This year, Baidu ordered over a thousand Ascend 910B chips from Huawei to build approximately 200 AI servers. Additionally, in August, Chinese company iFlytek, in partnership with Huawei, released the "Gemini Star Program," a hardware and software integrated device for exclusive enterprise LLMs, equipped with the Ascend 910B AI acceleration chip, according to TrendForce's research.

TrendForce conjectures that the next-generation Ascend 910B chip is likely manufactured using SMIC's N+2 process. However, the production faces two potential risks. Firstly, as Huawei recently focused on expanding its smartphone business, the N+2 process capacity at SMIC is almost entirely allocated to Huawei's smartphone products, potentially limiting future capacity for AI chips. Secondly, SMIC remains on the Entity List, possibly restricting access to advanced process equipment.

NVIDIA CFO Colette Kress, responding to a question in the Q&A session of the recent UBS Global Technology Conference, hinted at the possibility of NVIDIA onboarding a third semiconductor foundry partner besides its current TSMC and Samsung, with the implication being Intel Foundry Services (IFS). "We would love a third one. And that takes a work of what are they interested in terms of the services. Keep in mind, there is other ones that may come to the U.S. TSMC in the U.S. may be an option for us as well. Not necessarily different, but again in terms of the different region. Nothing that stops us from potentially adding another foundry."

NVIDIA currently sources its chips from TSMC and Samsung. It uses the premier Taiwanese fab for its latest "Ada" GPUs and "Hopper" AI processors, while using Samsung for its older generation "Ampere" GPUs. The addition of IFS as a third foundry partner could improve the company's supply-chain resilience in an uncertain geopolitical environment; given that IFS fabs are predominantly based in the US and the EU.

AMD today announced the new Ryzen 8040 mobile processor series codenamed "Hawk Point." These chips are shipping to notebook manufacturers now, and the first notebooks powered by these should be available to consumers in Q1-2024. At the heart of this processor is a significantly faster neural processing unit (NPU), designed to accelerate AI applications that will become relevant next year, as Microsoft prepares to launch Windows 12, and software vendors make greater use of generative AI in consumer applications.

The Ryzen 8040 "Hawk Point" processor is almost identical in design and features to the Ryzen 7040 "Phoenix," except for a faster Ryzen AI NPU. While this is based on the same first-generation XDNA architecture, its NPU performance has been increased to 16 TOPS, compared to 10 TOPS of the NPU on the "Phoenix" silicon. AMD is taking a whole-of-silicon approach to AI acceleration, which includes not just the NPU, but also the "Zen 4" CPU cores that support the AVX-512 VNNI instruction set that's relevant to AI; and the iGPU based on the RDNA 3 graphics architecture, with each of its compute unit featuring two AI accelerators, components that make the SIMD cores crunch matrix math. The whole-of-silicon performance figures for "Phoenix" is 33 TOPS; while "Hawk Point" boasts of 39 TOPS. In benchmarks by AMD, "Hawk Point" is shown delivering a 40% improvement in vision models, and Llama 2, over the Ryzen 7040 "Phoenix" series.

TrendForce's research indicates a dynamic third quarter for the global foundry industry, marked by an uptick in urgent orders for smartphone and notebook components. This surge was fueled by healthy inventory levels and the release of new iPhone and Android devices in 2H23. Despite persisting inflation risks and market uncertainties, these orders were predominantly executed as rush orders. Additionally, TSMC and Samsung's high-cost 3 nm manufacturing process had a positive impact on revenues, driving the 3Q23 value of the top ten global foundries to approximately US$28.29 billion—a 7.9% QoQ increase.

Looking ahead to 4Q23, the anticipation of year-end festive demand is expected to sustain the inflow of urgent orders for smartphones and laptops, particularly for smartphone components. Although the end-user market is yet to fully recover, pre-sales season stockpiling for Chinese Android smartphones appears to be slightly better than expected, with demand for mid-to-low range 5G and 4G phone APs and continued interest in new iPhone models. This scenario suggests a continued upward trend for the top ten global foundries in Q4, potentially exceeding the growth rate seen in Q3.

Apple has announced a partnership deal with Amkor, one of the leading chip packaging and testing manufacturers, which will build a two billion US Dollar silicon packaging facility in Peoria, Arizona. Being the only US-based OSAT (outsourced semiconductor assembly and test) provider, Amkor has decided to invest its funds and apply for the CHIPS Act, hoping to get a part of the funding from the US government's grant budget. The state-of-the-art facility in Arizona will feature over 500,000 square feet (46,452 square meters) of cleanroom space for packaging and testing chips. Using Amkor's latest technologies, the plant will support advanced computing, automotive, and communications chip packaging. It is tailored to meet the capacity needs of major customer Apple starting in 2025-2026. Apple will be the largest customer, with the Amkor facility packaging Apple-designed chips produced at the nearby TSMC wafer fabrication plant.

Building a chip packaging facility in the US with advanced packaging types means that the domestic manufacturing of advanced silicon is now possible across almost the entire supply chain, with OSAT now being present on US soil as well. In the initial phase, this partnership will enable domestic advanced packaging capabilities for leading-edge chips down to 3 nm nodes, which Apple plans to utilize for its A and M series of processors. Along with the creation of an estimated 2,000 local jobs, the investment serves as a boost to the local economy as well. Additionally, Amkor is TSMC's strategic partner, meaning future designs and packaging will cooperate without any delays.

NVIDIA's most recent FY3Q24 financial reports reveal record-high revenue coming from its data center segment, driven by escalating demand for AI servers from major North American CSPs. However, TrendForce points out that recent US government sanctions targeting China have impacted NVIDIA's business in the region. Despite strong shipments of NVIDIA's high-end GPUs—and the rapid introduction of compliant products such as the H20, L20, and L2—Chinese cloud operators are still in the testing phase, making substantial revenue contributions to NVIDIA unlikely in Q4. Gradual shipments increases are expected from the first quarter of 2024.

The US ban continues to influence China's foundry market as Chinese CSPs' high-end AI server shipments potentially drop below 4% next year
TrendForce reports that North American CSPs like Microsoft, Google, and AWS will remain key drivers of high-end AI servers (including those with NVIDIA, AMD, or other high-end ASIC chips) from 2023 to 2024. Their estimated shipments are expected to be 24%, 18.6%, and 16.3%, respectively, for 2024. Chinese CSPs such as ByteDance, Baidu, Alibaba, and Tencent (BBAT) are projected to have a combined shipment share of approximately 6.3% in 2023. However, this could decrease to less than 4% in 2024, considering the current and potential future impacts of the ban.

MediaTek today announced the Dimensity 8300, a power-efficient chipset designed for premium 5G smartphones. As the newest SoC in the Dimensity 8000 lineup, this chipset combines generative AI capabilities, low-power savings, adaptive gaming technology, and fast connectivity to bring flagship-level experiences to the premium 5G smartphone segment.

Based on TSMC's 2nd generation 4 nm process, the Dimensity 8300 has an octa-core CPU with four Arm Cortex-A715 cores and four Cortex-A510 cores built on Arm's latest v9 CPU architecture. With this powerful core configuration, the Dimensity 8300 boasts 20% faster CPU performance and 30% peak gains in power efficiency compared to the previous generation chipset. Additionally, the Dimensity 8300's Mali-G615 MC6 GPU upgrade provides up to 60% greater performance and 55% better power efficiency. Plus, the chipset's impressive memory and storage speeds ensure users can enjoy smooth and dynamic experiences in gaming, lifestyle applications, photography, and more.

Ansys has collaborated with TSMC and Microsoft to validate a joint solution for analyzing mechanical stresses in multi-die 3D-IC systems manufactured with TSMC's 3DFabric advanced packaging technologies. This collaborative solution gives customers added confidence to address novel multiphysics requirements that improve the functional reliability of advanced designs using TSMC's 3DFabric, a comprehensive family of 3D silicon stacking and advanced packaging technologies.

Ansys Mechanical is the industry-leading finite element analysis software used to simulate mechanical stresses caused by thermal gradients in 3D-ICs. The solution flow has been proven to run efficiently on Microsoft Azure, helping to ensure fast turn-around times with today's very large and complex 2.5D/3D-IC systems.

During its Ignite conference, Microsoft introduced a duo of custom-designed silicon made to accelerate AI and excel in cloud workloads. First of the two is Microsoft's Azure Cobalt 100 CPU, a 128-core design that features a 64-bit Armv9 instruction set, implemented in a cloud-native design that is set to become a part of Microsoft's offerings. While there aren't many details regarding the configuration, the company claims that the performance target is up to 40% when compared to the current generation of Arm servers running on Azure cloud. The SoC has used Arm's Neoverse CSS platform customized for Microsoft, with presumably Arm Neoverse N2 cores.

The next and hottest topic in the server space is AI acceleration, which is needed for running today's large language models. Microsoft hosts OpenAI's ChatGPT, Microsoft's Copilot, and many other AI services. To help make them run as fast as possible, Microsoft's project Athena now has the name of Maia 100 AI accelerator, which is manufactured on TSMC's 5 nm process. It features 105 billion transistors and supports various MX data formats, even those smaller than 8-bit bit, for maximum performance. Currently tested on GPT 3.5 Turbo, we have yet to see performance figures and comparisons with competing hardware from NVIDIA, like H100/H200 and AMD, with MI300X. The Maia 100 has an aggregate bandwidth of 4.8 Terabits per accelerator, which uses a custom Ethernet-based networking protocol for scaling. These chips are expected to appear in Microsoft data centers early next year, and we hope to get some performance numbers soon.

MediaTek today announced the Dimensity 9300, its newest flagship mobile chip with a one-of-a-kind All Big Core design. The unique configuration combines extreme performance with MediaTek's industry-leading power efficiency to deliver unmatched user experiences in gaming, video capture and on-device generative AI processing.

"The Dimensity 9300 is MediaTek's most powerful flagship chip yet, bringing a huge boost in raw computing power to flagship smartphones with our groundbreaking All Big Core design," said Joe Chen, President at MediaTek. "This unique architecture, combined with our upgraded on-chip AI Processing Unit, will usher in a new era of generative AI applications as developers push the limits with edge AI and hybrid AI computing capabilities."

The Chinese semiconductor industry is advancing, and interestingly, it is growing rapidly under sanctions, even with the blacklisting of companies by the US government. China's semiconductor industry is mainly represented by companies like Semiconductor Manufacturing International Corp (SMIC) and Huawei Technologies, who are leading the investment and progress in both chip manufacturing and chip design. According to the latest interview with Bloomberg, former TSMC Vice President Burn J. Lin said that the US government and its sanctions can not stop the advancement of Chinese semiconductor companies. Currently, Lin notes that SMIC and Huawei can use older machinery to produce more advanced chips.

Even so, SMIC could progress to 5 nm technology using existing equipment, particularly with scanners and other machinery from ASML. Development under sanctions would also force China to experiment with new materials and other chip packaging techniques that yield higher performance targets. SMIC has already developed a 7 nm semiconductor manufacturing node, which Huawei used for its latest Mate 60 Pro smartphone, based on Huawei's custom HiSilicon Kirin 9000S chip. Similarly, the transition is expected to happen to the 5 nm node as well, and it is only a matter of time before we see other nodes appear. "It is just not possible for the US to completely prevent China from improving its chip technology," noted Burn J. Lin.

Moore Threads Technology (MTT), a Chinese GPU manufacturer, is reportedly testing its next-generation graphics processors for client PCs and data centers. The products under scrutiny are the MTT S90 for client/gaming computers and the MTT S4000 for data centers. Characterized by their Device IDs, 0301 and 0323, this could imply that these GPUs belong to MTT's 3rd generation GPU lineup. While few details about these GPUs are available, the new Device IDs suggest a possible introduction of a novel microarchitecture following the MTT Chunxiao GPU series. The current generation Chunxiao series, featuring the MTT S70, MTT S80, and MTT S3000, failed to compete effectively with AMD, Intel, and NVIDIA GPUs.

Thanks to @Löschzwerg who found the Device Hunt submission, we see hardware identifiers in PCI ID and USB ID repositories earlier than launch, as this often signals the testing of new chips or drivers by various companies. In the case of MTT, the latest developments are complicated by its recent inclusion on the U.S. Entity List, limiting its access to US-made technologies. This introduces a problem for the company, as they can't access TSMC's facilities for chip production, and will have to turn to domestic production in the likely case, with SMIC being the only leading option to consider.

TSMC today announced consolidated revenue of NT$546.73 billion, net income of NT$211.00 billion, and diluted earnings per share of NT$8.14 (US$1.29 per ADR unit) for the third quarter ended September 30, 2023. Year-over-year, third quarter revenue decreased 10.8% while net income and diluted EPS both decreased 24.9%. Compared to second quarter 2023, third quarter results represented a 13.7% increase in revenue and a 16.1% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, third quarter revenue was $17.28 billion, which decreased 14.6% year-over-year and increased 10.2% from the previous quarter. Gross margin for the quarter was 54.3%, operating margin was 41.7%, and net profit margin was 38.6%. In the third quarter, shipments of 3-nanometer accounted for 6% of total wafer revenue; 5-nanometer accounted for 37%; 7-nanometer accounted for 16%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 59% of total wafer revenue.

Socionext today announced a collaboration with Arm and TSMC for the development of an innovative power-optimized 32-core CPU chiplet in TSMCʼs 2 nm silicon technology, delivering scalable performance for hyperscale data center server, 5/6G infrastructure, DPU and edge-of- network markets.

The engineering samples are targeted to be available in 1H2025. This advanced CPU chiplet proof-of-concept using Arm Neoverse CSS technology is designed for single or multiple instantiations within a single package, along with IO and application-specific custom chiplets to optimize performance for a variety of end applications.

Ever since the creation of A64FX for the Fugaku supercomputer, Fujitsu has been plotting the development of next-generation CPU design for accelerating AI and general-purpose HPC workloads in the data center. Codenamed Monaka, the CPU is the latest creation for TSMC's 2 nm semiconductor manufacturing node. Based on Armv9-A ISA, the CPU will feature up to 150 cores with Scalable Vector Extensions 2 (SVE2), so it can process a wide variety of vector data sets in parallel. Using a 3D chiplet design, the 150 cores will be split into different dies and placed alongside SRAM and I/O controller. The current width of the SVE2 implementation is unknown.

The CPU is designed to support DDR5 memory and PCIe 6.0 connection for attaching storage and other accelerators. To bring cache coherency among application-specific accelerators, CXL 3.0 is present as well. Interestingly, Monaka is planned to arrive in FY2027, which starts in 2026 on January 1st. The CPU will supposedly use air cooling, meaning the design aims for power efficiency. Additionally, it is essential to note that Monaka is not a processor that will power the post-Fugaku supercomputer. The post-Fugaku supercomputer will use post-Monaka design, likely iterating on the design principles that Monaka uses and refining them for the launch of the post-Fugaku supercomputer scheduled for 2030. Below are the slides from Fujitsu's presentation, in Japenese, which highlight the design goals of the CPU.

According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That said, TSMC has at least five known 3 nm nodes, of which two should be in production by now, assuming N3E has proved to be reliable enough to kick off. Samsung on the other hand has three known 3 nm nodes, with only one in production so far, called 3GAE.

ChosunBiz reports that neither company is getting the kind of yields that you'd expect from a node that should have been in volume production for around a year by now, with Samsung apparently being somewhat better than TSMC. At 60 and 50 percent respectively, neither Samsung nor TSMC are anywhere near decent yields. Anything below 70 percent is considered very poor and even the 60 percent claim in Samsungs case, is apparently limited to some kind of Chinese mining ASIC and doesn't include the SRAM you find in most modern processors. ChosunBiz also mentions a source familiar with Samsung's foundry business who mentions a yield closer to 50 percent for the company. The same source also mentions that Samsung needs to reach at least 70 percent yield to be able to attract major customers to its 3 nm node.

AMD is preparing to launch its first APUs on the Socket AM5 desktop platform, with the Ryzen 7000G series. While the company has standardized integrated graphics with the Ryzen 7000 series, it does not consider the regular Ryzen 7000 series "Raphael" processors as APUs. AMD considers APUs to be processors with overpowered iGPUs that are fit for entry-mainstream PC gaming. As was expected for a while now, for the Ryzen 7000G series, AMD is tapping into its 4 nm "Phoenix" monolithic silicon, the same chip that powers the Ryzen 7040 series mobile processors. Proof of "Phoenix" making its way to desktop surfaced with CPU support lists for the latest AGESA SMUs (system management units) compiled by Reous, with the AGESA ComboAM5PI 1.0.8.0 listing support for "Raphael," as well as "Phoenix." Another piece of evidence was an ASUS B650 motherboard support page that listed a UEFI firmware update encapsulating 1.0.8.0, which references an "upcoming CPU."

Unlike "Raphael" and "Dragon Range," "Phoenix" is a monolithic processor die built on the TSMC 4 nm foundry node. Its CPU is based on the latest "Zen 4" microarchitecture, and features an 8-core/16-thread configuration, with 1 MB of L2 cache per core, and 16 MB of shared L3 cache. The star attraction here is the iGPU, which is based on the RDNA3 graphics architecture, meets the DirectX 12 Ultimate feature requirements, and is powered by 12 compute units worth 768 stream processors. Unlike "Raphael," the "Phoenix" silicon is known to feature an older PCI-Express Gen 4 root complex, with 24 lanes, so you get a PCI-Express 4.0 x16 PEG slot, one CPU-attached M.2 NVMe slot limited to Gen 4 x4, and a 4-lane chipset bus. "Phoenix" features a dual-channel (4 sub-channel) DDR5 memory controller, with native support for DDR5-5600. A big unknown with the Ryzen 7000G desktop APUs is whether they retain the Ryzen AI feature-set from the Ryzen 7040 series mobile processors.

TrendForce research indicates that in 1H23, the utilization rate of 8-inch production capacity primarily benefited from sporadic inventory restocking orders for Driver ICs in the second quarter. Additionally, wafer foundries initiated pricing strategies to encourage clients into early orders, offering solid backup. However, in 2H23, persistent macroeconomic and inventory challenges led to the evaporation of an anticipated demand surge.

Meanwhile, stockpiles in automotive and industrial control segments grew after meeting initial shortages, tempering demand. Under fierce price competition from PMIC leader Texas Instruments (TI), inventory reductions for Fabless and other IDMs were drastically inhibited. With IDMs ushering in output from their new plants and pulling back outsourced orders, this compounded reductions to wafer foundries. This dynamic saw 8-inch production capacity utilization dipping to 50-60% in the second half of the year. Both Tier 1 and Tier 2/3 8-inch wafer foundries saw a more lackluster capacity utilization performance compared to the first half of the year.

Intel Corporation today announced its intent to separate its Programmable Solutions Group (PSG) operations into a standalone business. This will give PSG the autonomy and flexibility it needs to fully accelerate its growth and more effectively compete in the FPGA industry, which serves a broad array of markets, including the data center, communications, industrial, automotive, aerospace and defense sectors. Intel also announced that Sandra Rivera, executive vice president at Intel, will assume leadership of PSG as chief executive officer; Shannon Poulin has been named chief operating officer.

Standalone operations for PSG are expected to begin Jan. 1, 2024, with ongoing support from Intel. Intel expects to report PSG as a separate business unit when it releases first-quarter 2024 financials. Over the next two to three years, Intel intends to conduct an IPO for PSG and may explore opportunities with private investors to accelerate the business's growth, with Intel retaining a majority stake.

Pierre Ferragu, the Global Technology Infrastructure chief at New Street Research, has predicted a very positive 2025 financial outcome for Taiwan Semiconductor Manufacturing Company Limited (TSMC). A global slowdown in consumer purchasing of personal computers and smartphones has affected a number of companies including the likes of NVIDIA and AMD—their financial reports have projected a 10% annual revenue drop for 2023. TSMC has similarly forecast that its full year revenue for 2023 will settle at $68.31 billion, after an approximate 10% fall. Ferragu did not contest these figures—via his team's analysis—TSMC is expected to pull in $68 billion in net sales for this financial year.

The rumor mill has TSMC revising its revenue guidance for a third time this year—but company leadership has denied that this will occur. New Street Research estimates that conditions will improve next year, with an uptick in client orders placed at TSMC's foundries. Ferragu reckons that TSMC could hit an all-time revenue high of $100 billion by 2025. His hunch is based on the upcoming spending habits of VIP foundry patrons encompassing: "a bottom-up perspective, looking at how TSMC's top customers, which we all know very well, will contribute to such growth." The Taiwanese foundry's order books are reported to be filling up for next year, with Apple and NVIDIA seizing the moment to stand firmly at the front of the 3 nm process queue.