TSMC today announced that in addition to TSMC Arizona's first fab, which is scheduled to begin production of N4 process technology in 2024, TSMC has also started the construction of a second fab which is scheduled to begin production of 3 nm process technology in 2026. The overall investment for these two fabs will be approximately US$40 billion, representing the largest foreign direct investment in Arizona history and one of the largest foreign direct investments in the history of the United States.

In addition to the over 10,000 construction workers who helped with construction of the site, TSMC Arizona's two fabs are expected to create an additional 10,000 high-paying high-tech jobs, including 4,500 direct TSMC jobs. When complete, TSMC Arizona's two fabs will manufacture over 600,000 wafers per year, with estimated end-product value of more than US $40 billion.

Apple and NVIDIA will be among the first customers of TSMC's swanky new $12 billion semiconductor fab in Arizona, USA. Apple will be the first major player to kick off mass-production in the fab, and will be closely followed by NVIDIA. Both companies plan to produce some of their inventory in Arizona, and ramp proportionately up as the fab grows in capacity.

The plan with TSMC's Arizona fab was to originally make 5 nm and 4 nm EUV chips, with an output of 20,000 wafers a month, but the company now expects to deploy a more advanced node to keep up with what will be considered cutting-edge when the fab goes live (think 2 nm-class); and also double the output to 40,000 wafers a month. The capacity should ensure Apple and NVIDIA make their most cutting-edge chips on the node (away from Asia), so there could be tighter export controls, and build supply-chain resilience in the face of security problems arising in the Taiwan straits.

Apple's ongoing pursuit of leading performance in custom silicon packages continues with each new generation of Apple Silicon. Today, we have alleged Geekbench performance figures of the upcoming M2 Max chip, designed for the upcoming Mac devices. Featuring the same configuration with two E-cores and eight P-cores, the chip is rumored to utilize TSMC's 3 nm design. However, that is yet to be confirmed by Apple, so we don't have the exact information. In the GB5 single-thread test, the CPU set a single-core performance target of 1899 points, while the multi-core score was 8737. While last year's M1 Max chips can reach 1787 single-core and 12826 multi-core scores, these configurations are benchmarked in a Mac Studio, which has better cooling and allows for higher clocks to be achieved.

Apples to apples (pun intended) comparison with the M1 Max chip inside of a MacBook Pro version with presumably the same cooling capacity, which gets 1497 single-core and 11506 multi-core score, the new M2 Max chip is 19.4% faster in single-core results. Multi-core improvements should follow, and this M2 Max result should be different from the final product. We await more benchmarks to confirm this performance increase and the correct semiconductor manufacturing node.

According to news out of Taiwan, NVIDIA is getting ready to move its logistics center from Hong Kong to Taiwan. The information comes from Taiwan's Minister of Economic Affairs, Wang Mei-Hua, so the source should be fairly reliable. The Taiwanese government has apparently been in negotiation with NVIDIA since some time last year and the two have now reached a consensus.

The media report didn't mention where NVIDIA will locate its new logistics center, but the company and the Taiwanese government have been discussing tax subsidies to help facilitate the move. Wang told the local media that the new logistics center should boost the local industry, least not because NVIDIA is already working with TSMC, as well as many other local suppliers and manufacturers. No details were given on when the move would take place, but it's likely to be a transition that will be drawn out, due to the fact that NVIDIA is still going to have to supply all of its customers during the move.

Semiconductor manufacturing is a significant investment that requires long lead times and constant improvement. According to the latest DigiTimes report, the pricing of a 3 nm wafer is expected to reach $20,000, which is a 25% increase in price over a 5 nm wafer. For 7 nm, TSMC managed to produce it for "just" $10,000; for 5 nm, it costs the company to make it for the $16,000 mark. And finally, the latest and greatest technology will get an even higher price point at $20,000, a new record in wafer pricing. Since TSMC has a proven track record of delivering constant innovation, clients are expected to remain on the latest tech purchasing spree.

Companies like Apple, AMD, and NVIDIA are known for securing orders for the latest semiconductor manufacturing node capacities. With a 25% increase in wafer pricing, we can expect the next-generation hardware to be even more expensive. Chip manufacturing price is a significant price-determining factor for many products, so the 3 nm edition of CPUs, GPUs, etc., will get the highest difference.

Although Morris Chang is no longer in charge of the day to day business at TSMC, the founder of the company is still getting his hands dirty. Chang attended the APEC Economic Leaders Meeting last week, as part of Taiwan's delegation and was questioned by the media about TSMC's future plans. The specific question was about TSMC's Arizona fab, which will initially produce chips using a 5 nm node. The US$12 billion plant is scheduled to kick off production at some point in 2024, by which time the 5 nm node should be a commonly used node rather than close to cutting edge.

When questioned about the future of the Arizona fab, Morris Chang answered that it will be moving to a 3 nm node, which is currently TSMC's most cutting edge node, that has gone into volume production earlier this year with th N3 node, which is set to be followed by the N3E node. According to Chang, there's interest by several countries to have TSMC set up fabs there, but apparently this is not something TSMC is considering at the moment. One potential reason for this would be a suitable labour force, something that has already proven to be tough for the Arizona fab.

Suppose you are following the inside of the semiconductor industry. In that case, you must be aware of the United States CHIPs act, where the US government plans to invest billions of dollars into domestic companies to boost the production of semiconductors devices on American soil. However, it seems like the Biden administration isn't the only governing body that realizes the importance of making semiconductors that power everything from entertainment to government, as Taiwan is supposed to announce a similar act for Taiwanese semiconductor makers like TSMC, MediaTek, GlobalWafers, UMC, etc. to simulate additional manufacturing and development on Taiwanese soil.

On Thursday, the Taiwanese government is expected to announce a 25% tax cut for research and development efforts of companies manufacturing their chips on the domestic playground. In addition to this tax deduction, Taiwan also plans to impose an additional 5% tax break on equipment purchasing, so companies like TSMC and GlobalWafers that purchase leading-edge equipment will be enjoying a healthy 30% smaller tax bill. This money is a Taiwanese way of creating additional funds for R&D purposes so these companies can bolster their CapEx with additional funds. We await to see what will happen tomorrow and update this story with more information as the official act gets announced.

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today announced two major milestones in the commercialization of its technology for multi-die chiplet integration: the close of its Series A $40M funding round, and the successful tapeout of its technology on an industry standard 5-nanometer (nm) process.

Eliyan's NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of specialized approaches.

MediaTek today launched the Dimensity 9200, its latest 5G chipset powering the next era of flagship smartphones. Boasting extreme performance and intelligent power efficiency, the new SoC brings immersive all-day gaming experiences, ultra-sharp image capturing and support for both mmWave 5G and sub-6 GHz connectivity to consumers around the globe.

"MediaTek's Dimensity 9200 combines ultimate performance with significant power savings, extending battery life and keeping smartphones cool," said JC Hsu, Corporate Vice President and General Manager of MediaTek's wireless communications business unit at MediaTek. "With notably brighter image capturing and improved gaming speeds, along with the latest display enhancements, the Dimensity 9200 will bring new possibilities for next-gen smartphones that come in a variety of stylish and foldable form factors."

In what can only be called an unusual move, several Chinese fabless chip makers—such as Alibaba and Biren Technology—who manufacturers at TSMC, are looking at running their chips slower. The reason for this is that they're trying to circumvent the US sanctions against Chinese chip makers. It should be noted that these are chips that have already taped out and gone into sample production, such as Biren's BR100 GPU.As reported earlier today, Alibaba even had one of its chips delisted from the official SPEC ranking, due to being unavailable and it's possible that it's one of the chips that's affected by the US sanctions.

Considering that the Chinese chip makers are dependent on the same cutting edge nodes at TSMC as the likes of Nvidia, AMD, Qualcomm etc. it would potentially lead to more capacity for these companies at TSMC. According to the report by the Financial Times, Biren has had to stop shipments of its GPUs, as the company is going to have to prove that its chips don't violate the US export control restrictions. Apparently the rules to work out if a chip falls under the US sanctions or not are anything but clear. One metric is apparently based on the bidirectional transfer rate, which is capped at below 600 GB/s between chips, but the tricky part is that this metric can be calculated in several different ways. As such, Biren has dropped the transfer rate from 640 to 576 GB/s according to the Financial Times. The sanctions are likely to cause longer term concerns for TSMC as well, as the company is likely to lose several big customers for its cutting edge nodes, at least for the time being.

Here's the first picture of the "Navi 31" GPU at the heart of AMD's fastest next-generation graphics cards. Based on the RDNA3 graphics architecture, this will mark an ambitious attempt by AMD to build the first multi-chip module (MCM) client GPU featuring more than one logic die. MCM GPUs aren't new in the enterprise space with Intel's "Ponte Vecchio," but this would be the first such GPU meant for hardcore gaming graphics products. AMD had made MCM GPUs in the past, but those have been packages with just one logic die, surrounded by memory stacks. "Navi 31" is an MCM of as many as eight logic dies, and no memory stacks (no, those aren't HBM stacks in the picture below).

It's rumored that "Navi 31" features one or two SIMD chiplets dubbed GCDs, featuring the GPU's main number crunching machinery, the RDNA3 compute units. These chiplets are likely built on the most advanced silicon fabrication node, likely TSMC 5 nm EUV, but we'll see. The GDDR6 memory controllers handling the chip's 384-bit wide GDDR6 memory interface, will be located on separate chiplets built on a slightly older node, such as TSMC 6 nm. This is not multi-GPU-a-stick, because both SIMD chiplets have uniform access to the entire 384-bit wide memory bus (which is not 2x 192-bit but 1x 384-bit), besides the other ancillaries. The "Navi 31" MCM are expected to be surrounded by JEDEC-standard 20 Gbps GDDR6 memory chips.

A major unnamed customer of TSMC has reportedly cut their order for 3 nm wafers. Foundry customers usually place orders for cutting-edge foundry nodes several quarters in advance, in exchange for priority foundry allocations, and preferential rates, while foundries use revenues from these orders to develop the capacity for manufacture these chips. The 3 nm customer could be anyone—Qualcomm, Mediatek, NVIDIA, AMD, or Intel. Order cancellations have reportedly had a domino-effect on the upstream supply-chain of TSMC, hitting suppliers of raw materials, manufacturing equipment, and other consumables. There is an industry-wide slump in demand for consumer electronics and PC hardware, which reflects in the slump in revenues and/or guidance in quarterly financial results releases by prominent companies.

Based on news out of Taiwan, TSMC is said to be in the early planning stages of yet another chip plant, this time for its first N1 node. The new plant will reportedly be built in a science park in Taoyuan, less than an hour south west of Taipei, according to the Commercial Times. TSMC already has a pair of chip packaging and testing facilities in the science park, making it a suitable location for a chip plant. This will be TSMC's most northern chip manufacturing plant in Taiwan, although it's not expected to start pilot production until sometime in 2027. TSMC hasn't confirmed any of the details, but the company didn't outright deny the report either.

Despite the potential global downturn in the economy, TSMC appears to be fully committed to continue to build new fabs for increasingly smaller nodes. The company is set to start its first commercial production on its N3 node this quarter and is expecting the N3 node to contribute as much as four to six percent of its overall revenue in 2023. Its N2 node should enter commercial production in 2025, but not much is known about the state of the N2 node at this point in time. The N1 node might end up being a 1.4 nm node, based on TSMC's measurements, but the company is still in the very beginning of the R&D phase for this node.

TSMC today announced the Open Innovation Platform (OIP) 3DFabric Alliance at the 2022 Open Innovation Platform Ecosystem Forum. The new TSMC 3DFabric Alliance is TSMC's sixth OIP Alliance and the first of its kind in the semiconductor industry that joins forces with partners to accelerate 3D IC ecosystem innovation and readiness, with a full spectrum of best-in-class solutions and services for semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. This alliance will help customers achieve speedy implementation of silicon and system-level innovations and enable next-generation HPC and mobile applications using TSMC's 3DFabric technologies, a comprehensive family of 3D silicon stacking and advanced packaging technologies.

"3D silicon stacking and advanced packaging technologies open the door to a new era of chip-level and system-level innovation, and also require extensive ecosystem collaboration to help designers navigate the best path through the myriad options and approaches available to them," said Dr. L.C. Lu, TSMC fellow and vice president of design and technology platform. "Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers an easy and flexible way to unlocking the power of 3D IC in their designs, and we can't wait to see the innovations they can create with our 3DFabric technologies."

Alphawave IP (LSE: AWE), a global leader in high-speed connectivity for the world's technology infrastructure, today announced the successful tapeout of its ZeusCORE100 1-112 Gbps NRZ/PAM4 Serialiser-Deserialiser ("SerDes"), Alphawave's first testchip on TSMC's most advanced N3E process. Alphawave IP will be exhibiting this new product alongside its complete portfolio of high-performance IP, chiplet, and custom silicon solutions at the TSMC OIP Forum on October 26 in Santa Clara, CA as the Platinum sponsor.

ZeusCORE100 is Alphawave's most advanced multi-standard-SerDes, supporting extra-long channels over 45dB and the most requested standards such as 800G Ethernet, OIF 112G-CEI, PCIe GEN6, and CXL 3.0. Attendees will be able to visit the Alphawave booth and meet the company's technology experts including members of the recently acquired OpenFive team. OpenFive is a longstanding partner of TSMC through the OIP Value Chain Aggregator (VCA) program. OpenFive is one of a select few companies with an idea-to-silicon methodology in TSMC's latest technologies, and advanced packaging capabilities, enabling access to the most advanced foundry solution available with the best Power-Performance-Area (PPA). With Alphawave's industry-leading IP portfolio and the addition of OpenFive's capabilities, designers can create systems on a chip (SoCs) that pack more compute power into smaller form factors for networking, AI, storage, and high-performance computing (HPC) applications.

Jon Peddie Research (JPR) has responded to the recent dramatic reports by Canalys, Gartner, and IDC showing a precipitous drop in Q3 2022 PC shipments. In addition, JPR is providing guidance on the impact to graphics chip and AIB shipments. Jon Peddie, president and founder of JPR, said, "Our advice to clients has been consistent since 2020: The pandemic boom was not a surge in demand brought about by real growth in the market. The PC market is now correcting itself after a period of extraordinary growth spurred on by spending from an overwhelming surge of users working from home."

Peddie continued, "People were forced to work at home in 2020 and 2021, and many needed equipment. As a result, PC sales surged. Those people have what they need, and some of them are going back to the office. They don't need new PCs, and won't for three to five years. So, we are back to the nominal growth of the PC market, which was, and will be again after two quarters' adjustment, tracking GNP growth."

Another quarter, another record breaking earnings report by TSMC, but it seems like the company has released that things are set to slow down sooner than initially expected and the company is hitting the brakes on some of its expansion projects. The company saw a 79.7 percent increase in profits compared to last year, with a profit of US$8.8 billion and a revenue of somewhere between US$19.9 to US$ 20.7 billion for the third quarter, which is a 47.9 percent bump compared to last year. TSMC's 5 nm nodes were the source for 28 percent of the revenues, followed by 26 percent for 7 nm nodes, 12 percent for 16 nm and 10 percent for 28 nm, with remaining nodes at 40 nm and larger making up for the remainder of the revenue. By platform, smartphone chips made up 41 percent, followed by High Performance Computing at 39 percent, IoT at 10 percent and automotive at five percent.

TSMC said it will cut back its CAPEX budget by around US$4 billion, to US$36 billion, compared to the earlier stated US$40 billion budget the company had set aside for expanding its fabs. Part of the reason for this is that TSMC is already seeing weaker demand for products manufactured using its N7 and N6 nodes, as the N7 node was meant to be a key part of the new fab in Kaohsiung in southern Taiwan. TSMC is expecting to start production on its first N3 node later this quarter and is expecting the capacity to be fully utilised for all of 2023. Supply is said to be exceeding demand, which TSMC said is partially to blame on tooling delivery issues. TSMC is expecting next year's revenue for its N3 node to be higher than its N5 node in 2020, although the revenue is said to be in the single digit percentage range. The N3E node is said to start production sometime in the second half of next year, or about a quarter earlier than expected. The N2 node isn't due to start production until 2025, but TSMC is already having very high customer engagement, so it doesn't look like TSMC is likely to suffer from a lack of business in the foreseeable future, as long as the company keeps delivering new nodes as planned.

In December of 2021, we covered the appearance of Russia's home-grown Baikal-S processor, which has 48 cores based on Arm Cortex-A75 cores. Today, thanks to the famous chip photographer Fritzchens Fritz, we have the first die shows that show us exactly how Baikal-S SoC is structured internally and what it is made up of. Manufactured on TSMC's 16 nm process, the Baikal-S BE-S1000 design features 48 Arm Cortex-A75 cores running at a 2.0 GHz base and a 2.5 GHz boost frequency. With a TDP of 120 Watts, the design seems efficient, and the Russian company promises performance comparable to Intel Skylake Xeons or Zen1-based AMD EPYC processors. It also uses a home-grown RISC-V core for management and controlling secure boot sequences.

Below, you can see the die shots taken by Fritzchens Fritz and annotated details by Twitter user Locuza that marked the entire SoC. Besides the core clusters, we see that a slum of cache connects everything, with six 72-bit DDR4-3200 PHYs and memory controllers surrounding everything. This model features a pretty good selection of I/O for a server CPU, as there are five PCIe 4.0 x16 (4x4) interfaces, with three supporting CCIX 1.0. You can check out more pictures below and see the annotations for yourself.

Stock prices of major semiconductor foundry companies such as TSMC and Samsung took a major beating on Monday. TSMC, Taiwan's premier foundry, sees its share prices drop by 7.1%, its lowest since Q1 2021. Samsung Electronics dropped by as much as 3.9%, and SK Hynix by 3.5%. Bloomberg reports that the selloffs in Asian markets may have been triggered by traders returning on Monday from a week's holiday reacting to fresh curbs on semiconductor sales to China by the Biden administration. The publication also remarks that global tech stocks have had their worst month since the October 2008.

"The latest U.S. move would prompt China to move faster in fostering the domestic chip industry," said Omdia analyst Akira Minamikawa. "Japanese firms should continue trading with Chinese firms with goods not restricted because the business is business. But they should be ready for a future--maybe in a decade or two--when they lose all the Chinese customers as a result of the current tension dialing up speed of the Chinese efforts."

The latest CFI-1202 series hardware revisions of the Sony PlayStation 5 entertainment system receive new "Oberon Plus" SoCs built on the TSMC N6 (6 nm) silicon fabrication node, and could include several new power-management features of the kind seen in AMD Ryzen 6000 mobile-processors, which could bring down the overall weight of the console as it could shed anywhere between 200-300 grams (6.25-6.5 percent) compared to older 2021 models. The CFI-1202B is the Digital-only variant that lacks an optical drive; while the CFI-1202A is the slightly heavier model that comes with a Blu-ray ROM drive. The 6% reduction in weight may not seem like much to the end-user, but has a cumulative effect for Sony to ship them by the thousands.

According to TrendForce research, due to steady weakening of overall demand for consumer electronics, inventory pressure has increased among downstream distributors and brands. Although there are still sporadic shortages of specific components, the curtain has officially fallen on a two-year wave of shortages in general, and brands have gradually suspended stocking in response to changes in market conditions. However, stable demand for automotive and industrial equipment is key to supporting the ongoing growth of foundry output value. At the same time, since the creation of a marginal amount of new capacity in 2Q22 led to growth in wafer shipments and a price hike for certain wafers, this drove output value among top ten foundries to reach US$33.20 billion in 2Q22. Quarterly growth fell to 3.9% on a weakening consumer market.

A prelude to inventory correction was officially revealed in 3Q22. In addition to intensifying severity in the initial wave of order slashing for LDDI/TDDI, and TV SoC, diminishing order volume also extended to non-Apple smartphone APs and peripheral IC PMIC, CIS, and consumer electronics PMICs, and mid-to-low-end MCUs, posing a challenge for foundry capacity utilization. However, the launch of the new iPhone in 3Q22 is expected to prop up a certain amount of stocking momentum for the sluggish market. Therefore, top ten foundry revenue in 3Q22 is expected to maintain a growth trend driven by high-priced processes and quarterly growth rate is expected to be slightly higher than in 2Q22.

Based on a report by Tom's Hardware, AMD's CEO Lisa Su is planning a trip to Taiwan in the next couple of months. It is said that she is planning to meet with multiple partners in Taiwan, such as ASUS, Acer and maybe more importantly, ASMedia, which will be the sole maker of chipsets for AMD, once the X570 chipset is discontinued. AMD is apparently also seeing various less well known partners that deliver parts for its CPUs, such as Nan Ya PCB, Unimicron Technologies and Kinsus Interconnects.

However, it appears that the main reason for Lisa Su herself to visit Taiwan will be to meet with TSMC, to discuss future collaboration with CC Wei, TSMC's chief executive. This is so AMD can secure enough wafer allocation on future nodes, such as its 3 nm and 2 nm class nodes. The move to these nodes is obviously not happening in the near future for AMD, but considering that TSMC is currently the leading foundry and is operating at capacity, it makes sense to get in early, as the competition is stiff when it comes to getting wafer allocation on cutting edge nodes. It's unclear which exact 3 nm class node AMD will be aiming for, but it might be the N3P node, which is said to kick off production sometime next year. Lisa Su is also said to have meetings with TSMC, SPIL and Ase Technology when it comes to advanced packaging for AMD's products. This includes technologies such as chip-on-wafer-on-substrate (CoWoS) and fan-out embedded bridge (FO-EB), with AMD already being expected to use some of these technologies in its upcoming Navi 3x GPUs.

Here's our first look at the "AD103" and "AD104" chips powering the GeForce RTX 4080 16 GB and RTX 4080 12 GB, respectively, thanks to Ryan Smith from Anandtech. These are the second- and third-largest implementations of the GeForce "Ada" graphics architecture, with the "AD102" powering the RTX 4090 being the largest. Both chips are built on the same TSMC 4N (4 nm EUV) silicon fabrication process as the AD102, but are significantly distant from it in specifications. For example, the AD102 has a staggering 80 percent more number-crunching machinery than the AD103, and a 50 percent wider memory interface. The sheer numbers at play here, enable NVIDIA to carve out dozens of SKUs based on the three chips alone, before we're shown the mid-range "AD106" in the future.

The AD103 die measures 378.6 mm², significantly smaller than the 608 mm² of the AD102, and it reflects in a much lower transistor count of 45.9 billion. The chip physically features 80 streaming multiprocessors (SM), which work out to 10,240 CUDA cores, 320 Tensor cores, 80 RT cores, and 320 TMUs. The chip is endowed with a healthy ROP count of 112, and has a 256-bit wide GDDR6X memory interface. The AD104 is smaller still, with a die-size of 294.5 mm², a transistor count of 35.8 billion, 60 SM, 7,680 CUDA cores, 240 Tensor cores, 60 RT cores, 240 TMUs, and 80 ROPs. Ryan Smith says that the RTX 4080 12 GB maxes out the AD104, which means its memory interface is physically just 192-bit wide.

The AD102 silicon on which NVIDIA's new flagship graphics card, the GeForce RTX 4090, is based, is a marvel of semiconductor engineering. Built on the 4 nm EUV (TSMC 4N) silicon fabrication process, the chip has a gargantuan transistor-count of 76.3 billion, a nearly 170% increase over the previous GA102, and a die-size of 608 mm², which is in fact smaller than the 628 mm² die-area of the GA102. This is thanks to TSMC 4N offering nearly thrice the transistor-density of the Samsung 8LPP node on which the GA102 is based.

The AD102 physically features 18,432 CUDA cores, 568 fourth-generation Tensor cores, and 142 third-generation RT cores. The streaming multiprocessors (SM) come with special components that enable the Shader Execution Reordering optimization, which has a significant performance impact on both raster- and ray traced graphics rendering performance. The silicon supports up to 24 GB of GDDR6X or up to 48 GB of GDDR6+ECC memory (the latter will be seen in the RTX Ada professional-visualization card), across a 384-bit wide memory bus. There are 568 TMUs, and a mammoth 192 ROPs on the silicon.

NVIDIA today unveiled the GeForce RTX 40 Series of GPUs, designed to deliver revolutionary performance for gamers and creators, led by its new flagship, the RTX 4090 GPU, with up to 4x the performance of its predecessor. The world's first GPUs based on the new NVIDIA Ada Lovelace architecture, the RTX 40 Series delivers massive generational leaps in performance and efficiency, and represents a new era of real-time ray tracing and neural rendering, which uses AI to generate pixels.

"The age of RTX ray tracing and neural rendering is in full steam, and our new Ada Lovelace architecture takes it to the next level," said Jensen Huang, NVIDIA's founder and CEO, at the GeForce Beyond: Special Broadcast at GTC. "Ada provides a quantum leap for gamers and paves the way for creators of fully simulated worlds. With up to 4x the performance of the previous generation, Ada is setting a new standard for the industry," he said.