NVIDIA's next-generation AD102 "Ada" GPU is shaping up to be a monstrosity, with a rumored transistor-count north of 75 billion. This would put over 2.6 times the 28.3 billion transistors of the current-gen GA102 silicon. NVIDIA is reportedly building the AD102 on the TSMC N5 (5 nm EUV) node, which offers a significant transistor-density uplift over the Samsung 8LPP (8 nm DUV) node on which the GA102 is built. The 8LPP offers 44.56 million transistors per mm² die-area (MTr/mm²), while the N5 offers a whopping 134 MTr/mm², which fits in with the transistor-count gain. This would put its die-area in the neighborhood of 560 mm². The AD102 is expected to power high-end RTX 40-series SKUs in the RTX 4090-series and RTX 4080-series.

AMD today announced the Ryzen 7000 series "Zen 4" desktop processors. These debut the company's new "Zen 4" architecture to the market, increasing IPC, performance, with new-generation I/O such as DDR5 and PCI-Express Gen 5. AMD hasn't increased core-counts over the previous-generation, the Ryzen 5 series is still 6-core/12-thread, the Ryzen 7 8-core/16-thread, and Ryzen 9 either 12-core/24-thread, or 16-core/32-thread; but these are all P-cores. AMD is claiming a 13% IPC uplift generation over generation, which coupled with faster DDR5 memory, and CPU clock speeds of up to 5.70 GHz, give the Ryzen 7000-series processor an up to 29% single-core performance gain over the Ryzen 5000 "Zen 3."

At their press event, AMD showed us an up to 35% increase in gaming performance over the previous-generation, and an up to 45% increase in creator performance (which is where it gets the confidence to stick to its core-counts from). The "Zen 4" CPU core dies (CCDs) are built on the TSMC 5 nm EUV (N5) node. Even the I/O die sees a transition to 6 nm (N6), from 12 nm. The switch to 5 nm gives "Zen 4" 62 percent lower power for the same performance, or 49% more performance for the same power. versus the Ryzen 5000 series on 7 nm. The "Zen 4" core along with its dedicated L2 cache is 50% smaller, and 47% more energy efficient than the "Golden Cove" P-core of "Alder Lake."

The US Government has instituted a ban on supply of GAA-FET EDA software to China (the Chinese government and companies in China). Humans can no longer design every single circuit on chips with tens of billions of transistors, and so EDA (electronics design automation) software is used to micromanage design based broadly on what chip architects want. Synopsys, Cadence, and Siemens are major EDA software suppliers. Intel is rumored to use an in-house EDA software that it doesn't sell, although this could change with the company roping in third-party foundries, such as TSMC, for cutting-edge logic chips (which will need the software to make sense of Intel's designs).

GAA or "gates-all-around" technology is vital to building transistors in the 3 nm and 2 nm silicon fabrication nodes. Samsung is already using GAA for its 3 nm node, while TSMC intends to use it with its 2N (2 nm) node. Intel is expected to use it with its Intel 20A (20 angstrom, or 2 nanometers) node. Both Intel and TSMC will debut nodes powered by GAAFETs for mass-production in 2024. The US Government has already banned the sales of EUV lithography machines to China, as well as machines fabricating 3D NAND flash chips with greater than 128 layers or 14 nm. In the past, technology embargoes have totally stopped China from copying or reverse-engineering western tech, or luring Taiwanese engineers armed with industry secrets away on the promise of wealth and a comfortable life in the Mainland.

AMD is now TSMC's second largest customer for its 5 nanometer N5 silicon fabrication node, according to a DigiTimes report. The Taiwan-based semiconductor industry observer also reports that AMD is more resilient than Intel in facing any downturns in the PC industry, in the coming few months. PC sales are expected to slump by as much as 15 percent in the near future, but the lower market-share compared to Intel; and the flexibility for AMD to move its CPU chips over to enterprise product to feed the growth in server processor segment, means that the company can ride over a bumpy road in the near future. The lower market-share translates to "lesser pain" from a slump compared to Intel. The report also says that embracing TSMC for processors "just in time" means that AMD has a front-row seat with product performance, time-to-market, yields, and delivery.

AMD is on the anvil of two major product launches on 5 nm, the Ryzen 7000 series "Raphael" desktop processors on August 30 (according to the report), and EPYC "Genoa" server processors in November 2022. The company is planning to refresh its notebook processor lineup in the first half of 2023, with "Dragon Range," and "Phoenix Point" targeting distinct market segments among notebooks. "Dragon Range" is essentially "Raphael" (5 nm chiplet + 6 nm cIOD) on a mobile-optimized BGA package, letting AMD cram up to 16 "Zen 4" cores, and take on Intel's high core-count mobile processors. The iGPU of "Dragon Range" will be basic, since designs based on this chip are expected to use discrete GPUs. "Phoenix Point" is a purpose-built mobile processor with up to 8 "Zen 4" cores, and a powerful iGPU based the RDNA3 architecture.

AMD in its HotChips 22 presentation released a block-diagram of its biggest AI-HPC processor, the Instinct MI250X. Based on the CDNA2 compute architecture, at the heart of the MI250X is the "Aldebaran" MCM (multi-chip module). This MCM contains two logic dies (GPU dies), and eight HBM2E stacks, four per GPU die. The two GPU dies are connected by a 400 GB/s Infinity Fabric link. They each have up to 500 GB/s of external Infinity Fabric bandwidth for inter-socket communications; and PCI-Express 4.0 x16 as the host system bus for AIC form-factors. The two GPU dies together make up 58 billion transistors, and are fabricated on the TSMC N6 (6 nm) node.

The component hierarchy of each GPU die sees eight Shader Engines share a last-level L2 cache. The eight Shader Engines total 112 Compute Units, or 14 CU per engine. The CDNA2 compute unit contains 64 stream processors making up the Shader Core, and four Matrix Core Units. These are specialized hardware for matrix/tensor math operations. There are hence 7,168 stream processors per GPU die, and 14,336 per package. AMD claims a 100% increase in double-precision compute performance over CDNA (MI100). AMD attributes this to increases in frequencies, efficient data paths, extensive operand reuse and forwarding; and power-optimization enabling those higher clocks. The MI200 is already powering the Frontier supercomputer, and is working for more design wins in the HPC space. The company also dropped a major hint that the MI300, based on CDNA3, will be an APU. It will incorporate GPU dies, core-logic, and CPU CCDs onto a single package, in what is a rival solution to NVIDIA Grace Hopper Superchip.

NVIDIA designed the Grace CPU, a processor in the classical sense, to replace the Intel Xeon or AMD EPYC processors it was having to cram into its pre-built HPC compute servers for serial-processing roles, and mainly because those half-a-dozen GPU HPC processors need to be interconnected by a CPU. The company studied the CPU-level limitations and bottlenecks not just with I/O, but also the machine-architecture, and realized its compute servers need a CPU purpose-built for the role, with an architecture that's heavily optimized for NVIDIA's APIs. This, the NVIDIA Grace CPU was born.

This is NVIDIA's first outing with a CPU with a processing footprint rivaling server processors from Intel and AMD. Built on the TSMC N4 (4 nm EUV) silicon fabrication process, it is a monolithic chip that's deployed standalone with an H100 HPC processor on a single board that NVIDIA calls a "Superchip." A board with a Grace and an H100, makes up a "Grace Hopper" Superchip. A board with two Grace CPUs makes a Grace CPU Superchip. Each Grace CPU contains a 900 GB/s switching fabric, a coherent interface, which has seven times the bandwidth of PCI-Express 5.0 x16. This is key to connecting the companion H100 processor, or neighboring Superchips on the node, with coherent memory access.

Intel's next-generation "Meteor Lake" processor is the first mass-production client processor to embody the company's IDM 2.0 manufacturing strategy—one of building processors with multiple logic tiles interconnected with Foveros and a base-tile (essentially an interposer). Each tile is built on a silicon fabrication process most suitable to it, so that the most advanced node could be reserved for the component that benefits from it the most. For example, while you need the SIMD components of the iGPU to be built on an advanced low-power node, you don't need its display controller and media engine to, and these could be relegated to a tile built on a less advanced node. This way Intel is able to maximize its use of wafers for the most advanced nodes in a graded fashion.

Japanese tech publication PC Watch has annotated the "Meteor Lake" SoC, and points out that the vast majority of the chip's tiles and logic die-area is manufactured on TSMC nodes. The MCM consists of four logic tiles—the CPU tile, the Graphics tile, the SoC tile, and the I/O tile. The four sit on a base tile that facilitates extreme-density microscopic wiring interconnecting the logic tiles. The base tile is built on the 22 nm HKMG silicon fabrication node. This tile lacks any logic, and only serves to interconnect the tiles. Intel has an active 22 nm node, and decided it has the right density for the job.

Based on media reports out of Taiwan, TSMC seems to have plenty of customers lined up for its 3 nm node, with Apple being the first customer out the gates when production starts sometime next month. However, TSMC is only expected to start the production with a mere 1,000 wafer starts a month, which seems like a very low figure, especially as this is said to remain unchanged through all of Q4. On the plus side, yields are expected to be better than the initial 5 nm node yields. Full-on mass production for the 3 nm node isn't expected to happen until the second half of 2023 and TSMC will also kick off its N3E node sometime in 2023.

Apart from Apple, major customers for the 3 nm node include AMD, Broadcom, Intel, MediaTek, NVIDIA and Qualcomm. Contrary to earlier reports by TrendForce, it appears that TSMC will continue its rollout of the 3 nm node as previously planned. Apple is expected to produce the A17 smartphone and tablet SoC, as well as advanced versions of the M2, as well as the M3 laptop and desktop processors on the 3 nm node. Intel is still said to be producing its graphics chiplets with TSMC, with the potential for GPU and FPGA products in the future. There's no word on what the other customers are planning to produce on the 3 nm node, but MediaTek and Qualcomm are obviously looking at using the node for future smartphone and tablet SoCs, with AMD and NVIDIA most likely aiming for upcoming GPUs and Broadcom for some kind of HPC related hardware.

Based on a report by TrendForce, Intel has yet again had to push back its upcoming Meteor Lake CPUs and it now appears that Intel will only be launching Meteor Lake towards the end of 2023. It's unclear why there has been yet another delay, but Intel is said to have cancelled most of its orders with TSMC for the 3 nm tGPU that Intel will have made at TSMC, for 2023. The knock-on effect of this, is that TSMC is said to be slowing down its production line expansion towards 3 nm, as the company is now unsure if it'll be able to fill its order books for all of 2023. TSMC's main customer for the 3 nm node is still going to be Apple, but with the loss of what is likely to be around six months worth of production from Intel, TSMC is said to be considering cutting its CapEx for 2023.

TSMC's other customers, such as AMD, MediaTek and Qualcomm aren't planning on moving to 3 nm until 2024, so unless there's a change in plans from either of these companies, or increased demand from Apple, TSMC is said to hit the brakes when it comes to starting up new, cutting edge production lines next year. TSMC is also likely to see reduced revenues during 2023 due to Intel's change of plans, although it's too early to make any assumptions. TrendForce also suggests that Intel might still use TSMC's 3 nm node as a backup plan, if Intel would fail to execute on moving to the Intel 4 process, but considering how complex it is to move a design between different foundry processes, this seems unlikely.

Amidst all the news of NVIDIA going slow with its GeForce RTX 40-series "Ada Lovelace" launch cycle to allow the market to absorb inventories of current-gen cards as demand from crypto-currency miners has crashed; and amidst related news that NVIDIA has delayed the production ramp of these GPUs with foundry-partner TSMC by at least a quarter (3 months), we're getting reports that production of these cards are sticking to the original launch timeline. This need not be a contradictory report, as it could be a case of NVIDIA moving forward with a limited production run in preparation to a launch.

Tech publication PRO Hi-Tech reports that one of their contacts among NVIDIA add-in-card (AIC) partners told them, that the AIC could receive the first RTX 40-series cards from NVIDIA "in less than a month" (mid/late August). This roughly aligns with the product development timeline reported by Igor's Lab, which put the final stages of hardware development by July 2022, with production validation testing in August, with video-BIOS source release, and start of mass-production toward the end of August. This would mean that prototypes of the cards are already in the hands of the AICs, and August could see them receive close-to-final hardware while they await the release of a working BIOS. With mass-production commencing toward the end of August or September, product launches could commence by Q4-2022.

The Chinese technology giant, SMIC, has managed to advance its semiconductor manufacturing technology and shipped the first 7 nm silicon manufactured on China's soil. According to analyst firm TechInsights, who examined the 7 nm Bitcoin mining SoC made for MinerVa firm, there are doubts that SMIC 7 nm process is somewhat similar to TSMC's 7 nm process. Despite having no access to advanced semiconductor manufacturing tools, and US restrictions placed around it, SMIC has managed to produce what resembles an almost perfect 7 nm node. This could lead to a true 7 nm logic and memory bitcells sometimes in the future, as the node advances in SMIC's labs.

Having done an in-depth die analysis, the TechInsights report indicates that TSMC, Intel, and Samsung have a more advanced 7 nm node and are two nodes ahead of the Chinese SMIC. The results are not great regarding the economics and yield of this SMIC 7 nm process. While we have no specific data, the report indicates that the actual working chips made with older DUV tools are not perfect. This is not a problem for the Chinese market as it seeks independence from Western companies and technology. However, introducing a China-made 7 nm chip is more critical as it shows that the country can manufacture advanced nodes with restrictions and sanctions in place. The MinerVa SoC die and the PCB that houses those chips are pictured below.

Based on a report from IC Insights, it appears that the demand for semiconductors and memory is starting to slow down. The slowdown is industry wide, with most major players having seen a reduction in sales in June compared to May. Although the report is focused on Taiwanes semiconductor companies, it also mentions Micron, who is expecting a slowdown in the third quarter of this year. Micron is reportedly expecting a drop in sales by as much as 17 percent, although this past quarter the company saw an increase in sales by 11 percent compared to the previous quarter, or 19 percent compared to last year, so it could simply be that the market is starting to normalise.

As for the Taiwanese semiconductor companies, TSMC saw a reduction in sales of five percent in June, although its competitor UMC saw an increase of two percent. Two other Taiwanese foundries, Powerchip and Vanguard, saw a decrease of four percent and an increase of three percent respectively, which shows that the foundry businesses are seeing change based on the type of chips they make. Apart from Winbond and Macronix, the other four companies in the report saw a decrease in sales by anything between two and 26 percent. Novatek, a manufacturer of semiconductors for the display industry saw the biggest dip in sales, with memory manufacturer Nanya seeing a drop of 16 percent. It should be pointed out that Novatek saw an increase in sales of 78 percent during the pandemic, which suggests their customers might not be seeing the same demand for their end products as they did over the past two years. For now, this could just be a slowdown over the summer months, when demand is usually quite low, but it could also be an indication of a return to a more normalised market.

TSMC (TWSE: 2330, NYSE: TSM) today announced consolidated revenue of NT$534.14 billion, net income of NT$237.03 billion, and diluted earnings per share of NT$9.14 (US$1.55 per ADR unit) for the second quarter ended June 30, 2022. Year-over-year, second quarter revenue increased 43.5% while net income and diluted EPS both increased 76.4%. Compared to first quarter 2022, second quarter results represented an 8.8% increase in revenue and a 16.9% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, second quarter revenue was $18.16 billion, which increased 36.6% year-over-year and increased 3.4% from the previous quarter. Gross margin for the quarter was 59.1%, operating margin was 49.1%, and net profit margin was 44.4%. In the second quarter, shipments of 5-nanometer accounted for 21% of total wafer revenue; 7- nanometer accounted for 30%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 51% of total wafer revenue.

It seems like NVIDIA wants the market to absorb inventories of its high-end GeForce RTX 30-series SKUs, such as the RTX 3090 Ti, so the company could make room for high-end SKUs from the RTX 40-series "Ada" series. Prices of the RTX 3090 Ti have tanked to as low as $1,599 for the Founders Edition, from its launch MSRP of $1,999. This $400 price-cut is probably triggered by crypto-currency miners flooding the market with high-end RTX 30-series graphics cards at attractive prices, which gamers are all too happy to lap up. The crash in demand from miners, compounded by drop in demand from gamers buying up cards in circulation, has forced NVIDIA to renegotiate its semiconductor foundry allocation with TSMC in the short-term.

New product alert! In January last year, we launched the $4 Raspberry Pi Pico, our first product built on silicon designed here at Raspberry Pi. At its heart is the RP2040 microcontroller, built on TSMC's 40 nm low-power process, and incorporating two 133 MHz Arm Cortex-M0+ cores, 264kB of on-chip SRAM, and our unique programmable I/O subsystem. Since launch, we've sold nearly two million Pico boards, and RP2040 has found its way into a huge number of third-party products. We always believed that RP2040 was a great fit for commercial and industrial applications, but the global semiconductor shortage has vastly accelerated adoption. With millions of units on hand today, and pipeline in place for tens of millions more, design engineers who have been let down by their current suppliers have a perfect excuse to experiment.

Fast cores, large memory, and flexible interfacing make RP2040 a natural building block for Internet of Things (IoT) applications. But Pico itself has one obvious missing feature for IoT: a method for connecting to the network. Now, this is about to change. Today, we're launching three new members of the Pico family. Raspberry Pi Pico W is priced at $6, and brings 802.11n wireless networking to the Pico platform, while retaining complete pin compatibility with its older sibling. Pico H ($5) and Pico WH ($7) add pre-populated headers, and our new 3-pin debug connector, to Pico and Pico W respectively. Pico H and Pico W are available today; Pico WH will follow in August.

The island of Taiwan is in many ways very much still stuck in an era where the government controls most utilities and where there is little to no competition. For example, the government controls fuel prices, be that for your motor vehicle or for cooking and heating. This also applies to the cost of electricity in most cases and the Ministry of Economic Affairs has announced that the electricity price will increase by up to 15 percent for high usage customers, which translates to the industry. The increase might sound tiny at just over 1.3 cents per kilowatt hour, for a total cost of 10.43 cents per kWh. However, a company like TSMC that uses a lot of electricity, is expected to see an increase in costs of at least US$135 million per year, according to some Taiwanese news sources, while others claim it'll be as much as US$270 million.

TSMC does in all fairness produce some of its own electricity thanks to solar panels on many of its buildings and the company has also invested heavily in renewable energy. In fact, TSMC has bought up almost all available renewable capacity in Taiwan and the company is committed to using 100 percent renewable energy in the long term. Currently a mere 8 percent (based on 2020 estimates) is coming from TSMC's own efforts, but the company should be at somewhere around 12-15 percent overall. Even so, these extra costs are likely to be reflected in future customer pricing. It's the first price hike in four years, but as Taiwan is a manufacturing nation, TSMC is unlikely to be the only company affected, but the price hike is related to global inflation and is targeting high-usage businesses and consumers alike.

Hsinchu, Taiwan-based global semiconductor silicon wafer company, GlobalWafers, announced today that it plans to build a state-of-the-art 300-millimeter silicon wafer factory in Sherman, Texas, which is the first of its kind in the USA over twenty (20) years. Construction is expected to commence later this year. This 300-millimeter greenfield investment is consistent with the Company's announcement on February 6th of this year of brownfield and greenfield expansions totaling NTD 100 bn. This new Texas investment could also support as many as 1,500 jobs with production volumes ultimately reaching 1.2 mn wafers per month after multiple stages of equipment installation, in alignment with market demand.

300-millimeter silicon wafers are the starting material for all advanced semiconductor fabrication sites (or fabs), including recently announced United States (US) expansions by GlobalFoundries, Intel, Samsung, Texas Instruments and TSMC. Most of these wafers are currently manufactured in Asia, forcing the US semiconductor industry to highly rely on imported silicon wafers. This investment will represent the first new silicon wafer facility in the US in over two decades and close a critical semiconductor supply chain gap.

According to TrendForce research, although demand for consumer electronics remains weak, structural growth demand in the semiconductor industry including for servers, high-performance computing, automotive, and industrial equipment has not flagged, becoming a key driver for medium and long term foundry growth. At the same time, due to robust wafer production at higher pricing in 1Q22, quarterly output value hit a new high for the 11th consecutive quarter, reaching US$31.96 billion, 8.2% QoQ, marginally less than the previous quarter. In terms of ranking, the biggest change is Nexchip surpassed Tower at the ninth position.

TSMC's across the board wafer hikes in 4Q21 on batches primarily produced in 1Q22 coupled with sustained strong demand for high-performance computing and better foreign currency exchange rates pushed TSMC's 1Q22 revenue to $17.53 billion, up 11.3% QoQ. Quarterly revenue growth by node was generally around 10% and the 7/6 nm and 16/12 nm processes posted the highest growth rate due to small expansions in production. The only instance of revenue decline came at the 5/4 nm process due to Apple's iPhone 13 entering the off season for production stocking.

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its PHY and Controller IP for the PCI Express (PCIe ) 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed certification tests from PCI-SIG at the industry's first event for PCIe 5.0 specification compliance held in April. The Cadence solutions were tested to their full potential and complied with the full speed of 32GT/s for PCIe 5.0 technology. The compliance program provides designers with testing procedures to assess that the PCIe 5.0 interfaces on their system-on-chip (SoC) designs will operate as expected.

The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence's PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs while accelerating time to market.

An engineering sample of AMD's next-generation Ryzen "Phoenix Point" mobile processor has been powered up, and made its first appearance on the Geekbench user-database. "Phoenix Point" is a monolithic silicon mobile processor built on the TSMC N5 (5 nm EUV) process, featuring "Zen 4" CPU cores, and a significantly faster iGPU based on the RDNA3 graphics architecture; along with a DDR5/LPDDR5 memory interface, and PCI-Express Gen 5.0 capability. An engineering sample with an 8-core/16-thread CPU, with the OPN code "100-000000709-23_N," hit the radar. AMD could debut Ryzen "Phoenix Point" in the first quarter of 2023, possibly with an International CES announcement.

TSMC today showcased the newest innovations in its advanced logic, specialty, and 3D IC technologies at the Company's 2022 North America Technology Symposium, with the next-generation leading-edge N2 process powered by nanosheet transistors and the unique FINFLEX technology for the N3 and N3E processes making their debut.

Resuming as an in-person event after being held online in the past two years, the North America symposium in Santa Clara, California, kicks off a series of Technology Symposiums around the world in the coming months. The Symposiums also feature an Innovation Zone that spotlights the achievements of TSMC's emerging start-up customers.

Intel officially launched the Arc A380 "Alchemist" entry-mainstream desktop graphics card in China, priced at RMB ¥1,030, including VAT, which roughly converts to USD $153. The Arc A380 "Alchemist" is based on the Xe-HPG graphics architecture, and the smaller DG2-128 (ACM-G11) silicon, which is built on the TSMC N6 (6 nm) silicon fabrication process.

The A380 desktop GPU is endowed with 8 Xe Cores, or 128 EU (execution units), which work out to 1,024 unified shaders. The chip features a 96-bit wide GDDR6 memory interface, running 6 GB of memory. Despite these hardware specs, you get full DirectX 12 Ultimate capability, including ray tracing, and the XeSS performance enhancement. There are also several content-creation accelerators, including Intel XMX, and AV1 hardware-encode capabilities.

One of AMD's big announcements this fall has been its entry-level "Mendocino" Ryzen 3 mobile processor, which enables the company to compete with Intel's latest-generation Pentium Gold-powered notebooks by combining older-generation IP with the latest I/O and fabrication node. The chip has possibly surfaced on the UserBenchmark database, as the Ryzen 3 7320U processor.

Built on the TSMC N6 (6 nm) silicon fabrication process, the "Mendocino" chip features a 4-core/8-thread CPU based on the older "Zen 2" microarchitecture. This CPU is a single CCX with four "Zen 2" cores sharing a 4 MB L3 cache. It features an iGPU based on the latest RDNA2 graphics architecture, but with just two compute units (128 stream processors). The chip also features a single-channel DDR5 memory interface, and a PCI-Express Gen 3 interface with four PCIe 3.0 general-purpose lanes, besides some USB and display outputs.

AMD is planning to debut its next-generation RDNA3 graphics architecture with the Radeon RX 7000 series desktop graphics cards, some time in late-October or early-November, 2022. This, according to Greymon55, a reliable source with AMD and NVIDIA leaks. We had known about a late-2022 debut for AMD's next-gen graphics, but now we have a finer timeline.

AMD claims that RDNA3 will repeat the feat of over 50 percent generational performance/Watt gains that RDNA2 had over RDNA. The next-generation GPUs will be built on the TSMC N5 (5 nm EUV) silicon fabrication process, and debut a multi-chip module design similar to AMD's processors. The logic dies with the GPU's SIMD components will be built on the most advanced node, while the I/O and display/media accelerators will be located in separate dies that can make do on a slightly older node.

Cadence Design Systems, Inc. today announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, supporting the latest Design Rule Manual (DRM). In addition, Cadence and TSMC delivered N3E and N4P process design kits (PDKs) and design flows to accelerate customer adoption and advance mobile, AI and hyperscale computing design innovation. Joint customers are actively designing with the new N3E and N4P PDKs, and several test chips have already been taped out, which demonstrates how Cadence solutions help customers improve engineering efficiency and maximize the power, performance and area (PPA) benefits offered by the latest TSMC process technologies. The Cadence digital and custom/analog advanced-node solutions support the company's Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence.

Cadence worked closely with TSMC to ensure the digital full flow was optimized for TSMC's advanced N3E and N4P process technologies. The complete RTL-to-GDS flow includes the Cadence Innovus Implementation System, Quantus Extraction Solution, Quantus Field Solver, Tempus Timing Signoff Solution and ECO option, Pegasus Verification System, Liberate Characterization Solution and Voltus IC Power Integrity Solution. Additionally, the Cadence Genus Synthesis Solution and predictive iSpatial technology are enabled for the TSMC N3E and N4P process technologies.