Yesterday, United States President Donald Trump announced a set of tariffs imposed on US trading partners, imposing a series of 10%+ tariffs on partners, calling it a "Liberation Day." Today, we are calculating how much these tariffs will impact consumers and what is most important at TechPowerUp: semiconductors powering our GPUs and CPUs. According to one of the top investment banks, Goldman Sachs, semiconductors are exempt from the reciprocal tariffs that Trump has imposed on Taiwan. However, the semiconductor manufacturing equipment used by makers like TSMC is not exempt and is expected to be hit with the 32% tariffs. This is only half of what Taiwan imposes on imports of US-made goods. For TSMC, the number one maker of GPUs and CPUs, tariffs can be tricky to navigate. While its existing manufacturing facilities use equipment sourced from Dutch ASML and a few US companies like Lam Research and KLA Corporation, it shouldn't be a problem to ship new silicon to the US.

However, if TSMC wants to expand its manufacturing facilities in any country that is not the US, it will have to deal with 32% tariffs on US-sourced silicon manufacturing equipment. For EU-based ASML, things are looking a little different. If over 20% of the equipment is made up of US content, a tariff exemption might apply, potentially reducing import costs. If more than one-fifth of a product's components or value originates from US sources, the equipment may be eligible for tariff relief. ASML's machines include some US components, so determining whether these machines meet the 20% threshold is crucial. If they do, the tariff exemption could help lower costs associated with importing these advanced machines, reaching up to $380 million. For non-US-injected goods, EU entities are subject to 20% tariffs.

Surface defects on the GPU die of a PowerColor Radeon RX 9070 XT Hellhound have been linked to excessive thermal hotspots, according to analysis following Igor's Lab's investigation. Microscopic examination revealed 1,934 pits across the silicon die surface despite proper thermal interface material application. The defects affect over one percent of the chip's surface area, with the largest measuring 12.59 µm in depth and 212.36 µm in diameter—significantly exceeding industry tolerances. These imperfections impede heat transfer, causing localized temperatures to reach 113°C, exceeding the 110°C threshold for RDNA GPUs and triggering thermal throttling. The defects appear to stem from flaws in the backgrinding process that thins silicon wafers for packaging. Improper process control creates surface irregularities that compromise thermal conductivity and structural integrity.

The discovery raises questions about the effectiveness of automated optical inspection systems in detecting subtle surface abnormalities. TSMC, the maker of these chips, uses optical recognition tools to see if any defects occurred. AMD stated: "We are aware of the reported issue and believe this to be an isolated incident. We are working with our partners and internal teams to understand the issue." The company maintains this is an isolated case, though the findings suggest potential gaps in quality control protocols. Users experiencing thermal issues with affected RX 9070 XT units should initiate the RMA process for replacement while AMD and PowerColor investigate whether these defects exist beyond the identified sample. We hope no further issues are present, and so far, PowerColor hasn't received any customer complaints. We are on the lookout for further situation development. We reviewed PowerColor's Radeon RX 9070 Hellhound, and found no issues on our unit, so this indeed remains an isolated case so far.

Mark Gurman—Bloomberg's resident soothsayer of Apple inside track info—has disclosed predictive outlooks for next-generation M5 chip-based MacBooks. Early last month, we experienced the launch of the Northern Californian company's M4 MacBook Air series—starting at $999; also available in a refreshing metallic blue finish. The latest iteration of Apple's signature "extra slim" notebook family arrived with decent performance figures. As per usual, press and community attention has turned to a potential successor. Gurman's (March 30) Power On newsletter posited that engineers are already working on M5-powered super slim sequels—he believes that these offerings will arrive early next year, potentially reusing the current generation's 15-inch and 13-inch fanless chassis designs.

In a mid-February predictive report, Gurman theorized that Apple was planning a major overhaul of the MacBook Pro design. A radical reimagining of the long-running notebook series—that reportedly utilizes M6 chipsets and OLED panels—is a distant prospect; perhaps later on in 2026. The Cupertino-headquartered megacorp is expected to stick with its traditional release cadence, so 2025's "M5" refresh of MacBook Pro models could trickle out by October. Insiders believe that Apple will reuse existing MacBook Pro shells—the last major redesign occurred back in 2021. According to early February reportage, mass production of the much-rumored M5 chip started at some point earlier in the year. Industry moles posit that a 3 nm (N3P) node process was on the order books, chez TSMC foundries.

Industry insiders posit that TSMC's two flagship fabrication facilities are running ahead of schedule with the development of an advanced 2 nm (N2) process node. A cross-facility mass production phase is tipped to begin later this year, which leaves room for next-level experiments. Taiwan's Economic Daily News has heard supply chain whispers about the Baoshan "P2" plant making internal preparations for a truly cutting edge 1.4 nm-class product. According to the report, unnamed sources have claimed that: "TSMC has made a major breakthrough in the advancement of its 1.4 nm process. (The company) has recently notified suppliers to prepare the necessary equipment for 1.4 nm, and plans to install a trial production 'mini-line' at P2 (Baoshan Fab 20)."

Their Hsinchu-adjacent "Fab 20" site is touted as a leading player in the prototyping of this new technology. Industry moles reckon that "1.4 nm expertise" will eventually trickle over to nearby "P3 and P4 plants" for full production phases. Allegedly, these factories were originally going to be involved in the manufacturing of 2 nm (N2) wafers. Additionally, TSMC's "Fab 25" campus could potentially play host to trial 1.4 nm activities—the Economic Daily News article proposes that four plants based in the Central Taiwan Science Park are pitching in with collaborative work. As interpreted by TrendForce, "P1" could begin "risk trial production" by 2027, followed by full-scale output within the following year.

Going back to the start of this year, TSMC's trial run of a cutting-edge 2 nm (N2) node process was reportedly progressing beyond initial expectations. According to industry moles, two flagship fabrication facilities are "optimistically" tipped to pump out 80,000 units per month (by the end of 2025). This cross-facility total figure was linked to TSMC's Baoshan—located near the Northern Taiwanese city of Hsinchu—and Kaohsiung (in the South) plants. The latest regional reports suggest that the aforementioned trial phase was a resounding success, with pleasing results pointing to an "ahead of schedule" transfer to mass production phases. Insiders previously heard about the Kaohsiung production hub's schedule; with mass production set to start by early 2026—according to fresh rumors, revised calendars have a kick-off window repositioned somewhere in late 2025. Apparently a special "2 nm plant expansion ceremony" took place in that location, earlier today.

A noted semiconductor business analyst—Ming-Chi Kuo—reckons that recent 2 nm pilot yields have progressed well over the 60% mark, meaning that the involved foundry teams are more than ready to move onto kicking things into high gear. Taiwan's Economic News Daily anticipates significant financial gains, due to TSMC N2 products already being in high demand: "the quarterly revenue in the second half of the year is expected to reach one trillion yuan (~US$30.1 billion) for the first time, and it is poised to challenge the goal of earning twice the share capital in a quarter and rewrite the record for a single quarter." The local publication claims that TSMC Baoshan's "first batch of production capacity" is fully reserved for Apple, while Kaohsiung will take care of orders for other (i.e. less) important customers.

Ayar Labs, the leader in optical interconnect solutions for large-scale AI workloads, today announced the industry's first Universal Chiplet Interconnect Express (UCIe) optical interconnect chiplet to maximize AI infrastructure performance and efficiency while reducing latency and power consumption. By incorporating a UCIe electrical interface, this solution is designed to eliminate data bottlenecks and integrate easily into customer chip designs.

Capable of achieving 8 Tbps bandwidth, the TeraPHY optical I/O chiplet is powered by Ayar Labs' 16-wavelength SuperNova light source. The integration of a UCIe interface means this solution not only delivers high performance and efficiency but also enables interoperability among chiplets from different vendors. This compatibility with the UCIe standard creates a more accessible, cost-effective ecosystem, which streamlines the adoption of advanced optical technologies necessary for scaling AI workloads and overcoming the limitations of traditional copper interconnects.

Digital Chat Station (DCS)—a tenured leaker of Qualcomm pre-release information—has shared new "Snapdragon 8 Elite Gen 2" chipset details. Earlier today, their Weibo feed was updated with a couple of technological predictions. The announced smartphone chip's "SM8850" identifier was disclosed once again, along with the repeated claim that Qualcomm has selected a 3 nm "N3P" node process. Industry watchdogs expect to see the San Diego-headquartered fabless semiconductor designer introduce its next-generation flagship smartphone SoC in October. The current-gen Snapdragon 8 Elite platform was unveiled last Fall; sporting cutting-edge "Oryon" (aka Phoenix) processor cores and an integrated Adreno 830 graphics solution. DCS reckons that the natural successor will reuse a familiar "2 + 6" core configuration; comprised of two prime "big performance" units, and six "normal" performance-tuned units. An Adreno 840 iGPU was listed as DCS's final point of conjecture.

The incoming "Snapdragon 8 Elite Gen 2" chipset was mentioned in the same sentence as rumored "Pegasus" cores (Phoenix's sequel)—slightly far-fetched rumors from 2024 suggested Qualcomm's upgraded processor architecture being tested at maximum frequencies of 5.0 GHz (on performance cores). As pointed out by Wccftech, Gen 1's performance cores run at 4.47 GHz (by default). In today's follow-up post, DCS claimed that Qualcomm's: "self-developed CPU architecture is now in the second generation, with a performance setting of over 380 W+." Industry watchdogs reckon that the "Snapdragon 8 Elite 2" chip will be capable of recording 3.8+ million point tallies in AnTuTu V10 gauntlets, thanks to the alleged utilization of ArmV9 architecture. DCS theorized that the speculated "SM8850" SoC will support ARM's Scalable Matrix Extension 1 (SME 1) and Scalable Vector Extension 2 (SVE2) instruction sets.

According to a report produced by semiconductor industry analysts at Kiwoom Securities—a South Korean financial services firm—Semiconductor Manufacturing International Corporation (SMIC) is expected to complete the development of a 5 nm process at some point in 2025. Jukanlosreve summarized this projection in a recent social media post. SMIC is often considered to be China's flagship foundry business; the partially state-owned organization seems to heavily involved in the production of (rumored) next-gen Huawei Ascend 910 AI accelerators. SMIC foundry employees have reportedly struggled to break beyond a 7 nm manufacturing barrier, due to lack of readily accessible cutting-edge EUV equipment. As covered on TechPowerUp last month, leading lights within China's semiconductor industry are (allegedly) developing lithography solutions for cutting-edge 5 nm and 3 nm wafer production.

Huawei is reportedly evaluating an in-house developed laser-induced discharge plasma (LDP)-based machine, but finalized equipment will not be ready until 2026—at least for mass production purposes. Jukanlosreve's short interpretation of Kiwoom's report reads as follows: (SMIC) achieved mass production of the 7 nm (N+2) process without EUV and completed the development of the 5 nm process to support the mass production of the Huawei Ascend 910C. The cost of SMIC's 5 nm process is 40-50% higher than TSMC's, and its yield is roughly one-third." The nation's foundries are reliant on older ASML equipment, thus are unable to produce products that can compete with the advanced (volume and quality) output of "global" TSMC and Samsung chip manufacturing facilities. The fresh unveiling of SiCarrier's Color Mountain series has signalled a promising new era for China's foundry industry.

TSMC is reconfiguring its US strategy after a challenging start at its Fab 21 facility near Phoenix, Arizona. The company's initial module took nearly five years to move from groundbreaking to production—far longer than the typical two-year process observed in Taiwan. Early setbacks, including labor issues, rising costs, and cultural differences, slowed progress, but these hurdles have provided valuable lessons. With a clearer understanding of the local construction environment, TSMC plans to speed up future projects. Company executives have identified reliable local contractors and addressed many bottlenecks that once hindered progress. As a result, the Taiwanese maker is gearing up to accelerate construction timelines for its upcoming modules. Notably, TSMC intends to start building its third fab—Fab 21 module 3—this year, aiming for a pace similar to that in Taiwan.

In the current phase, TSMC is finalizing equipment installations for Fab 21 module 1 while laying the groundwork for module 2. The plan is to begin trial production of advanced 3 nm-class chips at module 2 in 2026, with high-volume manufacturing expected to kick off by 2028. The accelerated schedule for module 3 is seen as a pathway to faster production of next-generation chips, including those using the N2-series and A16 process technologies. However, rapid construction is not without risks. A critical concern remains the timely procurement of essential fab tools. Leading suppliers such as ASML and Applied Materials face significant backlogs and capacity constraints, which may delay the delivery of necessary equipment. As TSMC vows to build its US capacity more swiftly, the entire supply chain is watching closely to see if these supply chain challenges can be resolved, ensuring that the company meets its ambitious production timelines while expanding its foothold in the American market.

According to an investment bank UBS note, two industry titans—NVIDIA and Broadcom—are potential future clients that could significantly enhance Intel's Foundry business revenue. To revitalize Intel, newly appointed CEO Lip-Bu Tan reportedly aims to forge strategic alliances with two AI chip manufacturers. Tan, who assumed leadership earlier this month, is determined to rebuild the company's reputation by focusing on customer satisfaction and accelerating the development of its foundry business. UBS analyst Tim Arcuri suggests that while Broadcom might join the client roster, NVIDIA appears to be the more likely candidate. Rather than initially manufacturing NVIDIA's AI GPUs, Intel is expected to begin production with gaming GPUs. NVIDIA could even move to AI GPU production at Intel's fabs if satisfied.

Despite some early optimism, Intel's new CEO is now committed to addressing issues related to power consumption in Intel's manufacturing processes. UBS analyst Tim Arcuri noted that the firm is pushing hard to introduce a lower-power version of its 18A process, the so-called 18AP, which has reportedly struggled to meet energy requirements. Additionally, Intel is working to improve its advanced packaging techniques to rival Taiwan's TSMC CoWoS (S/L/R variants) technology, aiming to overcome packaging constraints that have slowed AI chip production. Analysts speculate that Intel might also become a secondary supplier to tech giant Apple. A promising partnership with Taiwan's United Microelectronics (UMC) could pave the way for Intel's chips to find their way into future Apple products. Whatever materializes, we are yet to see. Switching foundries from TSMC to Intel entirely is not possible for any of the aforementioned fabless designers, so it will likely be dual-sourcing at first, with some non-flagship SKUs getting the full port to Intel 18A.

Shipping manifests have served as fairly reliable sources of pre-launch information—Everest (aka Olrak29) has discovered many juicy details in recent times. Their latest sleuthing session—combing through NBD documents—has indicated AMD's (alleged) prepping of a larger socket design for next-generation mobile processors. A leaked document alludes to the existence of various "MEDUSA01" jig and block "FP10" socket validation parts. Current-generation Ryzen AI "Strix Point" 300 series APUs utilize the FP8 socket format. Based on the "MEDUSA01" shipping manifest, it seems that a successor will arrive with a larger footprint—measurements of 25 mm x 42.5 mm are repeated throughout the leaked description list. Industry watchdogs surmise that "Medusa Point's" BGA FP10 socket will be approximately 6% larger than its predecessor.

Mid-way through last month, insider theorizations pointed to "Medusa Point" being a chiplet-based design. A "single 12-core Zen 6 CCD" was linked to a TSMC 3 nm-class node, with "N4P" reportedly selected for a separate mobile client I/O die. Readily available 4 nm Ryzen AI "Strix Point" processors are monolithic in nature. Initial inside track info mentioned RDNA 4 technology in the same equation as "Medusa Point," but recent Team Red's recent-ish targeting of "GFX1153" places RDNA 3.5 as the de facto choice.

A recent study by TechInsights is reshaping the narrative around the cost of semiconductor manufacturing in the United States. According to the survey, processing a 300 mm wafer at TSMC's Fab 21 in Phoenix, Arizona, is only about 10% more expensive than similar operations in Taiwan. This insight challenges earlier assumptions based on TSMC founder Morris Chang's comments, which suggested that high fab-building expenses in Arizona made US chip production financially impractical. G. Dan Hutcheson of TechInsights highlighted that the observed cost difference largely reflects the expenses associated with establishing a brand-new facility. "It costs TSMC less than 10% more to process a 300 mm wafer in Arizona than the same wafer made in Taiwan," he explained. The initial higher costs stem from constructing a fab in an unfamiliar market with a new, sometimes unskilled workforce—a scenario not typical for mature manufacturing sites.

A significant portion of the wafer production cost is driven by equipment, which accounts for well over two-thirds of the total expenses. Leading equipment providers like ASML, Applied Materials, and Lam Research charge similar prices globally, effectively neutralizing geographic disparities. Although US labor costs are higher than in Taiwan, the heavy automation in modern fabs means that labor represents less than 2% of the overall cost. Additional logistics for Fab 21, including the return of wafers to Taiwan for dicing, testing, and packaging, add complexity but only minimally affect the overall expense. With plans to expand domestic packaging capabilities, TSMC's approach is proving to be strategically sound. This fresh perspective suggests that the apparent high cost of US fab construction has been exaggerated. TSMC's $100B investment in American semiconductor manufacturing reflects a calculated decision informed by detailed cost analysis—demonstrating that location-based differences become less significant when the equipment dominates expenses.

NVIDIA's CEO Jensen Huang made some interesting commentary for the Financial Times, stating that the company will procure over half a trillion US Dollars worth of electronics over the next four years, and it it plans to keep hundreds of billions from the supply chain procurement in the US. "Overall, we will procure, over the course of the next four years, probably half a trillion dollars worth of electronics in total. And I think we can easily see ourselves manufacturing several hundred billion of it here in the US," said Jensen for FT. NVIDIA currently manufactures its silicon at TSMC's facilities, as well as electronics like motherboards and servers at Foxconn. However, the geopolitical situation is making NVIDIA reconsider its supply chain dependencies, and the company is looking for more US-based manufacturing.

NVIDIA confirmed that its latest "Blackwell" series of GPUs, including the latest Blackwell Ultra, are being manufactured at TSMC's Arizona facilities. TSMC announced a $100 billion investment in its Arizona expansion, and NVIDIA is ready to take up more of TSMC's capacity to meet its ever-growing demand for GPUs. During the GTC 2025 event, Jensen noted that only four cloud service providers will use 3.6 million GPUs this year. That is without any AI labs and enterprises, which are massive consumers of GPUs (xAI only has 200,000 GPU clusters). To continue manufacturing excellence so customers won't suffer, NVIDIA is also looking at other options for supply chain manufacturing partners. Intel, the only US-based company capable of producing advanced silicon, is a potential target for NVIDIA. "We evaluate their foundry technology on a regular basis, and we are ongoing in doing that... We look for opportunities to be a customer of theirs... I have every confidence that Intel can do it," added Jensen, who also stated that NVIDIA is interested in silicon manufacturing and chip packaging services, as Intel's Foveros 3D packaging and other technologies are attractive for Team Green.

Earlier in the week, Apple specialist press outlets picked up on a noted industry analyst's technological forecast for a future iPhone processor design. Jeff Pu—of GF Industries, Hong Kong—predicted that the next-generation A20 SoC would be produced via a TSMC 3 nm (N3P) nodes process. Despite rumors of Apple gaining front row seats at the "2 nm ballgame," the partnership between fabless chip designer and foundry could potentially revisit already covered ground. The A19 chipset was previously linked to N3P (by insiders), with Pu expressing the belief that A20 would utilize the same fundamental lithographic underpinnings; albeit enhanced with TSMC's Chip on Wafer on Substrate (CoWoS) packaging technology (for AI improvements).

This morning, MacRumors followed up on their initial news article—they reported that "wires were crossed" at GF Industries, regarding projections for the (2026) iPhone 18 generation. The publication received direct feedback from the man of the hour: "Jeff Pu (lead Apple analyst) has since clarified that he believes the A20 chip will be manufactured with the N2 process, so the information about the chip using the N3P process should be disregarded. Earlier reports had said the A20 chip would be 2 nm, so rumors align again. This is ultimately good news, as it means the A20 chip should have more substantial performance and power efficiency improvements over the A19 chip." Cutting-edge smartphone processor enthusiasts expressed much disappointment when A20 was (regressively) linked to N3P; the latest revisement should instill some joy. According to industry moles, TSMC is making good progress with its cutting-edge 2 nm node process—mass production is expected to start at some point within the second half of 2025.

NVIDIA has developed co-packaged optics (CPO) technology with TSMC for its upcoming Quantum-X InfiniBand and Spectrum-X Ethernet switches, integrating silicon photonics directly onto switch ASICs. The engineering approach reduces power consumption by 3.5x. It decreases signal loss from 22 dB to 4 dB compared to traditional pluggable optics, addressing critical power and connectivity limitations in large-scale GPU deployments, especially in 10,000+ GPU systems. The architecture incorporates continuous wave laser sources within the switch chassis, consuming 2 W per port, compared to the 10 W required by conventional externally modulated lasers in pluggable modules. This configuration, combined with integrated optical engines that use 7 W versus 20 W for traditional digital signal processors, reduces total optical interconnect power from approximately 72 MW to 21.6 MW in a 400,000 GPU data center scenario.

Specifications for the Quantum 3450-LD InfiniBand model include 144 ports running at 800 Gb/s, delivering 115 Tb/s of aggregate bandwidth using four Quantum-X CPO sockets in a liquid-cooled chassis. The Spectrum-X lineup features the SN6810 with 128 ports at 800 Gb/s (102.4 Tb/s) and the higher-density SN6800 providing 512 ports at 800 Gb/s for 409.6 Tb/s total throughput. The Quantum-X InfiniBand implementation uses a monolithic switch ASIC with six CPO modules supporting 36 ports at 800 Gb/s, while the Spectrum-X Ethernet design employs a multi-chip approach with a central packet processing engine surrounded by eight SerDes chiplets. Both architectures utilize 224 Gb/s signaling per lane with four lanes per port. NVIDIA's Quantum-X switches are scheduled for availability in H2 2025, with Spectrum-X models following in H2 2026.

Over a year ago, industry watchdogs posited that Apple was patiently waiting in line at the front of TSMC's 2 Nanometer GAA "VVIP queue." The securing of cutting-edge manufacturing processes seems to be a consistent priority for the Cupertino, California-headquartered fabless chip designer. Current generation Apple chipsets—at best—utilize TSMC 3 nm (N3E) wafers. Up until very recently, many insiders believed that the projected late 2026 launch of A20 SoC-powered iPhone 18 smartphones would signal a transition to the Taiwanese foundry's advanced 2 nm (N2) node process. Officially, TSMC has roadmapped the start of 2 nm mass production around the second half of 2025.

According to Jeff Pu—a Hong Kong-based analyst at GF Securities—the speculated A20 (2026) chipset could stick with N3P. Leaks suggest that aspects of Apple's next in line "A19" and "A19 Pro" mobile SoCs could be produced via a 3 nm TSMC process. MacRumors has picked up on additional inside track whispers; about Apple M5 processors (for next-gen iPad Pro models) being based on N3P—"likely due to increased wafer costs." Pu reckons that Apple's engineering team has provisioned a major generational improvement with A20's AI capabilities, courtesy of TSMC's Chip on Wafer on Substrate (CoWoS) packaging technology. This significant upgrade is touted to tighten integration between the chip's processor, unified memory, and Neural Engine segments. Revised insider forecasts have positioned A21 chip designs as natural candidates for a shift into 2 nm GAA territories.

According to Reuters, citing The Information, Google will collaborate with MediaTek to develop its seventh-generation Tensor Processing Unit (TPU), which is also known as TPU v7. Google maintains its existing partnership with Broadcom despite the new MediaTek collaboration. The AI accelerator is scheduled for production in 2026, and TSMC is handling manufacturing duties. Google will lead the core architecture design while MediaTek manages I/O and peripheral components, as Economic Daily News reports. This differs from Google's ongoing relationship with Broadcom, which co-develops core TPU architecture. The MediaTek partnership reportedly stems from the company's strong TSMC relationship and lower costs compared to Broadcom.

There is also a possibility that MediaTek could design inference-focused TPU v7 chips while Broadcom focuses on training architecture. Nonetheless, the development of TPU is a massive market as Google is using so many chips that it could use a third company, hypothetically. The development of TPU continues Google's vertical integration strategy for AI infrastructure. Google reduces dependency on NVIDIA hardware by designing proprietary AI chips for internal R&D and cloud operations. At the same time, competitors like OpenAI, Anthropic, and Meta rely heavily on NVIDIA's processors for AI training and inference. At Google's scale, serving billions of queries a day, designing custom chips makes sense from both financial and technological sides. As Google develops its own specific workloads, translating that into hardware acceleration is the game that Google has been playing for years now.

According to Akira Amari, a Japanese politician and semiconductor industry expert, it's unlikely that the US will ever reach self-sufficiency when it comes to semiconductor production. This has nothing to do with foundries, as the US might manage to be self-sufficient in terms or raw chip production needs, but the country is said to be unlikely to be able to reach a complete supply chain of everything else needed to produce the chips. Countries like Japan, Taiwan, the Netherlands, Belgium, South Korea and more are heavily invested in supplying not only components needed to produce semiconductors, but also machinery and chemicals.

Amari is suggesting that these countries should form a co-operative alliance to help strengthen their supply chains at home, rather than putting all eggs in one basket to try and appease the US. This statement comes after TSMC promised to invest an additional US$100 billion over an unspecified time frame in the US. Time will tell if he's right or not, but it's unlikely that any country will ever be self-sufficient when it comes to making semiconductors, regardless of how big they are or what natural resources they have access to locally.

Late last month, industry insiders posited that pleasing progress was being made with Samsung's cutting-edge 2 nm Gate-All-Around (GAA) node process. The rumored abandonment of an older 3 nm GAA-based project—in late 2024—has likely sent the South Korean foundry team into overdrive. A speculated Exynos 2500 flagship mobile processor was previously linked to said 3 nm node, but industry watchdogs believe that company engineers are experimenting with a 2 nm GAA manufacturing process. According to the latest insider report—from FN News SK—Samsung Foundry (SF) has assembled a special "task force (TF)." Allegedly, this elite team will be dedicated to getting a newer "Exynos 2600 chip" over the finish line—suggesting an abandonment of the older "2500" design, or a simple renaming.

Samsung's recent launch of Galaxy S25 series smartphones was reportedly viewed as a disappointing compromise—with all models being powered by Qualcomm's "first-of-its-kind customized Snapdragon 8 Elite Mobile Platform," instead of in-house devised chipsets. According to industry moles, one of the SF task force's main goals is a boosting of 2 nm GAA production yields up to "economically viable" levels (roughly 60-70%)—apparently last month's best result was ~30%. Mass production of prototype chipsets is tipped to start by May. Samsung's reported target of "stabilizing their Exynos 2600" SoC design will ensure that "Galaxy S26 series" devices will not become reliant on Qualcomm internals. Additionally, FN News proposes a bigger picture scenario: "the stabilization of 2 nm (SF2/GAA) products, is expected to speed up the acquisition of customers for Samsung Electronics' foundry division, which is thirsty for leading-edge process customers." A forthcoming rival next-gen mobile chip—Snapdragon 8 Elite Gen 2—is supposedly in the pipeline. The smartphone industry inside track reckons that Qualcomm has signed up with TSMC; with a 2 nm manufacturing process in mind.

Global Unichip Corp. (GUC), the Advanced ASIC Leader, today announced the successful launch of industry's first Universal Chiplet Interconnect Express (UCIe) PHY silicon, achieving a data rate of 32 Gbps per lane, the highest speed defined in the UCIe specification. The 32G UCIe IP, supporting UCIe 2.0, delivers an impressive bandwidth density of 10 Tbps per 1 mm of die edge (5 Tbps/mm full-duplex). This milestone was achieved using TSMC's advanced N3P process and CoWoS packaging technologies, targeting AI, high-performance computing (HPC), xPU, and networking applications.

In this test chip, several dies with North-South and East-West IP orientations are interconnected through CoWoS interposer. The silicon measurements show robust 32 Gbps operation with wide horizontal and vertical eye openings. GUC is working aggressively on the full-corner qualification, and the complete silicon report is expected to be available in the coming quarter.

Scientists from Beijing University have developed the world's first two-dimensional gate-all-around field-effect transistor (GAAFET), establishing a new performance benchmark in domestic semiconductor design. The design, documented in Nature, represents a difference in transistor architecture that could reshape the future of Chinese microelectronics design. Given the reported characteristic of 40% higher performance and 10% improved efficiency compared to the TSMC 3 nm N3 node, it looks rather promising. The research team, headed by Professors Peng Hailin and Qiu Chenguang, engineered a "wafer-scale multi-layer-stacked single-crystalline 2D GAA configuration" that demonstrated superior performance metrics when benchmarked against current industry leaders. The innovation leverages bismuth oxyselenide (Bi₂O₂Se), a novel semiconductor material that maintains exceptional carrier mobility at sub-nanometer dimensions—a critical advantage as the industry struggles to push angstrom-era semiconductor nodes.

"Traditional silicon-based transistors face fundamental physical limitations at extreme scales," explained Professor Peng, who characterized the technology as "the fastest, most efficient transistor ever developed." The 2D GAAFET architecture circumvents the mobility degradation that plagues silicon in ultra-small geometries, allowing for continued performance scaling beyond current nodes. The development comes during China's intensified efforts to achieve semiconductor self-sufficiency, as trade restrictions have limited access to advanced lithography equipment and other critical manufacturing technologies. Even with China developing domestic EUV technology, it is still not "battle" proven. Rather than competing directly with established fabrication processes, the Beijing team has pioneered an entirely different technological approach—what Professor Peng described as "changing lanes entirely" rather than seeking incremental improvements, where China can not compete in the near term.

TSMC is still considering a strategic joint venture to operate Intel's manufacturing capacity, according to four sources close to Reuters that are familiar with the discussions. The proposed arrangement would limit TSMC's ownership to less than 50% and potentially distribute stakes to major American chip designers, including AMD, Broadcom, NVIDIA, and Qualcomm. The initiative emerged following direct intervention from the Trump administration, which has prioritized revitalizing domestic semiconductor manufacturing while maintaining American control of critical technology infrastructure. Under the proposed framework, Intel would spin off its Intel Foundry division, with TSMC acquiring a minority stake and bringing in partner companies as co-investors.

Apple, TSMC's largest customer, is absent from these preliminary discussions, suggesting careful strategic positioning within the competitive ecosystem—however, significant technical and operational challenges are facing the potential joint venture. Intel's manufacturing and real estate assets are valued at approximately $108 billion, requiring substantial capital commitments from prospective partners. More fundamentally, the technological integration presents massive obstacles, as Intel and TSMC utilize fundamentally different manufacturing processes with distinct equipment configurations and material requirements. However, the complex negotiations remain in the early stages, with significant technical, financial, and regulatory hurdles to overcome before any formal agreement materializes. Intel is still not giving the clear green light to spin off rumors.

According to a Reuters technology report, Meta's engineering department is engaged in the testing of their "first in-house chip for training artificial intelligence systems." Two inside sources have declared this significant development milestone; involving a small-scale deployment of early samples. The owner of Facebook could ramp up production, upon initial batches passing muster. Despite a recent-ish showcasing of an open-architecture NVIDIA "Blackwell" GB200 system for enterprise, Meta leadership is reported to be pursuing proprietary solutions. Multiple big players—in the field of artificial intelligence—are attempting to breakaway from a total reliance on Team Green. Last month, press outlets concentrated on OpenAI's alleged finalization of an in-house design, with rumored involvement coming from Broadcom and TSMC.

One of the Reuters industry moles believes that Meta has signed up with TSMC—supposedly, the Taiwanese foundry was responsible for the production of test batches. Tom's Hardware reckons that Meta and Broadcom were working together with the tape out of the social media giant's "first AI training accelerator." Development of the company's "Meta Training and Inference Accelerator" (MTIA) series has stretched back a couple of years—according to Reuters, this multi-part project: "had a wobbly start for years, and at one point scrapped a chip at a similar phase of development...Meta last year, started using an MTIA chip to perform inference, or the process involved in running an AI system as users interact with it, for the recommendation systems that determine which content shows up on Facebook and Instagram news feeds." Leadership is reportedly aiming to get custom silicon solutions up and running for AI training by next year. Past examples of MTIA hardware were deployed with open-source RISC-V cores (for inference tasks), but is not clear whether this architecture will form the basis of Meta's latest AI chip design.

According to a recent Center for Strategic and International Studies report, Huawei got its hand on approximately two million Ascend 910B logic dies through shell companies that misled TSMC. This acquisition violates US export controls designed to restrict China's access to advanced semiconductor technology. The report details how Huawei leveraged intermediaries to procure chiplets for its AI accelerators before TSMC discovered the deception and halted shipments. These components are critical for Huawei's AI hardware roadmap, which progressed from the original Ascend 910 (manufactured by TSMC on N7+ until 2020) to the domestically produced Ascend 910B and 910C chips fabricated at SMIC using first and second-generation 7 nm-class technologies, respectively. Huawei reportedly wanted TSMC-made dies because of manufacturing challenges in domestic chip production. The Ascend 910B and 910C reportedly suffer from poor yields, with approximately 25% of units failing during the advanced packaging process that combines compute dies with HBM memory.

Despite these challenges, the performance gap with market-leading solutions still remains but has narrowed considerably, with the Ascend 910C reportedly delivering 60% of NVIDIA H100's performance. Huawei has executed a strategic stockpiling initiative, particularly for high-bandwidth memory components. The company likely acquired substantial HBM inventory between August and December 2024, when restrictions on advanced memory sales to China were announced but not yet implemented. The semiconductor supply chain breach shows that enforcing technology export controls is challenging, and third parties can still purchase silicon for restricted companies. While Huawei continues building AI infrastructure for both internal projects and external customers, manufacturing constraints may limit its ability to scale deployments against competitors with access to more advanced manufacturing processes. Perhaps a future domestic EUV-based silicon manufacturing flow will allow Huawei to gain access to more advanced domestic production, completely circumventing US-imposed restrictions.

TrendForce's latest research reveals that the global foundry industry exhibited a polarized trend in 4Q24. Advanced process nodes benefited from strong demand in AI servers, flagship smartphone application processors (APs), and new PC platforms, driving high-value wafer shipments. This growth helped offset the slowdown in mature process demand, allowing the top 10 foundries to achieve nearly 10% QoQ revenue growth, reaching US$38.48 billion, and marking another industry record.

TrendForce notes that new U.S. trade tariffs under the Trump administration have started affecting the foundry industry. A surge in recent orders for TVs, PCs, and notebooks bound for the U.S. in 4Q24 is expected to extend into 1Q25. Additionally, China's consumer subsidy program—introduced in late 2024—has spurred early inventory restocking among upstream customers. Combined with persistent demand for TSMC's AI-related chips and advanced packaging, these factors suggest that despite Q1 being a seasonally weak quarter, foundry revenue will only decline slightly.