Tuesday, May 18th 2021
AMD Reportedly Preparing B2 Stepping of Ryzen 5000 Series "Vermeer" Processors, Boost Speeds to Reach 5.0 GHz
AMD is reportedly preparing to launch a B2 stepping of their Ryzen 5000 series of processors, codenamed Vermeer. Thanks to the findings of Patrick Schur, who was lucky to get ahold of AMD's processor codes, we have information that AMD is slowly preparing a B2 stepping of Vermeer processors, to come as a refresh. First off is the alleged Ryzen 9 5950XT 16 core, 32 threaded models which are supposed to feature a base speed of 3.4 GHz, and a boost frequency of 5.0 GHz, entering the 5 GHz world. Another B2 stepping that we know about is an alleged Ryzen 5 5600XT 6 core, 12 threaded design. This one features the same frequencies as its Ryzen 5 5600X variant, meaning 3.7 GHz base, and 4.6 GHz boost frequencies.
Of course, all this information should be taken with a big grain of salt, as we don't know what AMD is planning to do, or how the company plans to manifest any new product launch.
Sources:
Patrick Schur, via VideoCardz
Of course, all this information should be taken with a big grain of salt, as we don't know what AMD is planning to do, or how the company plans to manifest any new product launch.
41 Comments on AMD Reportedly Preparing B2 Stepping of Ryzen 5000 Series "Vermeer" Processors, Boost Speeds to Reach 5.0 GHz
www.techpowerup.com/gpu-specs/a100-sxm4-80-gb.c3746
The single biggest GPU out there!
Nvidia probably makes more $$$ off this than all of their other chips combined :pimp:
Of course all core could be interesting, but I think I will keep my 5950x
"For Intel SKUs it's certainly not margin of error as they have different clocks on the same CPU so it's very easy to say that the higher clocked CPUs will always perform x% better."
This is factually incorrect as performance on Intel's latest 11000 series CPUs can vary as much as 45% simply based on motherboard selection as HardwareUnboxed recently demonstrated. Mind you clock speed isn't the only factor as the Intel 5775C has proven, aside from of course core clocks. Even when reviewers minimize variables and do multiple runs, there is certainly room for margin of error. If you still question that fact, I suggest you try and seriously benchmark some games following industry protocol. From setting uniform game settings to plotting an in-game benchmark route, to ensuring your software environment is correct, to ensuring your data is valid. I know personally that even with all those steps taken, there is still certainly variance and other reviewers like HWUB frequently express this as well.
This is precisely why margin of error exists. Regardless of who many times you run the test, every game is going to have a level of variances to the results, every CPU a bit different performance, and the test itself is limited in it's resolution.
The refresh chips makes sense for someone on a Zen 2 or lower chip. Same for the Zen 2 XT chips they made no sense to anyone on a 3700X or 3800X.
Your next upgrade is zen 4 and to be honest you can probably skip the first gen of the new stuff then leap at the 2nd gen Zen 4 stuff.
Are you deaf?
Typically review outlets chart out their testing methodology with the highest performance in mind. In the case of HWUB's recent video though, the goal was to see performance with mid range B560 motherboards. This wasn't a failure on their end to isolate variables, it was a very valid change in methodology. Objectively neither method (testing with the best vs testing the reasonable) is invalid and show how much variation you can get by changing a single variable.
Heck I've done plenty of benchmark runs myself and I can say as a matter of fact that you'll still see runs that have abnormal variation that need to be investigated and potentially re-done. You clearly have never done serious benchmark yourself as you have no idea of the variance that can exist even when all variables are accounted for. The original argument being made was that higher clock speed equals more performance. No one said anything about clock speed across the same architecture.
5% is the number I originally stated for margin of error as that's the limit of modern testing methodology. My 45% example was in response to another point posited by a prior poster. It was not as to say that all benchmarks have that level of variance.
:kookoo: