Friday, November 15th 2024
Intel Plans to Copy AMD's 3D V-Cache Tech in 2025, Just Not for Desktops
Intel is coming around to the idea of large last-level caches on its processors. Florian Maislinger, a tech communications manager for Intel, in an interview with Der8auer and Bens Hardware, revealed that the company is working on augmenting its processors with large shared L3 caches, however, it will begin doing so only with its server processors. The company is working on a new server/workstation processor for 2025 that comes with cache tiles that augment the shared L3 cache on its server processor, so it excels in the kind of workloads AMD's EPYC "Genoa-X" processors and upcoming "Turin-X" processors excel at—technical computing. On "Genoa-X" processors, each of the up to 12 "Zen 4" CCDs comes with stacked 3D V-Cache, which is found to have a profound impact on performance in applications that are cache-sensitive, such as the Ansys suite, OpenFOAM, etc.
The interview reveals that the server processor with large last-level cache should come out in 2025, however there is no such effort on the horizon for the company's client processors, such as the Core Ultra "Arrow Lake-S," at least not in the year 2025. The company's recently launched "Arrow Lake-S" desktop processors do not provide a generational gaming performance uplift over the 14th Gen Core "Raptor Lake Refresh," however, Intel claims to have identified certain correctable reasons for the gaming performance falling below expectations, and is hoping to release updates to the processor (possibly in the form of a new microcode, or something at the OS-vendor level). This, the company claims, should improve the gaming performance of "Arrow Lake-S."
Sources:
Der8auer (YouTube), VideoCardz, HardwareLuxx.de
The interview reveals that the server processor with large last-level cache should come out in 2025, however there is no such effort on the horizon for the company's client processors, such as the Core Ultra "Arrow Lake-S," at least not in the year 2025. The company's recently launched "Arrow Lake-S" desktop processors do not provide a generational gaming performance uplift over the 14th Gen Core "Raptor Lake Refresh," however, Intel claims to have identified certain correctable reasons for the gaming performance falling below expectations, and is hoping to release updates to the processor (possibly in the form of a new microcode, or something at the OS-vendor level). This, the company claims, should improve the gaming performance of "Arrow Lake-S."
77 Comments on Intel Plans to Copy AMD's 3D V-Cache Tech in 2025, Just Not for Desktops
neverlater.:DThey still need to figure out how to lower their CPU's wattage is just crazy.
Anyways lost opportunity for Intel.
www.intel.com/content/www/us/en/products/sku/88040/intel-core-i75775c-processor-6m-cache-up-to-3-70-ghz/specifications.html
Again, the CPU includes 6MB of L3 cache and 128MB of eDRAM.
www.tomshardware.com/reviews/intel-core-i7-5775c-i5-5675c-broadwell,4169.html
It's up to discussion. I see the 7800X3d Cache as 4th level one like the EDRAM cache of the i7-5775C
64MB of SRAM for L3 vs 128MB of EDRAM for L4.
Otherwise you may as well argue that systems with soldered RAM are better than those with removable as it's attached to the system. Just being attached doesn't make them better or have higher performance.
I hope intel does provide chips with far higher L3 cache. Should give us some competition in the gaming CPU world, and may encourage more game devs and other workloads to be designed to take advantage of it even more.
I always try to use the datasheet or specification from the manufacturer:
www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-7-7800x3d.htmlthe same stupidity for the 9800X3d see: www.amd.com/en/products/processors/desktops/ryzen/9000-series/amd-ryzen-7-9800x3d.html
I can not take any manufacturer serious who is unable to provide proper specifications on the specifications page.
Something like
32MiB CACHE TYPE x
64MiB CACHE type y
which also give me the next question. MB or MiB units?
I think the units are wrong also. The units should be MiB. What I read about microcontrollers and such, it's always binary. not the human 10er base. Its base 2.
simple.wikipedia.org/wiki/Mebibyte
e.g. I saw in past months that more and more software in gnu linux already use the correct units. Base 2 or Base 10.
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It up to discussion. What a Level Cache is? How you define a Level 1, Level 2, Level 3 and Level 4 Cache.
I do not think that the latency of a Level 4 cache is an argument. I do agree - AMD may be first with a 3D-Type of Cache Module for a Level 4 Cache. But maybe not the first who uses Level 4 Cache the first time.
Cache bandwidth and latency are two key factors on why the L1/2/3 caches are so impactful to performance. So the high latency of the eDRAM is a massive disadvantage and why it was referred to as an L4 style memory.
If it was similar then we'd see far better performance impact from that older intel chip, and we'd see issues with worse performance for code needing smaller L3 cache on X3D vs non X3D if the extra L3 cache on X3D didn't perform as well as standard L3 cache.
Tbh it's just a matter of memory hierarchy, and at this point we can add storage and different memory levels as well. What is a "cache", "memory" or "storage" ends up moot under this view since what matters is their speed/latency.
But it's hard to find something more deserving of the title "waste of sand" than throwing a bunch of L3 cache on a die, as it's only a tiny subset of very poorly optimized code which significantly benefit from it, namely certain outliers in applications and games running at very unrealistically low GPU load. It would be much better to have a CPU with 5% more computational power, especially down the road, as future games are likely to become more demanding so the bottleneck will be computational performance, not "artificial" ones running games at hundreds of frames per second.
For CPUs to advance, they should stop focusing on gimmicks and make actual architectural advancements instead. Large L3 caches is a waste of precious development resources as well as production capacity.
You can only go so far with shrinking nodes and they are at the mercy of TSMC in that respect. Secondly I don't think Epyc processors that don't run client workloads that benefit greatly from cache is a bad idea. Client Desktop doesn't really drive anything its all enterprise. Better to deal with the low hanging fruit as you continue to address overall processor improvement than trying to hit the ball of the park every single launch. I consider that a better use of development and production capacity as the core counts go up and processors get faster feeding the cores will always be an issue. If you can help that with cache's and not having to add additional memory channels etc I consider that a win.
Extra CPU cycles don't do anything if the CPU is waiting for the data from memory. That's why the 1% lows massively benefit, and performance is better even if the frequency is lower. I have a very high end GPU yet I noticed the difference when playing at 4k. Lows, frame pace consistency etc all benefit and games that used to have very periodic stutters have none compared to my 5ghz 9900k.
I have my 7800X3D at 40-60W providing a much better, much more consistent experience with the same GPU and screen than my 9900k that was eating 150W.
Back to the days of minor performance increases and new board is a requirement for 2% performance increase….
But good on Intel, doing what they would sue AMD for, copying a good idea. I wonder if they will be paying royalties?