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VIA Centaur CHA

8
Cores
8
Threads
70 W
TDP
1200 MHz
Frequency
2.5 GHz
Boost
CHA
Codename
VIA Socket 2084
Socket
Front
Brutus
Front
Die Shot
Die Shot
Installed
Installed
VIA Socket 2084
VIA Socket 2084
The VIA Centaur CHA was a server/workstation processor with 8 cores, that was never released. It is part of the CHA lineup, using the CNS architecture with VIA Socket 2084. To further increase overall system performance, up to two Centaur CHA CPUs can link up in a multi-processor (SMP) configuration. Centaur CHA has 16 MB of L3 cache and operates at 1200 MHz by default, but can boost up to 2.5 GHz, depending on the workload. VIA is building the Centaur CHA on a 16 nm production process, the transistor count is unknown. The silicon die of the chip is not fabricated at VIA, but at the foundry of TSMC. You may freely adjust the unlocked multiplier on Centaur CHA, which simplifies overclocking greatly, as you can easily dial in any overclocking frequency.
With a TDP of 70 W, the Centaur CHA consumes typical power levels for a modern PC. VIA's processor supports DDR4 memory with a quad-channel interface. The highest officially supported memory speed is 3200 MT/s, but with overclocking (and the right memory modules) you can go even higher. ECC memory is supported, too, which is an important capability for mission-critical systems, to avoid data corruption. For communication with other components in the system, Centaur CHA uses a PCI-Express Gen 3 connection. This processor lacks integrated graphics, you might need a graphics card.
Programs using Advanced Vector Extensions (AVX) will run on this processor, boosting performance for calculation-heavy applications. Besides AVX, VIA has added support for the newer AVX2 and AVX-512 instructions, too.

Physical

Socket: VIA Socket 2084
Foundry: TSMC
Process Size: 16 nm
Die Size: 195 mm²
Package: FC-LGA2084

Processor

Market: Server/Workstation
Production Status: End-of-life
Release Date: Never Released
Intended Release:2H 2020
Part#: unknown

Performance

Frequency: 1200 MHz
Turbo Clock: up to 2.5 GHz
Base Clock: 100 MHz
Multiplier: 12.0x
Multiplier Unlocked: Yes
Voltage: 1.1 V
NCORE NPU:up to 20.5 TOPS
TDP: 70 W

Architecture

Codename: CHA
Generation: CHA
(CNS)
Memory Support: DDR4
Rated Speed: 3200 MT/s
Memory Bus: Quad-channel
ECC Memory: Yes
PCI-Express: Gen 3, 44 Lanes
(CPU only)
Chipset: Zhaoxin ZX-200

Core Config

# of Cores: 8
# of Threads: 8
SMP # CPUs: 2
Integrated Graphics: N/A

Cache

Cache L1: 64 KB (per core)
Cache L2: 256 KB (per core)
Cache L3: 16 MB (shared)

Features

  • MMX
  • SSE
  • SSE2
  • SSE3
  • SSSE3
  • SSE4.1
  • SSE4.2
  • AVX
  • AVX2
  • AVX-512F
  • AVX-512_IFMA
  • AVX-512BW
  • AVX-512CD
  • AVX-512DQ
  • AVX-512_VBMI
  • AVX-512VL
  • BMI
  • BMI2
  • ABM
  • FMA3
  • VIA FEMMS
  • ADX
  • DEP
  • VMX
  • ACE
  • ACE2
  • SMEP
  • SMAP
  • UMIP
  • MPX
  • EM64T
  • AES-NI
  • RDRAND
  • RDSEED
  • SHA-

Notes

CHA SoC configuration combines eight CNS x86-64 cores with a 16-slice, 32,768-bit VLIW "NCORE" neural processing unit.
Jul 1st, 2024 14:47 EDT change timezone

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