Next gen is Foveros (advanced tiles with backside power delivery and disaggregated nodes).
That combined with RibbonFET (gate all around transistors) should lead to a significant jump in performance per watt, while also avoiding the high idle/low load power draw Zen chips are known for, due to their simple chiplet design with an IO die built on an old process. The Intel design has a single "E core" within the "IO die" equivalent too, so that should enable even lower idle than what Intel currently has, since the main CPU die won't need to be even powered on for idle, or things like video decoding (if you're only watching something on YouTube or from a file, the main CPU die can be powered off).
Apparently Zen 6 is going to move to a better organic/silicon substrate (similar to Intel's own packaging tech with Foveros), which should be one of the options available from TSMC. I do wonder if that will still be on AM5 though.
Here's the current round up from the TPU upcoming hardware article.
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