NVIDIA today reported revenue for the second quarter ended July 28, 2024, of $30.0 billion, up 15% from the previous quarter and up 122% from a year ago. For the quarter, GAAP earnings per diluted share was $0.67, up 12% from the previous quarter and up 168% from a year ago. Non-GAAP earnings per diluted share was $0.68, up 11% from the previous quarter and up 152% from a year ago.

"Hopper demand remains strong, and the anticipation for Blackwell is incredible," said Jensen Huang, founder and CEO of NVIDIA. "NVIDIA achieved record revenues as global data centers are in full throttle to modernize the entire computing stack with accelerated computing and generative AI."

At Gamescom, Korean peripheral manufacturer Pulsar showed many upcoming releases slated for 2024 and 2025, some of which had to be flown in overnight fresh out of the factory. Aside from updates to existing mice series such as the Xlite, X2, X2H, or X2A, Pulsar also showed wholly new shapes and concepts.

Pulsar XS-1 sensor and in-house firmware
Shared between all new mouse releases from Pulsar will be improvements to the sensor and firmware. Based on PixArt's latest PAW3950 sensor, the custom XS-1 sensor will be capable of CPI adjustment in increments of 10, which would be restricted to steps of 50 on a regular PAW3950. After two years of development time, Pulsar's own in-house developed firmware is also nearing completion, and will feature multiple improvements over the third-party solution used previously. More specifically, refined double-click prevention will be included, slam-click prevention is implemented, and latency has been lowered further across the board. The firmware change will be accompanied by a new software as well, which will be exclusive to all newer models featuring the XS-1.

Intel has begun sampling the test tools for their "Oak Stream" platform which will house the "Diamond Rapids" generation of processors sometime in late 2025 or early 2026. Previously rumored to continue using the "Birch Stream" platform LGA 7529 socket that will soon be shipping with the 288-core flavor of the "Sierra Forest" efficiency core Xeons as well as 120-core "Granite Rapids" performance core Xeons, "Diamond Rapids" appears to instead be moving up to a substantially larger LGA 9324 socket. This is Intel's next-next generation of Xeon from what is shipping today, following up on the next-gen Intel 18A based "Clearwater Forest" which was only just reported to be powering on earlier this month. Other than the codename there is almost nothing currently known about "Diamond Rapids" but the rumor mill is already fired up and mentioning things such as increased core counts, 16 DRAM channels (similar to what AMD is expected to introduce with EPYC "Venice") and PCI-E 6.0 support.

The LGA 9324 test interposer for use with Intel's Gen 5 VR Test Tool that appeared on their Design-in Tools storefront before the page went to a 404 error carried a price tag of $900 USD and stipulated that this was a pre-order with an expected shipment date in Q4 2024.

Intel's Sales and Marketing Group (SMG) has announced a 35% reduction in costs as the company looks to streamline operations and adapt to challenging market conditions. The cuts, revealed during an all-hands meeting on August 5th, will impact both jobs and marketing expenses within the SMG. Intel has directed the group to "simplify programs end-to-end" by the end of the year, a directive that comes on the heels of the company's announcement that it would lay off 15% of its global workforce to save $10 billion in operating expenses. "We are becoming a simpler, leaner, and more agile company that's easier for partners and customers to work with while ensuring we focus our investments on areas where we see the greatest opportunities for innovation and growth," Intel said in a statement to CRN. The company emphasized that this restructuring is about "building a stronger Intel for the future," with partners integral to its plans.

The job cuts within the SMG are expected to target overlapping responsibilities, such as account managers and industry-focused teams, which can confuse customers navigating Intel's complex organization. Additionally, the company plans to significantly reduce its marketing budget and simplify programs, aiming to save at least $100 million in the latter half of 2024 and an additional $300 million in the first half of 2025. The impact will also be felt in Intel's market development fund (MDF), a crucial tool for supporting OEMs and other partners through events, training, and more. An ex-Intel executive warned that the MDF had become vital as the company's product leadership waned, allowing it to maintain valuable relationships with partners. As Intel navigates these changes, its partners are bracing for the impact, with one CEO describing the situation as everyone "hunkering down and just waiting to hear something." Another partner executive expressed concerns about Intel's ability to maintain the level of service and support its customers have come to expect.

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

Intel today announced that its lead products on Intel 18A, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), are out of the fab and have powered-on and booted operating systems. These milestones were achieved less than two quarters after tape-out, with both products on track to start production in 2025. The company also announced that the first external customer is expected to tape out on Intel 18A in the first half of next year.

"We are pioneering multiple systems foundry technologies for the AI era and delivering a full stack of innovation that's essential to the next generation of products for Intel and our foundry customers. We are encouraged by our progress and are working closely with customers to bring Intel 18A to market in 2025." -Kevin O'Buckley, Intel senior vice president and general manager of Foundry Services

According to sources close to Bloomberg, Intel plans to cut 10,000 jobs from its global workforce. The news comes amid heavy pressure on the semiconductor giant, which has been on a steady decline over the years, while other industry rivals like AMD and NVIDIA have been rising and taking market share in various areas from Intel. It is reported that Intel currently has 110,000 employees globally, and reducing the workforce by 10,000 would net Intel around 100,000 global employees left. These figures exclude employees from spun-out units like Altera FPGA company, which is under Intel's ownership. Intel's aim to reduce its workforce is expected to come with a significant cost benefit to the company, with projected savings of $10 billion by 2025.

The news isn't yet official, but it is expected to see the light of the day as soon as this week. As Intel's CEO Pat Gelsinger invests heavily into the fab construction and development of next-generation products, there have been a few notes that Intel would have to overcome some challenges shortly to reach its long-term goals like more advanced silicon manufacturing facilities and new products for AI/HPC and client sector. One of those short-term measures is reducing the workforce to cut down expenses. Intel has reduced its workforce before. In 2022, the company announced reduced spending in non-critical areas and reducing the workforce, and in 2023, cut the workforce by 5% to 124,800 employees last year, only to be left with 110,000 employees in 2024.

AMD reportedly plans to incorporate glass substrates into its high-performance system-in-packages (SiPs) sometimes between 2025 and 2026. Glass substrates offer several advantages over traditional organic substrates, including superior flatness, thermal properties, and mechanical strength. These characteristics make them well-suited for advanced SiPs containing multiple chiplets, especially in data center applications where performance and durability are critical. The adoption of glass substrates aligns with the industry's broader trend towards more complex chip designs. As leading-edge process technologies become increasingly expensive and yield gains diminish, manufacturers turn to multi-chiplet designs to improve performance. AMD's current EPYC server processors already incorporate up to 13 chiplets, while its Instinct AI accelerators feature 22 pieces of silicon. A more extreme testament is Intel's Ponte Vecchio, which utilized 63 tiles in a single package.

Glass substrates could enable AMD to create even more complex designs without relying on costly interposers, potentially reducing overall production expenses. This technology could further boost the performance of AI and HPC accelerators, which are a growing market and require constant innovation. The glass substrate market is heating up, with major players like Intel, Samsung, and LG Innotek also investing heavily in this technology. Market projections suggest explosive growth, from $23 million in 2024 to $4.2 billion by 2034. Last year, Intel committed to investing up to 1.3 trillion Won (almost one billion USD) to start applying glass substrates to its processors by 2028. Everything suggests that glass substrates are the future of chip design, and we await to see first high-volume production designs.

Taiwanese semiconductor giant TSMC is reportedly planning to increase its wafer prices by up to 10% in 2025, according to a Morgan Stanley note cited by investor Eric Jhonsa. The move comes as demand for cutting-edge processors in smartphones, PCs, AI accelerators, and HPC continues to surge. Industry insiders reveal that TSMC's state-of-the-art 4 nm and 5 nm nodes, used for AI and HPC customers such as AMD, NVIDIA, and Intel, could see up to 10% price hikes. This increase would push the cost of 4 nm-class wafers from $18,000 to approximately $20,000, representing a significant 25% rise since early 2021 for some clients and an 11% rise from the last price hike. Talks about price hikes with major smartphone manufacturers like Apple have proven challenging, but there are indications that modest price increases are being accepted across the industry. Morgan Stanley analysts project a 4% average selling price increase for 3 nm wafers in 2025, which are currently priced at $20,000 or more per wafer.

Mature nodes like 16 nm are unlikely to see price increases due to sufficient capacity. However, TSMC is signaling potential shortages in leading-edge capacity to encourage customers to secure their allocations. Adding to the industry's challenges, advanced chip-on-wafer-on-substrate (CoWoS) packaging prices are expected to rise by 20% over the next two years, following previous increases in 2022 and 2023. TSMC aims to boost its gross margin to 53-54% by 2025, anticipating that customers will absorb these additional costs. The impact of these price hikes on end-user products remains uncertain. Competing foundries like Intel and Samsung may seize this opportunity to offer more competitive pricing, potentially prompting some chip designers to consider alternative manufacturing options. Additionally, TSMC's customers could reportedly be unable to secure their capacity allocation without "appreciating TSMC's value."

The PC market gathered momentum in Q2 2024, with worldwide shipments of desktops and notebooks up 3.4% year-on-year, reaching 62.8 million units. Shipments of notebooks (including mobile workstations) hit 50 million units, growing 4%. Desktops (including desktop workstations), which constitute 20% of the total PC market, experienced a slight 1% growth, totaling 12.8 million units. The stage is now set for accelerated growth as the refresh cycle driven by the Windows 11 transition and AI PC adoption ramps up over the next four quarters.

"The PC industry is going from strength to strength with a third consecutive quarter of growth," said Ishan Dutt, Principal Analyst at Canalys. "The market turnaround is coinciding with exciting announcements from vendors and chipset manufacturers as their AI PC roadmaps transition from promise to reality. The quarter culminated with the launch of the first Copilot+ PCs powered by Snapdragon processors and more clarity around Apple's AI strategy with the announcement of the Apple Intelligence suite of features for Mac, iPad and iPhone. Beyond these innovations, the market will start to benefit even more from its biggest tailwind - a ramp-up in PC demand driven by the Windows 11 refresh cycle. The vast majority of channel partners surveyed by Canalys in June indicated that Windows 10 end-of-life is likely to impact customer refresh plans most in either the second half of 2024 or the first half of 2025, suggesting that shipment growth will only gather steam in upcoming quarters."

0patch plans to combat Microsoft's ending Windows 10 support by offering unofficial security updates for the 2015 operating system. Microsoft is ending Windows 10 security updates on October 14, 2025, after which the OS will stop receiving patches for vulnerabilities. The Redmond giant will provide you with an option to update your Windows 10 build, however, with a hefty fee slapped. Extended Security Updates (ESU) pricing structure follows a tiered model that doubles each year. From October 2025 to October 2026, the cost is $61 per device. The following year, from October 2026 to October 2027, the price increases to $122 per device. In the final year, spanning October 2027 to October 2028, the cost rises to $244 per device. For users planning to maintain Windows 10 until October 2028, the total expense over the three-year period would amount to $427 per device.

However, 0patch, a company focused on providing unofficial security updates for Windows OSes, will provide Windows 10 users with free and paid security updates post-end of service. Their system focuses on delivering targeted "micropatches" for critical vulnerabilities that emerge after Microsoft's official support ends. These micropatches are designed to be extremely precise and minimal, often consisting of just a few CPU instructions. A key feature of 0patch's approach is its non-invasive nature. The patches are applied directly to running processes in the computer's memory, leaving the original Microsoft files untouched. This method allows for rapid deployment of security fixes without requiring system reboots or interrupting user activities. The patching process is designed to be seamless and virtually unnoticeable to users. For instance, a user working on a document wouldn't experience any disruption while a micropatch is being applied. This approach is particularly beneficial for servers, where continuous uptime is crucial, as patches can be implemented without any downtime.

Micron has announced more precise timeframes for the commencement of operations at its two new memory facilities in the United States during its Q3 FY2024 results presentation. The company expects these fabs, located in Idaho and New York, to begin production between late 2026 and 2029. The Idaho fab, currently under construction near Boise, is slated to start operations between September 2026 and September 2027. Meanwhile, the New York facility is projected to come online in the calendar year 2028 or later, pending the completion of regulatory and permitting processes. These timelines align with Micron's original plans announced in 2022 despite recent spending optimizations. The company emphasizes that these investments are crucial to support supply growth in the latter half of this decade.

Micron's capital expenditure for FY2024 is set at approximately $8 billion, with a planned increase to around $12 billion in FY2025. This substantial rise in spending, targeting a mid-30s percentage of revenue, will support various technological advancements and facility expansions. A substantial portion of this increased investment - over $2 billion - will be dedicated to constructing the new fabs in Idaho and New York. Additional funds will support high-bandwidth memory assembly and testing, as well as the development of other fabrication and back-end facilities. Sanjay Mehrotra, Micron's CEO, underscored the importance of these investments, stating that the new capacity is essential to meet long-term demand and maintain the company's market position. He added that these expansions, combined with ongoing technology transitions in Asian facilities, will enable Micron to grow its memory bit supply in line with industry demand.

PC (excluding tablets) shipments to the United States grew 5% year-on-year to 14.8 million units in Q1 2024. The consumer and SMB segments were the key growth drivers, both witnessing shipment increases above 9% year-on-year in the first quarter. With a strong start to the year, the market is now poised for a healthy recovery trajectory amid the ongoing Windows refresh cycle. Total PC shipments to the US are expected to hit 69 million units in 2024 before growing another 8% to 75 million units in 2025.

For the third consecutive quarter, the consumer segment showed the best performance in the US market. "Continued discounting after the holiday season boosted consumer demand for PCs into the start of 2024," said Greg Davis, Analyst at Canalys. "However, the first quarter also saw an uptick in commercial sector performance. Shipment growth in small and medium businesses indicates that the anticipated refresh brought by the Windows 10 end-of-life is underway. With enterprise customers set to follow suit, the near-term outlook for the market remains highly positive."

The PC (desktops, notebooks, and workstations) market in Mainland China is forecast to contract by 1% in 2024 according to the latest Canalys data. The first quarter of the year already saw a sharp decline, with shipments down 12%, in contrast to the global market which returned to growth. Desktop shipments are expected to perform well in 2024, growing 10% annually as they benefit from commercial sector refresh demand, especially from large state-held enterprises and local governments. Notebook shipments are set to drop 5%, as demand from consumers and the private sector is anticipated to remain cautious on short-term expenditure such as PCs.

China's PC market trajectory is diverging from global trends in its recovery journey. In Q1 2024, the commercial sector bore the brunt of the market downturn, undergoing a 19% decline due to weak IT spending by large enterprises. The decline in consumer shipments was milder, with shipments dropping 8%. However, despite the muted performance in 2024, significant local developments point to a stronger market in 2025, in which PC shipments are expected to grow 12%.

The race is on for memory manufacturers to bring the next generation GDDR7 graphics memory into mass production. While rivals Samsung and Micron are aiming to have GDDR7 chips available in Q4 of 2024, South Korean semiconductor giant SK Hynix revealed at Computex 2024 that it won't kick off mass production until the first quarter of 2025. GDDR7 is the upcoming JEDEC standard for high-performance graphics memory, succeeding the current GDDR6 and GDDR6X specifications. The new tech promises significantly increased bandwidth and capacities to feed the appetites of next-wave GPUs and AI accelerators. At its Computex booth, SK Hynix showed off engineering samples of its forthcoming GDDR7 chips, with plans for both 16 Gb and 24 Gb densities.

The company is targeting blazing-fast 40 Gbps data transfer rates with its GDDR7 offerings, outpacing the 32 Gbps rates its competitors are starting with on 16 Gb parts. If realized, higher speeds could give SK Hynix an edge, at least initially. While trailing a quarter or two behind Micron and Samsung isn't ideal, SK Hynix claims having working samples now validates its design and allows partners to begin testing and qualification. Mass production timing for standardized memories also doesn't necessarily indicate a company is "late" - it simply means another vendor secured an earlier production window with a specific customer. The GDDR7 transition is critical for SK Hynix and others, given the insatiable demand for high-bandwidth memory to power AI, graphics, and other data-intensive workloads. Hitting its stated Q1 2025 mass production target could ensure SK Hynix doesn't fall too far behind in the high-stakes GDDR7 race, with faster and higher-density chips to potentially follow shortly after volume ramp.

Last year, Micron unveiled plans to construct a cutting-edge DRAM factory in Hiroshima, Japan. However, the project has faced a significant two-year delay, pushing back the initial timeline for mass production of the company's most advanced memory products. Originally slated to begin mass production by the end of 2025, Micron now aims to have the new facility operational by 2027. The complexity of integrating extreme ultraviolet lithography (EUV) equipment, which enables the production of highly advanced chips, has contributed to the delay. The Hiroshima plant will produce next-generation 1-gamma DRAM and high-bandwidth memory (HBM) designed for generative AI applications. Micron expects the HBM market, currently dominated by rivals SK Hynix and Samsung, to experience rapid growth, with the company targeting a 25% market share by 2025.

The project is expected to cost between 600 and 800 billion Japanese yen ($3.8 to $5.1 billion), with Japan's government covering one-third of the cost. Micron has received a subsidy of up to 192 billion yen ($1.2 billion) for construction and equipment, as well as a subsidy to cover half of the necessary funding to produce HBM at the plant, amounting to 25 billion yen ($159 million). Despite the delay, the increased investment in the factory reflects Micron's commitment to advancing its memory technology and capitalizing on the growing demand for HBM. An indication of that is the fact that customers have pre-ordered 100% of the HBM capacity for 2024, not leaving a single HBM die unused.

According to the report from Volksstimme.de, Intel has delayed its Magdeburg fab construction until 2025 due to difficulties in acquiring suitable land. The company had initially planned to begin construction in 2024, but the process has been slowed significantly due to the availability of suitable land. The Magdeburg plant is a significant investment for Intel, with the company planning to invest around €30 billion in the facility. The plant is expected to create thousands of jobs and play a crucial role in the company's European expansion plans. However, the delay in construction is likely to impact these plans and may result in a longer timeline for the plant's completion.

The delay is attributed to the difficulty in finding suitable land for the plant. Intel's original plan of producing a factory on the land concluded that there was humus-rich black soil up to 40 cm in the ground, which would get removed for usage by agricultural fields in Germany. However, now the top layer of black soil, which needs to be excavated, is measured up to 90 cm in depth, which doesn't allow fab construction to start and requires the removal of the soil in order to satisfy the safety regulations. This useful soil has to be extracted first before being "contaminated" with concrete and other types of foundation soils like gravel. The state of Saxony-Anhalt postponed the construction until the required soil was removed and regulations were met. This will supposedly happen by the end of 2024, and construction will start in 2025.

Intel's upcoming Falcon Shores GPU is shaping up to be a powerhouse for AI and high-performance computing (HPC) workloads, but it will also be an extreme power hog. The processor, combining Gaudi and Ponte Vecchio successors into a single GPU, is expected to consume an astonishing 1500 W of power - more than even Nvidia's beefy B200 accelerator, which draws 1000 W. This immense power consumption will require advanced cooling solutions to ensure the Falcon Shores GPU operates efficiently and safely. Intel's partners may turn to liquid cooling or even full immersion liquid cooling, a technology Intel has been promoting for power-hungry data center hardware. The high power draw is the cost of the Falcon Shores GPU's formidable performance promises. Intel claims it will deliver 5x higher performance per watt and 5x more memory capacity and bandwidth compared to its Ponte Vecchio products.

Intel may need to develop proprietary hardware modules or a new Open Accelerator Module (OAM) spec to support such extreme power levels, as the current OAM 2.0 tops out around 1000 W. Slated for release in 2025, the Falcon Shores GPU will be Intel's GPU IP based on its next-gen Xe graphics architecture. It aims to be a major player in the AI accelerator market, backed by Intel's robust oneAPI software development ecosystem. While the 1500 W power consumption is sure to raise eyebrows, Intel is betting that the Falcon Shores GPU's supposedly impressive performance will make it an enticing option for AI and HPC customers willing to invest in robust cooling infrastructure. The ultra-high-end accelerator market is heating up, and the HPC accelerator market needs a Ponte Vecchio successor.

According to ServeTheHome, Intel has decided to discontinue its high-performance computing (HPC) product line, Ponte Vecchio, and shift its focus towards developing its next-generation data center GPU, codenamed Falcon Shores. This decision comes as Intel aims to streamline its operations and concentrate its resources on the most promising and competitive offerings. The Ponte Vecchio GPU, released in January of 2023, was intended to be Intel's flagship product for the HPC market, competing against the likes of NVIDIA's H100 and AMD's Instinct MI series. However, despite its impressive specifications and features, Ponte Vecchio faced significant delays and challenges in its development and production cycle. Intel's decision to abandon Ponte Vecchio is pragmatic, recognizing the intense competition and rapidly evolving landscape of the data center GPU market.

By pivoting its attention to Falcon Shores, Intel aims to deliver a more competitive and cutting-edge solution that can effectively challenge the dominance of its rivals. Falcon Shores, slated for release in 2025, is expected to leverage Intel's latest process node and architectural innovations. Currently, Intel has Gaudi 2 and Gaudi 3 accelerators for AI. However, the HPC segment is left without a clear leader in the company's product offerings. Intel's Ponte Vecchio is powering Aurora exascale supercomputer, which is the latest submission to the TOP500 supercomputer lists. This is also coming after the Rialto Bridge cancellation, which was supposed to be an HPC-focused card. In the future, the company will focus only on the Falcon Shores accelerator, which will unify HPC and AI needs for high-precision FP64 and lower-precision FP16/INT8.

The rollout of SiPearl's much-anticipated Rhea processor for European supercomputers has been pushed back by a year to 2025, but the delay comes with a silver lining - a significant upgrade in core count and potential performance. Originally slated to arrive in 2024 with 72 cores, the homegrown high-performance chip will now pack 80 cores when it eventually launches. This decisive move by SiPearl and its partners is a strategic choice to ensure the utmost quality and capabilities for the flagship European processor. The additional 12 months will allow the engineering teams to further refine the chip's architecture, carry out extensive testing, and optimize software stacks to take full advantage of Rhea's computing power. Now called the Rhea1, the chip is a crucial component of the European Processor Initiative's mission to develop domestic high-performance computing technologies and reduce reliance on foreign processors. Supercomputer-scale simulations spanning climate science, drug discovery, energy research and more all require astonishing amounts of raw compute grunt.

By scaling up to 80 cores based on the latest Arm Neoverse V1, Rhea1 aims to go toe-to-toe with the world's most powerful processors optimized for supercomputing workloads. The SiPearl wants to utilize TSCM's N6 manufacturing process. The CPU will have 256-bit DDR5 memory connections, 104 PCIe 5.0 lanes, and four stacks of HBM2E memory. The roadmap shift also provides more time for the expansive European supercomputing ecosystem to prepare robust software stacks tailored for the upgraded Rhea silicon. Ensuring a smooth deployment with existing models and enabling future breakthroughs are top priorities. While the delay is a setback for SiPearl's launch schedule, the substantial upgrade could pay significant dividends for Europe's ambitions to join the elite ranks of worldwide supercomputer power. All eyes will be on Rhea's delivery in 2025, mainly from Europe's governments, which are funding the project.

Intel's CEO, Pat Gelsinger, has confirmed that the upcoming 18A process of the Panther Lake CPU generation is on schedule for a mid-2025 release, which aligns with the initial projection. This development marks a significant milestone in the company's ongoing efforts to integrate AI capabilities into its processors. The mid-2025 release date is expected to follow the debut of Intel's Arrow Lake process in late 2024 or early 2025, a release that holds the promise of significant advancements in AI computing. During Intel's Q1 2024 Quarterly Results, Gelsinger expressed confidence in the company's AI capabilities, stating that the Core Ultra platform currently delivers leadership AI performance and that the next-generation platforms, Lunar Lake and Arrow Lake, will launch later this year, tripling AI performance. He also mentioned that the Panther Lake generation, set to release in 2025, will grow AI performance up to an additional 2x.

The Panther Lake generation represents the culmination of three generations of work in a short time and is expected to continue Intel's iterative approach. This transition is marked by a shift from a hybrid architecture, a combination of different types of processors, to a disaggregated die, where different components of the processor are separated, as AI computing becomes increasingly prominent. This strategic move is aimed at optimizing AI performance and flexibility. This marks the third generation of the Intel Core Ultra series, following Ultra 100 (Meteor Lake), Ultra 200 (Arrow Lake), and Lunar Lake (200V). Intel's release strategy mirrors the pattern set by the Hybrid Architecture, with Alder Lake debuting in 2021, followed by Raptor Lake in 2022, and a refreshed Raptor Lake released last year to bridge the gap until LGA 1851 was ready. However, Intel's roadmap has seen adjustments in the past, such as the initial promise of an Arrow Lake release before the end of 2024, which was later retracted. The mid-2025 release of Panther Lake aligns with rumors of Arrow Lake's late 2024 or early 2025 debut, suggesting that the 18A process CPU generation could debut several months after Arrow Lake.

While everyone has been focused on shipping an AI-enhanced product recently, one tech giant didn't appear to be bothered- Apple. However, according to Mark Gurman from Bloomberg, Apple is readying an overhaul of its Apple Silicon M-series chips to embed AI processing capabilities at the processor level. As the report indicates, Apple is preparing an update for late 2024 and early 2025 with the M4 series of chips, which will reportedly feature AI processing units similar to those found in other commercial chips. There should be three levels of the M4 series, with the entry-level M4 codenamed Donan, the mid-level M4 chip codenamed Brava, and the high-end M4 chip codenamed Hydra.

Sales of Apple Macs peaked in 2022; the following year was a sharp decline, and sales have continued to be flat since. The new AI PCs for Windows-based systems have been generating hype from all major vendors, hoping to introduce AI features to end users. However, Apple wants to be part of the revolution, and the company has already scheduled the World Wide Developer Conference for June 10th. At WWDC this year, Apple is supposed to show a suite of AI-powered solutions to enable better user experience and increase productivity. With M4 chips getting AI enhancement, the WWDC announcements will get extra hardware accelerations. However, we must wait for the exact announcements before making further assumptions.

According to the latest report from Bloomberg, the US government under Joe Biden's administration has announced plans to provide Taiwan Semiconductor Manufacturing Company (TSMC) with a substantial financial support package worth $11.6 billion. The package is composed of $6.6 billion in grants and up to $5 billion in loans. This represents the most significant financial assistance approved under the CHIPS and Science Act, a key initiative to resurrect the US chip industry. The funding will aid TSMC in establishing three cutting-edge semiconductor production facilities in Arizona, with the company's total investment in the state expected to exceed an impressive $65 billion. TSMC's multi-phase Arizona project will commence with the construction of a fab module near its existing Fab 21 facility. Production using 4 nm and 5 nm process nodes is slated to begin by early 2025. The second phase, scheduled for 2028, will focus on even more advanced 2 nm and 3 nm technologies.

TSMC has kept details about the third facility's production timeline and process node under wraps. The company's massive investment in Arizona is expected to profoundly impact the local economy, creating 6,000 high-tech manufacturing jobs and over 20,000 construction positions. Moreover, $50 million has been earmarked for training local workers, which aligns with President Joe Biden's goal of bolstering domestic manufacturing and technological independence. However, TSMC's Arizona projects have encountered obstacles, including labor disputes and uncertainties regarding government support, resulting in delays for the second facility's production timeline. Additionally, reports suggest that at least one TSMC supplier has abandoned plans to set up operations in Arizona due to workforce-related challenges.

Canalys' latest forecast predicts that an estimated 48 million AI-capable PCs will ship worldwide in 2024, representing 18% of total PC shipments. But this is just the start of a major market transition, with AI-capable PC shipments projected to surpass 100 million in 2025, 40% of all PC shipments. In 2028, Canalys expects vendors to ship 205 million AI-capable PCs, representing a staggering compound annual growth rate of 44% between 2024 and 2028.

These PCs, integrating dedicated AI accelerators, such as Neural Processing Units (NPUs), will unlock new capabilities for productivity, personalization and power efficiency, disrupting the PC market and delivering significant value gains to vendors and their partners.

Lee Kang-Wook, Vice President of Research and Development at SK Hynix, has discussed the increased importance of advanced chip packaging with Bloomberg News. In an interview with the media company's business section, Lee referred to a tradition of prioritizing the design and fabrication of chips: "the first 50 years of the semiconductor industry has been about the front-end." He believes that the latter half of production processes will take precedence in the future: "...but the next 50 years is going to be all about the back-end." He outlined a "more than $1 billion" investment into South Korean facilities—his department is hoping to "improve the final steps" of chip manufacturing.

SK Hynix's Head of Packaging Development pioneered a novel method of packaging the third generation of high bandwidth technology (HBM2E)—that innovation secured NVIDIA as a high-profile and long term customer. Demand for Team Green's AI GPUs has boosted the significance of HBM technologies—Micron and Samsung are attempting to play catch up with new designs. South Korea's leading memory supplier is hoping to stay ahead in the next-gen HBM contest—supposedly 12-layer fifth generation samples have been submitted to NVIDIA for approval. SK Hynix's Vice President recently revealed that HBM production volumes for 2024 have sold out—currently company leadership is considering the next steps for market dominance in 2025. The majority of the firm's newly announced $1 billion budget will be spent on the advancement of MR-MUF and TSV technologies, according to their R&D chief.