Intel today unveiled its first clean-slate CPU core micro-architecture since "Nehalem," codenamed "Sunny Cove." Over the past decade, the 9-odd generations of Core processors were based on incrementally refined descendants of "Nehalem," running all the way down to "Coffee Lake." Intel now wants a clean-slate core design, much like AMD "Zen" is a clean-slate compared to "Stars" or to a large extent even "Bulldozer." This allows Intel to introduce significant gains in IPC (single-thread performance) over the current generation. Intel's IPC growth curve over the past three micro-architectures has remained flat, and only grew single-digit percentages over the generations prior.

It's important to note here, that "Sunny Cove" is the codename for the core design. Intel's earlier codenaming was all-encompassing, covering not just cores, but also uncore, and entire dies. It's up to Intel's future chip-designers to design dies with many of these cores, a future-generation iGPU such as Gen11, and a next-generation uncore that probably integrates PCIe gen 4.0 and DDR5 memory. Intel details "Sunny Cove" as far as mentioning IPC gains, a new ISA (new instruction sets and hardware capabilities, including AVX-512), and improved scalability (ability to increase core-counts without running into latency problems).

SK Hynix announced that it has developed 16 Gb DDR5 DRAM, the industry's first DDR5 to meet the JEDEC standards. The same 1Ynm process technology used for the recently-developed 1Ynm 8Gb DDR4 DRAM was applied to the new DRAM, giving an industry-leading competitive edge for the Company.

DDR5 is a next-generation DRAM standard that offers ultra-high speed and high density with reduced power consumption as compared to DDR4, for use in data-intensive applications such as big data, artificial intelligence, and machine learning.

DDR5 will be the next step in DDR5 memory tech, again bringing increased transfer speeds over the previous JEDEC (the standards body responsible for the DDR specifications) specification. The new memory technology will also bring the customary reductions in operating voltage - the new version will push the 64-bit link down to 1.1V and burst lengths to 16 bits from 1.2V and 8 bits. In addition, DDR5 lets voltage regulators ride on the memory card rather than the motherboard. CPU vendors are also expected to expand the number of DDR channels on their processors from 12 to 16, which could drive main memory sizes to 128 GB from 64 GB today.

DDR5 is being developed with particular attention to the professional environment, where ever-increasingly gargantuan amounts of addressable memory are required. One of the guiding principles over DDR5's development is a density increase (to allow 16 Gbit chips) that would allow for larger volumes of memory (and thus data processing) in the environments that need that. Reduced power consumption also plays a role here, but all of this will have a cost: latency. For end-users, though, this increased latency will be offset by the usual suspects (DDR memory companies such as Crucial, Corsair, just to name some started with the letter C) in tighter timings and increased operating frequencies. JEDEC's specification for DDR5 is set at 4800 MT/s, but it's expected the memory tech will scale to 6400 MT/s, and you know overclocking and performance-focused companies will walk all over the standard.

Samsung Electronics, the world leader in advanced memory technology, today announced that it has successfully developed the industry's first 10-nanometer (nm) class* 8-gigabit (Gb) LPDDR5 DRAM. Since bringing the first 8Gb LPDDR4 to mass production in 2014, Samsung has been setting the stage to transition to the LPDDR5 standard for use in upcoming 5G and Artificial Intelligence (AI)-powered mobile applications.

The newly-developed 8Gb LPDDR5 is the latest addition to Samsung's premium DRAM lineup, which includes 10nm-class 16Gb GDDR6 DRAM (in volume production since December 2017) and 16Gb DDR5 DRAM (developed in February).

Cadence and Micron have joined forces to build the world's first working DDR5-4400 memory module. Cadence provided their DDR5 memory controller and PHY for the prototype while Micron produced the 8 Gb chips, which were manufactured under TSMC's 7 nm process. They were able to achieve 4400 megatransfers per second, which is roughly 37.5% faster than the fastest DDR4 memory that is currently on the market. Nevertheless, Marc Greenberg from Cadence emphasized that DDR5 aims to provide increased capacity solutions, more than actual performance.

The DDR5 standard should facilitate the production of 16 Gb dies and make vertical stacking easier. Restricted by laws of physics, dies eventually get slower as they increased in size. Once you start putting 16Gb die in 1X memory technology, the distances between them starts to get longer. As a result, core timing parameters become worse. Cadence's prototype had a CAS latency of 42 (No, not a typo). Although, the test module does run at 1.1 volts, which makes it quite impressive when compared to DDR4.

The DDR PHY Interface (DFI) Group today released version 5.0 of the specification for interfaces between high-speed memory controllers and physical (PHY) interfaces to support the requirements of future mobile and server memory standards. The DFI specifications, widely adopted throughout the memory industry, enable greater interoperability.

The DFI Group included several interface improvements in this newest specification. The new version of the specification adds protocol support for the newest DDR and low-power memory technologies. Previous versions of the specification defined memory training across the interface between the memory controller and the PHY. The new specification completely transitions to PHY-independent training mode where the PHY trains the memory interface without involving the controller. Other interface improvements include lower power enhancements, providing a PHY-independent boot sequence, expanding frequency change support, and defining new controller-to-PHY interface interactions.

"The industry is beginning to embrace new low-power and DDR memory technologies, including high-performance devices such as servers, storage, and networking; autonomous vehicles; and low-power handheld devices and IoT," stated John MacLaren, DFI Group chairman and Cadence design engineering architect. "The DFI Group, consisting of experts from leading companies in the industry, is enthusiastic to contribute to enabling this transition with the latest release of the DFI specification. Beyond supporting the latest DDR and LPDDR memory technologies, we have introduced significant improvements to the interface to improve low power, interoperability, and interface interactions."

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced today that it has begun mass producing the industry's first 2nd-generation of 10-nanometer class (1y-nm), 8-gigabit (Gb) DDR4 DRAM. For use in a wide range of next-generation computing systems, the new 8 Gb DDR4 features the highest performance and energy efficiency for an 8 Gb DRAM chip, as well as the smallest dimensions.

"By developing innovative technologies in DRAM circuit design and process, we have broken through what has been a major barrier for DRAM scalability," said Gyoyoung Jin, president of Memory Business at Samsung Electronics. "Through a rapid ramp-up of the 2nd-generation 10 nm-class DRAM, we will expand our overall 10 nm-class DRAM production more aggressively, in order to accommodate strong market demand and continue to strengthen our business competitiveness."

Rambus, a company that has veered around the line of being an innovative company and a patent troll, has shed some more light on what can be expected from HBM3 memory (when it's finally available). In an investor meeting, representatives from the company shared details regarding HBM3's improvements over HBM2. Details are still scarce, but at least we know Rambus' expectations for the technology: double the memory bandwidth per stack when compared to HBM2 (4000 MB/s), and a more complex design, which leaves behind the 2.5D design due to increased height of the HBM3 memory stacks. An interesting thing to note is that Rambus is counting on HBM3 to be produced on 7 nm technologies. Considering the overall semiconductor manufacturing calendar for the 7 nm process, this should place HBM3 production in 2019, at the earliest.

HBM3 is also expected to bring much lower power consumption compared to HBM2, besides increasing memory density and bandwidth. However, the "complex design architectures" in the Rambus slides should give readers pause. HBM2 production has had some apparent troubles in reaching demand levels, with suspected lower yields than expected being the most likely culprit. Knowing the trouble AMD has had in successful packaging of HBM2 memory with the silicon interposer and its own GPUs, an even more complex implementation of HBM memory in HBM3 could likely signal some more troubles in that area - maybe not just for AMD, but for any other takers of the technology. Here's hoping AMD's woes were due only to one-off snags on their packaging partners' side, and doesn't spell trouble for HBM's implementation itself.

DDR5, the natural successor to today's DDR4 memory that brings with double the bandwidth and density versus current generation DDR4. along with delivering improved channel efficiency, is expected to be available in the market starting 2019. JEDEC, the standards body responsible for the DDR specifications, says that base DDR5 frequencies should be at around DDR5-4800 - more than double that of base DDR4's 2133, but a stone throw away from today's fastest (and uber, kidney-like-expensive) 4600 MHz memory kits from the likes of G.Skill and Corsair.

DDR5 is expected to support data rates up to 6.4 Gb/s delivering 51.2 GB/s max, up from 3.2 Gb/s and 25.6 GB/s for today's DDR4. The new version will push the 64-bit link down to 1.1V and burst lengths to 16 bits from 1.2V and 8 bits. In addition, DDR5 lets voltage regulators ride on the memory card rather than the motherboard. CPU vendors are also expected to expand the number of DDR channels on their processors from 12 to 16, which could drive main memory sizes to 128 GB from 64 GB today. Whether this will be good for end-users in relation to DDR5 memory prices remains open for debate; however, considering the rampant memory prices this side of 2017, chances are it won't be unless supply increases considerably.

XFX has launched three variants of the RX 550 graphics cards, the tiny GPU that could, which AMD launched so as to bridge the enormous gap between IGP and its previous entry-line RX 460 (now RX 560) series of graphics cards. There are two low-profile versions of the RX 550, packing either 2GB or 4 GB of memory (whose amounts can be justified or not,) both with boost clocks set at 1203 MHz and 7000 MHz GDDR5 memory over a 128-bit bus. There is also a full-profile, dual slot RX 550, dubbed the Core Edition, and another Core Edition, though this one is a full-profile, single-slot solution.

All of these pack the same 1203 MHz boost clocks, so XFX is basically telling you to pick and choose the size of the graphics cards that best fits your use case, with improvements on cooling and sound profile that come with the larger, beefier cooling solutions. Display outputs stand the same among all the different cards, with 1x DVI-I Dual-Link, 1x DisplayPort, and 1x HDMI 2.0.

JEDEC Solid State Technology Association, responsible for creating the standards on which all of your versions of DDR memory are based upon, recently announced that development of the DDR5 memory standard is well underway, and in time for a 2018 release. The standards body said DDR5 memory will provide double the bandwidth and density versus current generation DDR4. along with delivering improved channel efficiency. Though considering the rate at which DDR4 prices have been increasing as of late, we really should fell a little uneasy at what this new memory standard's adoption will entail.

The current highest base clock that JEDEC allows in their DDR4 memory standard before "overclocking" takes over is DDR4-2400 - with timings ranging from 15~18 for the CAS latency, as well as tRCD, and tRP. And if, as JEDEC says, DDR5 is to be "twice as fast", that could imply that we could end up seeing DDR5-4800. Consider that for a moment: DDR4 kits today only go so far as DDR4-4266, and those are so few and far between that they'll cost you a singular kidney.