SiPearl has this week announced their collaboration with Open-Silicon Research, the India-based entity of OpenFive, to produce the next-generation SoC designed for HPC purposes. SiPearl is a part of the European Processor Initiative (EPI) team and is responsible for designing the SoC itself that is supposed to be a base for the European exascale supercomputer. In the partnership with Open-Silicon Research, SiPearl expects to get a service that will integrate all the IP blocks and help with the tape out of the chip once it is done. There is a deadline set for the year 2023, however, both companies expect the chip to get shipped by Q4 of 2022.

When it comes to details of the SoC, it is called Rhea and it will be a 72-core Arm ISA based processor with Neoverse Zeus cores interconnected by a mesh. There are going to be 68 mesh network L3 cache slices in between all of the cores. All of that will be manufactured using TSMC's 6 nm extreme ultraviolet lithography (EUV) technology for silicon manufacturing. The Rhea SoC design will utilize 2.5D packaging with many IP blocks stitched together and HBM2E memory present on the die. It is unknown exactly what configuration of HBM2E is going to be present. The system will also see support for DDR5 memory and thus enable two-level system memory by combining HBM and DDR. We are excited to see how the final product looks like and now we wait for more updates on the project.

Intel "Alder Lake" is the first processor generation coming from the company to feature the hybrid big.LITTLE type core arrangement and we are wondering how the configurations look like and just how powerful the next-generation processors are going to be. Today, a Geekbench submission has appeared that gave us a little more information about one out of twelve Alder Lake-S configurations. This time, we are getting an 8-core, 16-threaded design with all big cores and no smaller cores present. Such design with no little cores in place is exclusive to the Alder Lake-S desktop platform, and will not come to the Alder Lake-P processors designed for mobile platforms.

Based on the socket LGA1700, the processor was spotted running all of its eight cores at 2.99 GHz frequency. Please note that this is only an engineering sample and the clock speeds of the final product should be higher. It was paired with the latest DDR5 memory and NVIDIA GeForce RTX 2080 GPU. The OpenCL score this CPU ran has shown that it has provided the GPU with more than enough performance. Typically, the RTX 2080 GPU scores about 106101 points in Geekbench OpenCL tests. Paired with the Alder Lake-S CPU, the GPU has managed to score as much as 108068 points, showing the power of the new generation of cores. While there is still a lot of mystery surrounding the Alder Lake-S series, we have come to know that the big cores used are supposed to be very powerful.

Driven by such factors as the continued development of autonomous driving technologies and the build-out of 5G infrastructure, the demand for automotive memories will undergo a rapid growth going forward, according to TrendForce's latest investigations. Take Tesla, which is the automotive industry leader in the application of autonomous vehicle technologies, as an example. Tesla has adopted GDDR5 DRAM products from the Model S and X onward because it has also adopted Nvidia's solutions for CPU and GPU. The GDDR5 series had the highest bandwidth at the time to complement these processors. The DRAM content has therefore reached at least 8 GB for vehicles across all model series under Tesla. The Model 3 is further equipped with 14 GB of DRAM, and the next-generation of Tesla vehicles will have 20 GB. If content per box is used as a reference for comparison, then Tesla far surpasses manufacturers of PCs and smartphones in DRAM consumption. TrendForce forecasts that the average DRAM content of cars will continue to grow in the next three years, with a CAGR of more than 30% for the period.

In the name of Odin, Chinese manufacturer Asgard has launched their first DDR5 memory modules to market - beating some competing western companies that are still "gearing up" for it. Owned by the much less interestingly-named Shenzhen Jiahe Jinwei Electronic Technology Co., Ltd., Asgard likewise lost some of its flair in naming these DDR5 sticks - the best they could do was VMA5AUK-MMH224W3. The modules will be available in 32 GB, 64 GB and 128 GB per-stick densities.

The initial modules don't have any flair - they're built with the same green PCB that's actually the forerunner of today's colored ones. The company hs also announced that the modules win run at a relatively mild 4,800 MHz (the DDR5 specification goes up to 8,400 MHz), and that its timings coincide with JEDEC's "B" classification, which should mean 40-40-40. The voltage likewise remains at the JEDEC-set standard of 1.1 V. The company announced that mass-production rollout will only occur after there are actual CPUs and platforms that can take advantage of the DDR5 memory spec, and said that they expect Intel's Alder-Lake, Sapphire Rapids and Tiger Lake-U from the blue team, as well as Van Gogh and Rembrandt APUs from the AMD camp. No word on consumer pricing was available at time of writing.

In the latest round of rumors, we have today received some really interesting news regarding Intel's upcoming lineup of desktop processors. Thanks to HKEPC media, we have information about the launch date of Intel's Rocket Lake-S processor lineup and Alder Lake-S details. Starting with Rocket Lake, Intel did not unveil the exact availability date on these processors. However, thanks to HKEPC, we have information that Rocket Lake is landing in our hands on March 15th. With 500 series chipsets already launched, consumers are now waiting for the processors to arrive as well, so they can pair their new PCIe 4.0 NVMe SSDs with the latest processor generation.

When it comes to the next generation Alder Lake-S design, Intel is reported to use its enhanced 10 nm SuperFin process for the manufacturing of these processors. This would mean that the node is more efficient than the regular 10 nm SuperFin present on Tiger Lake processors, and some improvements like better frequencies are expected. Alder Lake is expected to make use of big.LITTLE core configuration, with small cores being Gracemont designs, and the big cores being Golden Cove designs. The magic of Golden Cove is expected to result in 20% IPC improvement over Willow Cove, which exists today in Tiger Lake designs. Paired with PCIe 5.0 and DDR5 technology, Alder Lake is looking like a compelling upgrade that is arriving in December of this year. Pictured below is the LGA1700 engineering sample of Alder Lake-S processor.

Here are some of the first pictures of the humongous Intel Xeon "Sapphire Rapids-SP" processor, in the flesh. Pictured by YuuKi-AnS on Chinese micro-blogging site bilibili, the engineering sample looks visibly larger than an AMD EPYC. Bound for 2021, this processor will leverage the latest generation of Intel's 10 nm Enhanced SuperFin silicon fabrication node, the latest I/O that include 8-channel DDR5 memory, a large number of PCI-Express gen 5.0 lanes, and ComputeXpress Link (CXL) interconnect. Perhaps the most interesting bit of information from the YuuKi-AnS has to be the mention of an on-package high-bandwidth memory solution. The processors will introduce an IPC uplift over "Ice Lake-SP" processors, as they use the newer "Willow Cove" CPU cores.

Yes, you are reading that title correctly. Today we got ahold of information that DDR3 prices are going to skyrocket by as much as 40-50% this year! Despite DDR4 being present for seven years (since 2014), which is a lot in the world of tech, DDR3 is still thriving. Used in a wide range of devices like IoT, older servers, and long time running machines that need maintenance for decades. The DDR3 has been manufactured by SK Hynix, Samsung, and Micron, however, as technology moved on, these companies began the migration to the newer DDR4 standard. Even DDR5 exists today and it is currently manufactured.

So why is DDR3 soaring in value? It is because of the increased scarcity of this memory. SK Hynix has stopped the production of 2 Gb modules, leaving only the 4 Gb modules in production. Samsung has cut down the capacity from 60,000 wafers of DDR3 memory modules per month to just 20,000. This has caused the price of 2 Gb and 4 Gb modules to rise already as much as 30%. Despite the age of 14 years, DDR3 is still widely used in many systems. And because of that, the scarcity is making the price of the current memory increase. The price is expected to rise through the whole year and it could reach a 50% increase.

Micron Technology, Inc., today announced volume shipment of 1α (1-alpha) node DRAM products built using the world's most advanced DRAM process technology and offering major improvements in bit density, power and performance. This milestone reinforces Micron's competitive strength and complements its recent breakthroughs with the world's fastest graphics memory and the first-to-ship 176-layer NAND.

"This 1α node achievement confirms Micron's excellence in DRAM and is a direct result of Micron's relentless commitment to cutting-edge design and technology," said Scott DeBoer, executive vice president of technology and products at Micron. "With a 40% improvement in memory density over our previous 1z DRAM node, this advancement will create a solid foundation for future product and memory innovation."

Micron plans to integrate the 1α node across its DRAM product portfolio this year to support all environments that use DRAM today. The applications for this new DRAM technology are extensive and far reaching—enhancing performance in everything from mobile devices to smart vehicles.

Leading global memory brand TEAMGROUP continues to make its mark on the next generation of DDR5 memory. At the end of last year, the company announced that it had entered the validation phase with the collaboration of major motherboard manufacturers. In early 2021, it has made another breakthrough. Paying attention to the needs of not only desktop but also notebook and mini PC users, TEAMGROUP has successfully created DDR5 SO-DIMM and is expected to be the first to take Intel and AMD's new platform validation tests.

Specifications of the DDR5 SO-DIMM at the early stage of development resemble those of the U-DIMM version. A single module has a capacity of 16 GB and a frequency of 4800 MHz, and both versions run at the lowered voltage of 1.1 V. For notebooks that need to stay mobile for a long period of time, this can noticeably reduce power consumption and extend standby time. DDR5 SO-DIMM also supports on-die ECC, a feature that self-corrects single-bit errors, greatly improving system stability. Users can look forward to the convenience and peace of mind that DDR5 will bring to notebooks, mini PCs, NAS, and more.

Intel has just launched its Rocket Lake-S desktop lineup of processors during this year's CES 2021 virtual event. However, the company is under constant pressure from the competition and it seems like it will not stop with that launch for this year. Today, thanks to the popular leaker @momomo_us on Twitter, we have the first SiSoftware entries made from the anonymous Alder Lake-S system. Dubbed a heterogeneous architecture, Alder Lake is supposed to be Intel's first desktop attempt at making big.LITTLE style of processors for general consumers. It is supposed to feature Intel 10 nm Golden Cove CPU "big" cores & Gracemont "small" CPU cores.

The SiSoftware database entry showcases a prototype system that has 16 cores and 32 threads running at the base frequency of 1.8 GHz and a boost speed of 4 GHz. There is 12.5 MB of L2 cache (split into 10 pairs of 1.25 MB) and 30 MB of level-three (L3) cache present on the processor. There is also an Alder Lake-S mobile graphics controller that runs at 1.5 GHz. Intel Xe gen 12.2 graphics is responsible for the video output. When it comes to memory, Alder Lake-S is finally bringing the newest DDR5 standard with a new motherboard chipset and socket called LGA 1700.

AMD is always in development mode and just when they launch a new product, the company is always gearing up for the next-generation of devices. Just a few months ago, back in November, AMD has launched its Zen 3 core, and today we get to hear about the next steps that the company is taking to stay competitive and grow its product portfolio. In the AnandTech interview with Dr. Lisa Su, and The Street interview with Rick Bergman, the EVP of AMD's Computing and Graphics Business Group, we have gathered information about AMD's plans for Zen 4 core development and RDNA 3 performance target.

Starting with Zen 4, AMD plans to migrate to the AM5 platform, bringing the new DDR5 and USB 4.0 protocols. The current aim of Zen 4 is to be extremely competitive among competing products and to bring many IPC improvements. Just like Zen 3 used many small advances in cache structures, branch prediction, and pipelines, Zen 4 is aiming to achieve a similar thing with its debut. The state of x86 architecture offers little room for improvement, however, when the advancement is done in many places it adds up quite well, as we could see with 19% IPC improvement of Zen 3 over the previous generation Zen 2 core. As the new core will use TSMC's advanced 5 nm process, there is a possibility to have even more cores found inside CCX/CCD complexes. We are expecting to see Zen 4 sometime close to the end of 2021.

ADATA Technology, a manufacturer of high-performance DRAM modules, NAND Flash products, mobile accessories, gaming products, electric power trains, and industrial solutions, is gearing up to bring next-generation DDR5 memory modules to market to offers users a significant upgrade in speed, capacity, as well as increased bandwidth per CPU cores. ADATA has been working closely with two leading motherboard makers, MSI and Gigabyte, to ensure an optimized experience through ensuring synergies between ADATA's DDR5 modules and their latest Intel platforms.

In parallel to developing the new memory modules, ADATA has also been working closely with two leading motherboard makers MSI and Gigabyte, its long-term strategic partners, to ensure their new platforms can take full advantage of DDR5. Among other initiatives, ADATA, MSI, and Gigabyte have been conducting joint testing and research to guarantee optimum DDR5 overclocking on the latest Intel platforms to meet gamers' discerning standards. ADATA and the motherboard above makers will be launching DDR5 modules and DDR5-compliant motherboards simultaneously to offer high performance to a wide range of users, including enterprises, gamers, and creators, to name a few.

Intel has just released its "Architecture Instruction Set Extensions and Future Features Programming Reference" manual, which serves the purpose of providing the developers' information about Intel's upcoming hardware additions which developers can utilize later on. Today, thanks to the @InstLatX64 on Twitter we have information that Intel is bringing on-package High Bandwidth Memory (HBM) solution to its next-generation Sapphire Rapids Xeon processors. Specifically, there are two instructions mentioned: 0220H - HBM command/address parity error and 0221H - HBM data parity error. Both instructions are there to address data errors in HBM so the CPU operates with correct data.

The addition of HBM is just one of the many new technologies Sapphire Rapids brings. The platform is supposedly going to bring many new technologies like an eight-channel DDR5 memory controller enriched with Intel's Data Streaming Accelerator (DSA). To connect to all of the external accelerators, the platform uses PCIe 5.0 protocol paired with CXL 1.1 standard to enable cache coherency in the system. And as a reminder, this would not be the first time we see a server CPU use HBM. Fujitsu has developed an A64FX processor with 48 cores and HBM memory, and it is powering today's most powerful supercomputer - Fugaku. That is showing how much can a processor get improved by adding a faster memory on-board. We are waiting to see how Intel manages to play it out and what we end up seeing on the market when Sapphire Rapids is delivered.

Intel needs a platform refresh to battle the competition, mainly speaking to battle AMD and its Ryzen 5000 series processors. That is why the company is developing 500 series of chipsets covering the low-end (H510), mid-range (B560), and high-end markets (Z590) that pair with the upcoming Rocket Lake-S processor generation. Dubbed 11th generation of Core processors, the 11th generation of Intel Core CPUs are going to be built on Intel's refined 14 nm process. The CPUs are supposed to feature a Cypress Cove core, which is a backport of Golden Cove found in Ice Lake. The 500 series motherboards are the last in the DDR4 generation, launching in the timeframe when DDR5 is supposed to take over in the coming years.

Today, thanks to Weixin, a Chinese media outlet that posted a short story on the WeChat platform, we have information about the launch date of these new chipsets. According to the source, we are allegedly going to see these new chipsets on January 11th, the day that Intel CES 2021 event is supposed to happen. The platform will include a range of motherboards from Intel's partners and is supposed to bring support for the much-needed PCIe 4.0 protocol. The launch date should be taken with a grain of salt, of course, before taking it as a fact.

Team Group, a global leader in computer memory, has rapidly responded to market demand changes during the crucial transition period of next-generation DRAM technology. By integrating the newest technologies to promote its development of DDR5 memory, it has outpaced competitions and developed the first engineering sample of consumer-grade DDR5 memory. With this success, it will welcome the new DDR5 generation with consumers worldwide.

Presently, Team Group is working hard at producing its first batch of DDR5 memory with the tentative specifications of 16 GB, 4800 MHz, and 1.1 V for a single module. The company is cooperating with major motherboard manufacturers, such as ASUS, MSI, ASRock, and GIGABYTE, providing memory and working together with their R&D divisions to perform validation tests. Through the collaboration of R&D teams, Team Group was able to accelerate the development of its DDR5 memory by adjusting the initial parameters. The successful completion of the validation phase will confirm that the frequencies of standard DDR5 products surpass those of overclocked DDR4 products, and will represent another big step forward in the evolution of computer memory.

Today, thanks to the ServeTheHome forum member "111alan", we have the first pictures of the alleged Intel Sapphire Rapids Xeon processor. Pictured is what appears to be a dual-die design similar to Cascade Lake-SP design with 56 cores and 112 threads that uses two dies. The Sapphire Rapids is a 10 nm SuperFin design that allegedly comes even in the dual-die configuration. To host this processor, the motherboard needs an LGA4677 socket with 4677 pins present. The new LGA socket, along with the new 10 nm Sapphire Rapids Xeon processors are set for delivery in 2021 when Intel is expected to launch its new processors and their respective platforms.

The processor pictured is clearly a dual-die design, meaning that Intel used some of its Multi-Chip Package (MCM) technology that uses EMIB to interconnect the silicon using an active interposer. As a reminder, the new 10 nm Sapphire Rapids platform is supposed to bring many new features like a DDR5 memory controller paired with Intel's Data Streaming Accelerator (DSA); a brand new PCIe 5.0 standard protocol with a 32 GT/s data transfer rate, and a CXL 1.1 support for next-generation accelerators. The exact configuration of this processor is unknown, however, it is an engineering sample with a clock frequency of a modest 2.0 GHz.

As a world leader in computer memory, TEAMGROUP understands the importance of getting ahead in the next generation of DDR technology, hence it will be releasing ELITE series DDR5 memory in 2021. With over 20 years of experience developing DDR3 and DDR4 products, the company has dazzled the world with its advanced R&D capabilities and excellent product quality. After the JEDEC announced the DDR5 memory standard, TEAMGROUP has been actively designing and working together with our IC manufacturing partners to pioneer and prepare for this new generation.

TEAMGROUP is leading the way with its first DDR5 memory under its global top-selling ELITE memory product line. It plans to release a 16 GB 4800 MHz module operating at 1.1 V, down from the 1.2 V of the previous generation. The data transfer rate is increased to 4,800-5,200 Mbps, an increase of up to 1.6 times while reducing power consumption by 10%. Today's DDR4 memory with error correction code (ECC) requires an additional chip installed on the PCB, whereas DDR5 supports on-die ECC, a feature that self-corrects single-bit errors, greatly improving system stability. Anticipation is high for the efficiency improvements brought by the new generation, which can be utilized for big data and AI computing and other related applications.

Intel has just recently announced its next-generation Rocket Lake-S processor specifications designed to bring improved performance and newer platform technologies like PCIe 4.0. However, we are yet to see the first 10 nm CPU for desktop users. Today, thanks to the sources over at VideoCardz, we have the first look at Intel's next-next-generation processor called Alder Lake. The Alder Lake-S is a platform that brings many of the "firsts" for Intel. It will be the first architecture being built on the company's 10 nm SuperFin architecture. Alongside the new node, the platform will transition to the next-generation of technologies. Rumored are the transitions to PCIe 5.0 and perhaps, most importantly - DDR5.

Another new approach will be Intel's adaptation of Arm's big.LITTLE heterogeneous core structure. The processor will feature a few of the "little" cores for light tasks, and fire up the "big" cores for heavy computing. All of that will require a new socket to house the processor, which is the LGA1700. You can see the new processor below, compared to LGA1200 CPU from the previous generation.

SK hynix Inc. today announced financial results for its third quarter 2020 ended on September 30, 2020. The consolidated revenue of third quarter 2020 was 8.129 trillion won while the operating profit amounted to 1.3 trillion won, and the net income 1.078 trillion won. Operating margin for the quarter was 16% and net margin was 13%.

Despite the Company saw the recovery of mobile DRAM demand in the quarter, both the revenue and operating profit decreased by 6% and 33% quarter-over-quarter (QoQ) respectively, as the server DRAM and SSD demands weakened, and the overall semiconductor memory price flow turned downwards in the quarter. For DRAM, SK hynix proactively responded to rising demands of mobile and graphics DRAM, and the expansion of consumer electronics DRAM demand as well. As a result, in spite of decreased server DRAM demand, the Company's DRAM bit shipment in the quarter still increased by 4% QoQ. However, due to the unfavorable price of server DRAM and other certain DRAM products, the average selling price decreased by 7% QoQ.

SK hynix and Intel today announced that they have signed an agreement on Oct. 20, KST, under which SK hynix would acquire Intel's NAND memory and storage business for US $9 billion. The transaction includes the NAND SSD business, the NAND component and wafer business, and the Dalian NAND memory manufacturing facility in China. Intel will retain its distinct Intel Optane business.

SK hynix and Intel will endeavor to obtain required governmental approvals expected in late 2021. Following receipt of these approvals, SK hynix will acquire from Intel the NAND SSD business (including NAND SSD-associated IP and employees), as well as the Dalian facility, with the first payment of US $7 billion. SK hynix will acquire from Intel the remaining assets, including IP related to the manufacture and design of NAND flash wafers, R&D employees, and the Dalian fab workforce, upon a final closing, expected to occur in March 2025 with the remaining payment of US $2 billion. Per the agreement, Intel will continue to manufacture NAND wafers at the Dalian Memory Manufacturing Facility and retain all IP related to the manufacture and design of NAND flash wafers until the final closing.

Intel has been preparing the launch of its 10 nm processors for desktop users for some time now, and today we are getting the first pictures of the Alder Lake-S CPU backside. Featuring a package with a size of 37.5×45 mm, the Alder Lake CPU uses more of its area for a pin count increase. Going up from 1200 pins in the LGA1200 socket, the new Alder Lake-S CPU uses 1700 CPU pins, which slots in the LGA1700 socket. In the picture below, there is an engineering sample of the Alder Lake-S CPU, which we see for the first time. While there is no much information about the processor, we know that it will use Intel's 10 nm SuperFin design, paired with hybrid core technology. That means that there will be big (Golden Cove) and little (Gracemont) cores in the design. Other features such as PCIe 5.0 and DDR5 should be present as well. The new CPU generation and LGA1700 motherboards are scheduled to arrive in second half of 2021.

SK hynix Inc. announced to launch world's first DDR5 DRAM. It is a high-speed and high-density product optimized for Big Data, Artificial Intelligence (AI), and machine learning (ML) as a next generation standard of DRAM. Since SK hynix announced the development of World's First 16 Gigabit (Gb) DDR5 DRAM on November 2018, the Company has provided its major partners including Intel with sample products, and has completed various tests and verification of its functions and compatibility. This will allow SK hynix to provide its customers with the products once the DDR5 market becomes active.

In the meantime, SK hynix has conducted joint-operation of on-site lab, system-level test, and simulation with System-on-Chip) (SoC) manufacturers to verify the functions of DDR5. Also, the Company validated compatibility of its DDR5 and the major components on DRAM module including register clock driver) (RCD), which affect DRAM performance, and power management integrated circuit) (PMIC). Through these verifications, SK hynix has been collaborating closely with its global partners.

Intel today launches its 11th Gen Core "Tiger Lake" mobile processors that introduce several new technologies on the backs of new IP. As described in the Architecture Day, "Tiger Lake" is built on the 10 nm SuperFin process, and combines new "Willow Cove" CPU cores with the first commercial debut of the Xe Gen12 graphics architecture that Intel is betting big on, to make a stab at the consumer graphics and scalar compute markets. Join us in this live-blog.Update 16:00 UTC: GB (Gregory Bryant, EVP Client), leads the event from the comfort of his home.Update 16:04 UTC: Here it is, the "world's best processor for thin and light laptops. You'll notice that like most Intel U-segment chips, this is an MCM of the processor and PCH die. Intel bases its "world's best" claims on a per-segment basis.

A lot is riding for Intel on its 11th Gen Core "Tiger Lake" system-on-chip (SoC), which will launch exclusively on mobile platforms, hoping to dominate the 7 W thru 15 W ultraportable form-factors in 2020, while eventually scaling up to the 25 W thru 45 W H-segment form-factors in 2021, with a variant that is rumored to double core-counts. The chip is built on Intel's new 10 nm SuperFin silicon fabrication node that enables a double digit percentage energy efficiency growth over 10 nm, allowing Intel to significantly dial up clock speeds without impacting the power envelope. The CPU and iGPU make up the two key components of the "Tiger Lake" SoC.

The CPU component on the "Tiger Lake" processors that launch in a few weeks from now features four "Willow Cove" CPU cores. Coupled with HyperThreading, this ends up being a 4-core/8-thread setup, although much of Intel's innovation is in giving these cores significant IPC increases over the "Skylake" core powering "Comet Lake" processors, and compared to the "Sunny Cove" cores powering "Ice Lake" a minor IPC (although major net performance increase from clock speeds). The "Willow Cove" CPU core appears to be a derivative of the "Sunny Cove" core, designed to take advantage of the 10 nm SuperFin node, along with three key innovations.

SK hynix Inc. today announced financial results for its second quarter 2020 ended on June 30, 2020. The consolidated revenue of second quarter 2020 was 8.607 trillion won while the operating profit amounted to 1.947 trillion won, and the net income 1.264 trillion won. Operating margin for the quarter was 23% and net margin was 15%.

Despite uncertainties of business environment due to COVID-19, both the Company's revenue and operating income increased by 20% and 143% quarter-over-quarter (QoQ) respectively, as the surging demand for server memory maintained favorable memory price while numerous factors including the increase of the main products' yield rate led to cost reduction.