Intel has just launched its Ice Lake-SP lineup of Xeon Scalable processors, featuring the new Sunny Cove CPU core design. Built on the 10 nm node, these processors represent Intel's first 10 nm shipping product designed for enterprise. However, there is another 10 nm product going to be released for enterprise users. Intel is already preparing the Sapphire Rapids generation of Xeon processors and today we get to see more details about it. Thanks to the anonymous tip that VideoCardz received, we have a bit more details like core count, memory configurations, and connectivity options. And Sapphire Rapids is shaping up to be a very competitive platform. Do note that the slide is a bit older, however, it contains useful information.

The lineup will top at 56 cores with 112 threads, where this processor will carry a TDP of 350 Watts, notably higher than its predecessors. Perhaps one of the most interesting notes from the slide is the department of memory. The new platform will make a debut of DDR5 standard and bring higher capacities with higher speeds. Along with the new protocol, the chiplet design of Sapphire Rapids will bring HBM2E memory to CPUs, with up to 64 GBs of it per socket/processor. The PCIe 5.0 standard will also be present with 80 lanes, accompanying four Intel UPI 2.0 links. Intel is also supposed to extend the x86_64 configuration here with AMX/TMUL extensions for better INT8 and BFloat16 processing.

We have seen a number of announcements from key industry players about the introduction of DDR5 memory but today's news from Chinese company Jiahe Jinwei marks the beginning of DDR5 mass production. The company announced that DDR5 RAM from Micron had arrived at its facilities and that memory module production could begin. Jiahe Jinwei is the fourth largest memory manufacturer in China and owns memory brands such as Guangwei and Asgard which have recently announced DDR5 modules with capacities of up to 128 GB and speeds reaching 4,800 MHz. Intel is expected to launch their 12th Generation Alder Lake processors later this year with DDR5 support while AMD will introduce support with Zen 4 processors on a new AM5 socket.

TEAMGROUP has worked vigorously on the development of next-generation DDR5 memory. After completing validation tests for standard DDR5 U-DIMM and SO-DIMM products with the collaboration of major motherboard manufacturers, TEAMGROUP is announcing an exciting breakthrough today: its T-FORCE brand has successfully created DDR5 overclocking memory. Samples were immediately sent to ASUS, ASRock, MSI, and GIGABYTE for collaborative testing of its overclocking capability. Consumers can expect TEAMGROUP's products to be fully compatible with motherboards from the four major manufacturers when the DDR5 generation arrives.

The DDR5 overclocking memory has greater room for voltage adjustment, due to its upgraded power management IC. This PMIC can support high frequency overclocking with voltage over 2.6 V. In previous generations, voltage conversion was controlled by the motherboard. With DDR5, components were moved to the memory, enabling the module to handle the voltage conversion, which not only reduces voltage wear but also reduces noise generation. This allows significantly increased room for overclocking compared to the past, and more powerful computing processing.

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today announced that it has expanded its DDR5 DRAM memory portfolio with the industry's first 512 GB DDR5 module based on High-K Metal Gate (HKMG) process technology. Delivering more than twice the performance of DDR4 at up to 7,200 megabits per second (Mbps), the new DDR5 will be capable of orchestrating the most extreme compute-hungry, high-bandwidth workloads in supercomputing, artificial intelligence (AI) and machine learning (ML), as well as data analytics applications.

"Samsung is the only semiconductor company with logic and memory capabilities and the expertise to incorporate HKMG cutting-edge logic technology into memory product development," said Young-Soo Sohn, Vice President of the DRAM Memory Planning/Enabling Group at Samsung Electronics. "By bringing this type of process innovation to DRAM manufacturing, we are able to offer our customers high-performance, yet energy-efficient memory solutions to power the computers needed for medical research, financial markets, autonomous driving, smart cities and beyond."

Intel only just announced their 11th generation Rocket Lake-S desktop processors last week but we are already receiving information about the next generation Alder Lake-S platform which will finally make the jump to 10 nm. Intel slides for the upcoming family of processors have been leaked and they reveal some interesting information including a claimed 20% single-threaded performance increases from the new Golden Cove core design and 10 nm SuperFin node. The processors will feature Intel Hybrid Technology with a mix of small low-performance cores and large high-performance cores with a maximum of eight each for sixteen total cores. The processors will also include the latest connectivity with both PCIe 4.0 and PCIe 5.0 support along with DDR4 and DDR5 4800 MHz compatibility.

Intel will also be launching a new socket type called LGA1700 with a new package size which will render existing cooling solutions for LGA115X and LGA1200 sockets incompatible. The processors will also come with the launch of a new 600 Series chipset with PCIe 3.0 and PCIe 4.0 support along with the usual complement of USB, SATA, and networking. The entry-level 600-series motherboards will only support DDR4 memory at up to 3200 MHz while high-end Z690 motherboards will include DDR5 support. Intel has confirmed that they intend to launch Alder Lake later this year but it is yet to be known if they are referring to the desktop or mobile series.

Longsys Electronics launches the Longsys DDR5 memory module (ES1). The company has done so in order to keep up with the development of storage technologies, to meet expectations from industry professionals and users regarding future product technology development, and to provide more possibilities for the future of storage industry applications. Moreover, Longsys' FORESEE, a technical storage brand, and Lexar, a storage brand for high-end consumer goods, will also provide strong support in their main areas of application.

The newly-launched DDR5 involves the prototypes of two new architecture products: the 1-Rank x8, and the 2-Rank x8 standard PC Unbuffered DIMM 288PIN On-die-ECC. Compared with DDR4, DDR5 boasts significantly improved function and performance.

AMD is slowly preparing to launch its next-generation client-oriented accelerated processing unit (APU), which is AMD's way of denoting a CPU+GPU combination. The future design is codenamed after Van Gogh, showing AMD's continuous use of historic names for their products. The APU is believed to be a design similar to the one found in the SoC of the latest PlayStation 5 and Xbox Series X/S consoles. That means that there are Zen 2 cores present along with the latest RDNA 2 graphics, side by side in the same processor. Today, one of AMD's engineers posted a boot log of the quad-core Van Gogh APU engineering sample, showing some very interesting information.

The boot log contains information about the memory type used in the APU. In the logs, we see a part that says "[drm] RAM width 256bits DDR5", which means that the APU has an interface for the DDR5 memory and it is 256-bit wide, which represents a quad-channel memory configuration. Such a wide memory bus is typically used for applications that need lots of bandwidth. Given that Van Gogh uses RDNA 2 graphics, the company needs a sufficient memory bandwidth to keep the GPU from starving for data. While we don't have much more information about it, we can expect to hear greater details soon.

As the industry is preparing for a shift to the new DDR standard, companies are trying to adopt the new technology and many companies are manufacturing the latest DDR5 memory modules. One of them is Shenzhen Longsys Electronics Co. Ltd, a Chinese manufacturer of memory chips, which has today demonstrated the power of DDR5 technology. Starting with this year, client platforms are expected to make a transition to the new standard, with the data center/server platform following. Using Intel's yet unreleased Alder Lake-S client platform, Longsys has been able to test its DDR5 DIMMs running at an amazing 6400 MHz speed and the company got some very interesting results.

Longsys has demoed a DDR5 module with 32 GB capacity, CAS Latency (CL) of 40 CL, operating voltage of 1.1 V, and memory modules clocked at 6400 MHz. With this being an impressive memory module, this is not the peak of DDR5. According to JEDEC specification, DDR5 will come with up to 8400 MHz speeds and capacities that are up to 128 GB per DIMM. Longsys has run some benchmarks, using an 8-core Alder Lake CPU, in AIDA64 and Ludashi. The company then proceeded to compare these results with DDR4-3200 MHz CL22 memory, which Longsys also manufactures. And the results? In AIDA64 tests, the new DDR5 module is faster anywhere from 12-36%, with the only regression seen in latency, where DDR5 is doubling it. In synthetic Ludashi Master Lu benchmark, the new DDR5 was spotted running 112% faster. Of course, these benchmarks, which you can check out here, are provided by the manufacturer, so you must take them with a grain of salt.

Micron Technology, Inc. today announced that it has begun sampling the industry's first automotive low-power DDR5 DRAM (LPDDR5) memory that is hardware-evaluated to meet the most stringent Automotive Safety Integrity Level (ASIL), ASIL D. The solution is part of Micron's new portfolio of memory and storage products targeted for automotive functional safety based on the International Organization for Standardization (ISO) 26262 standard.

Micron's functional safety-evaluated DRAM is compatible with advanced-driver assistance system (ADAS) technologies, including adaptive cruise control, automatic emergency braking systems, lane departure warning and blind spot detection systems. Micron's LPDDR5's high performance, superior power efficiency and low latency provide the requisite performance and headroom to keep pace with increasing bandwidth requirements of next-generation automotive systems.

"Autonomous vehicles promise to make our roads safer, but they need powerful, trusted memory that can enable real-time decision-making in extreme environments," said Kris Baxter, corporate vice president and general manager of Micron's Embedded Business Unit. "To fulfill this growing market need, we've optimized our automotive LPDDR5 to deliver the utmost performance, quality and reliability for the smart, safe cars of tomorrow."

AMD's next-generation EPYC enterprise processor that succeeds the upcoming 3rd Gen EYPIC "Milan," codenamed "Genoa," is expected to be the first major platform update for AMD's enterprise platforms since the 2017 debut of the "Zen" based "Naples." Implementing the latest I/O interfaces, such as DDR5 memory and PCI-Express gen 5.0, the chip will also increase CPU core counts by 50% over "Milan," according to ExecutableFix on Twitter, a reliable source with rumors from the semiconductor industry. To enable the goals of new I/O and increased core counts, AMD will transition to a new CPU socket type, the SP5. This is a 6,096-pin land grid array (LGA), and the "Genoa" MCM package on SP5 is imagined to be visibly larger than SP3-generation packages.

With the added fiberglass substrate real-estate, AMD is expected to add more CPU chiplets to the package, and ExecutableFix expects the chiplet count to be increased to 12. AMD is expected to debut the "Zen 4" microarchitecture in the enterprise space with "Genoa," with the CPU chiplets expected to be built on the 5 nm EUV silicon fabrication node. Assuming the chiplets still only pack 8 cores a piece, "Genoa" could cram up to 96 cores per socket, or up to 192 logical processors, with SMT enabled.

SiPearl has this week announced their collaboration with Open-Silicon Research, the India-based entity of OpenFive, to produce the next-generation SoC designed for HPC purposes. SiPearl is a part of the European Processor Initiative (EPI) team and is responsible for designing the SoC itself that is supposed to be a base for the European exascale supercomputer. In the partnership with Open-Silicon Research, SiPearl expects to get a service that will integrate all the IP blocks and help with the tape out of the chip once it is done. There is a deadline set for the year 2023, however, both companies expect the chip to get shipped by Q4 of 2022.

When it comes to details of the SoC, it is called Rhea and it will be a 72-core Arm ISA based processor with Neoverse Zeus cores interconnected by a mesh. There are going to be 68 mesh network L3 cache slices in between all of the cores. All of that will be manufactured using TSMC's 6 nm extreme ultraviolet lithography (EUV) technology for silicon manufacturing. The Rhea SoC design will utilize 2.5D packaging with many IP blocks stitched together and HBM2E memory present on the die. It is unknown exactly what configuration of HBM2E is going to be present. The system will also see support for DDR5 memory and thus enable two-level system memory by combining HBM and DDR. We are excited to see how the final product looks like and now we wait for more updates on the project.

Intel "Alder Lake" is the first processor generation coming from the company to feature the hybrid big.LITTLE type core arrangement and we are wondering how the configurations look like and just how powerful the next-generation processors are going to be. Today, a Geekbench submission has appeared that gave us a little more information about one out of twelve Alder Lake-S configurations. This time, we are getting an 8-core, 16-threaded design with all big cores and no smaller cores present. Such design with no little cores in place is exclusive to the Alder Lake-S desktop platform, and will not come to the Alder Lake-P processors designed for mobile platforms.

Based on the socket LGA1700, the processor was spotted running all of its eight cores at 2.99 GHz frequency. Please note that this is only an engineering sample and the clock speeds of the final product should be higher. It was paired with the latest DDR5 memory and NVIDIA GeForce RTX 2080 GPU. The OpenCL score this CPU ran has shown that it has provided the GPU with more than enough performance. Typically, the RTX 2080 GPU scores about 106101 points in Geekbench OpenCL tests. Paired with the Alder Lake-S CPU, the GPU has managed to score as much as 108068 points, showing the power of the new generation of cores. While there is still a lot of mystery surrounding the Alder Lake-S series, we have come to know that the big cores used are supposed to be very powerful.

Driven by such factors as the continued development of autonomous driving technologies and the build-out of 5G infrastructure, the demand for automotive memories will undergo a rapid growth going forward, according to TrendForce's latest investigations. Take Tesla, which is the automotive industry leader in the application of autonomous vehicle technologies, as an example. Tesla has adopted GDDR5 DRAM products from the Model S and X onward because it has also adopted Nvidia's solutions for CPU and GPU. The GDDR5 series had the highest bandwidth at the time to complement these processors. The DRAM content has therefore reached at least 8 GB for vehicles across all model series under Tesla. The Model 3 is further equipped with 14 GB of DRAM, and the next-generation of Tesla vehicles will have 20 GB. If content per box is used as a reference for comparison, then Tesla far surpasses manufacturers of PCs and smartphones in DRAM consumption. TrendForce forecasts that the average DRAM content of cars will continue to grow in the next three years, with a CAGR of more than 30% for the period.

In the name of Odin, Chinese manufacturer Asgard has launched their first DDR5 memory modules to market - beating some competing western companies that are still "gearing up" for it. Owned by the much less interestingly-named Shenzhen Jiahe Jinwei Electronic Technology Co., Ltd., Asgard likewise lost some of its flair in naming these DDR5 sticks - the best they could do was VMA5AUK-MMH224W3. The modules will be available in 32 GB, 64 GB and 128 GB per-stick densities.

The initial modules don't have any flair - they're built with the same green PCB that's actually the forerunner of today's colored ones. The company hs also announced that the modules win run at a relatively mild 4,800 MHz (the DDR5 specification goes up to 8,400 MHz), and that its timings coincide with JEDEC's "B" classification, which should mean 40-40-40. The voltage likewise remains at the JEDEC-set standard of 1.1 V. The company announced that mass-production rollout will only occur after there are actual CPUs and platforms that can take advantage of the DDR5 memory spec, and said that they expect Intel's Alder-Lake, Sapphire Rapids and Tiger Lake-U from the blue team, as well as Van Gogh and Rembrandt APUs from the AMD camp. No word on consumer pricing was available at time of writing.

In the latest round of rumors, we have today received some really interesting news regarding Intel's upcoming lineup of desktop processors. Thanks to HKEPC media, we have information about the launch date of Intel's Rocket Lake-S processor lineup and Alder Lake-S details. Starting with Rocket Lake, Intel did not unveil the exact availability date on these processors. However, thanks to HKEPC, we have information that Rocket Lake is landing in our hands on March 15th. With 500 series chipsets already launched, consumers are now waiting for the processors to arrive as well, so they can pair their new PCIe 4.0 NVMe SSDs with the latest processor generation.

When it comes to the next generation Alder Lake-S design, Intel is reported to use its enhanced 10 nm SuperFin process for the manufacturing of these processors. This would mean that the node is more efficient than the regular 10 nm SuperFin present on Tiger Lake processors, and some improvements like better frequencies are expected. Alder Lake is expected to make use of big.LITTLE core configuration, with small cores being Gracemont designs, and the big cores being Golden Cove designs. The magic of Golden Cove is expected to result in 20% IPC improvement over Willow Cove, which exists today in Tiger Lake designs. Paired with PCIe 5.0 and DDR5 technology, Alder Lake is looking like a compelling upgrade that is arriving in December of this year. Pictured below is the LGA1700 engineering sample of Alder Lake-S processor.

Here are some of the first pictures of the humongous Intel Xeon "Sapphire Rapids-SP" processor, in the flesh. Pictured by YuuKi-AnS on Chinese micro-blogging site bilibili, the engineering sample looks visibly larger than an AMD EPYC. Bound for 2021, this processor will leverage the latest generation of Intel's 10 nm Enhanced SuperFin silicon fabrication node, the latest I/O that include 8-channel DDR5 memory, a large number of PCI-Express gen 5.0 lanes, and ComputeXpress Link (CXL) interconnect. Perhaps the most interesting bit of information from the YuuKi-AnS has to be the mention of an on-package high-bandwidth memory solution. The processors will introduce an IPC uplift over "Ice Lake-SP" processors, as they use the newer "Willow Cove" CPU cores.

Yes, you are reading that title correctly. Today we got ahold of information that DDR3 prices are going to skyrocket by as much as 40-50% this year! Despite DDR4 being present for seven years (since 2014), which is a lot in the world of tech, DDR3 is still thriving. Used in a wide range of devices like IoT, older servers, and long time running machines that need maintenance for decades. The DDR3 has been manufactured by SK Hynix, Samsung, and Micron, however, as technology moved on, these companies began the migration to the newer DDR4 standard. Even DDR5 exists today and it is currently manufactured.

So why is DDR3 soaring in value? It is because of the increased scarcity of this memory. SK Hynix has stopped the production of 2 Gb modules, leaving only the 4 Gb modules in production. Samsung has cut down the capacity from 60,000 wafers of DDR3 memory modules per month to just 20,000. This has caused the price of 2 Gb and 4 Gb modules to rise already as much as 30%. Despite the age of 14 years, DDR3 is still widely used in many systems. And because of that, the scarcity is making the price of the current memory increase. The price is expected to rise through the whole year and it could reach a 50% increase.

Micron Technology, Inc., today announced volume shipment of 1α (1-alpha) node DRAM products built using the world's most advanced DRAM process technology and offering major improvements in bit density, power and performance. This milestone reinforces Micron's competitive strength and complements its recent breakthroughs with the world's fastest graphics memory and the first-to-ship 176-layer NAND.

"This 1α node achievement confirms Micron's excellence in DRAM and is a direct result of Micron's relentless commitment to cutting-edge design and technology," said Scott DeBoer, executive vice president of technology and products at Micron. "With a 40% improvement in memory density over our previous 1z DRAM node, this advancement will create a solid foundation for future product and memory innovation."

Micron plans to integrate the 1α node across its DRAM product portfolio this year to support all environments that use DRAM today. The applications for this new DRAM technology are extensive and far reaching—enhancing performance in everything from mobile devices to smart vehicles.

Leading global memory brand TEAMGROUP continues to make its mark on the next generation of DDR5 memory. At the end of last year, the company announced that it had entered the validation phase with the collaboration of major motherboard manufacturers. In early 2021, it has made another breakthrough. Paying attention to the needs of not only desktop but also notebook and mini PC users, TEAMGROUP has successfully created DDR5 SO-DIMM and is expected to be the first to take Intel and AMD's new platform validation tests.

Specifications of the DDR5 SO-DIMM at the early stage of development resemble those of the U-DIMM version. A single module has a capacity of 16 GB and a frequency of 4800 MHz, and both versions run at the lowered voltage of 1.1 V. For notebooks that need to stay mobile for a long period of time, this can noticeably reduce power consumption and extend standby time. DDR5 SO-DIMM also supports on-die ECC, a feature that self-corrects single-bit errors, greatly improving system stability. Users can look forward to the convenience and peace of mind that DDR5 will bring to notebooks, mini PCs, NAS, and more.

Intel has just launched its Rocket Lake-S desktop lineup of processors during this year's CES 2021 virtual event. However, the company is under constant pressure from the competition and it seems like it will not stop with that launch for this year. Today, thanks to the popular leaker @momomo_us on Twitter, we have the first SiSoftware entries made from the anonymous Alder Lake-S system. Dubbed a heterogeneous architecture, Alder Lake is supposed to be Intel's first desktop attempt at making big.LITTLE style of processors for general consumers. It is supposed to feature Intel 10 nm Golden Cove CPU "big" cores & Gracemont "small" CPU cores.

The SiSoftware database entry showcases a prototype system that has 16 cores and 32 threads running at the base frequency of 1.8 GHz and a boost speed of 4 GHz. There is 12.5 MB of L2 cache (split into 10 pairs of 1.25 MB) and 30 MB of level-three (L3) cache present on the processor. There is also an Alder Lake-S mobile graphics controller that runs at 1.5 GHz. Intel Xe gen 12.2 graphics is responsible for the video output. When it comes to memory, Alder Lake-S is finally bringing the newest DDR5 standard with a new motherboard chipset and socket called LGA 1700.

AMD is always in development mode and just when they launch a new product, the company is always gearing up for the next-generation of devices. Just a few months ago, back in November, AMD has launched its Zen 3 core, and today we get to hear about the next steps that the company is taking to stay competitive and grow its product portfolio. In the AnandTech interview with Dr. Lisa Su, and The Street interview with Rick Bergman, the EVP of AMD's Computing and Graphics Business Group, we have gathered information about AMD's plans for Zen 4 core development and RDNA 3 performance target.

Starting with Zen 4, AMD plans to migrate to the AM5 platform, bringing the new DDR5 and USB 4.0 protocols. The current aim of Zen 4 is to be extremely competitive among competing products and to bring many IPC improvements. Just like Zen 3 used many small advances in cache structures, branch prediction, and pipelines, Zen 4 is aiming to achieve a similar thing with its debut. The state of x86 architecture offers little room for improvement, however, when the advancement is done in many places it adds up quite well, as we could see with 19% IPC improvement of Zen 3 over the previous generation Zen 2 core. As the new core will use TSMC's advanced 5 nm process, there is a possibility to have even more cores found inside CCX/CCD complexes. We are expecting to see Zen 4 sometime close to the end of 2021.

ADATA Technology, a manufacturer of high-performance DRAM modules, NAND Flash products, mobile accessories, gaming products, electric power trains, and industrial solutions, is gearing up to bring next-generation DDR5 memory modules to market to offers users a significant upgrade in speed, capacity, as well as increased bandwidth per CPU cores. ADATA has been working closely with two leading motherboard makers, MSI and Gigabyte, to ensure an optimized experience through ensuring synergies between ADATA's DDR5 modules and their latest Intel platforms.

In parallel to developing the new memory modules, ADATA has also been working closely with two leading motherboard makers MSI and Gigabyte, its long-term strategic partners, to ensure their new platforms can take full advantage of DDR5. Among other initiatives, ADATA, MSI, and Gigabyte have been conducting joint testing and research to guarantee optimum DDR5 overclocking on the latest Intel platforms to meet gamers' discerning standards. ADATA and the motherboard above makers will be launching DDR5 modules and DDR5-compliant motherboards simultaneously to offer high performance to a wide range of users, including enterprises, gamers, and creators, to name a few.

Intel has just released its "Architecture Instruction Set Extensions and Future Features Programming Reference" manual, which serves the purpose of providing the developers' information about Intel's upcoming hardware additions which developers can utilize later on. Today, thanks to the @InstLatX64 on Twitter we have information that Intel is bringing on-package High Bandwidth Memory (HBM) solution to its next-generation Sapphire Rapids Xeon processors. Specifically, there are two instructions mentioned: 0220H - HBM command/address parity error and 0221H - HBM data parity error. Both instructions are there to address data errors in HBM so the CPU operates with correct data.

The addition of HBM is just one of the many new technologies Sapphire Rapids brings. The platform is supposedly going to bring many new technologies like an eight-channel DDR5 memory controller enriched with Intel's Data Streaming Accelerator (DSA). To connect to all of the external accelerators, the platform uses PCIe 5.0 protocol paired with CXL 1.1 standard to enable cache coherency in the system. And as a reminder, this would not be the first time we see a server CPU use HBM. Fujitsu has developed an A64FX processor with 48 cores and HBM memory, and it is powering today's most powerful supercomputer - Fugaku. That is showing how much can a processor get improved by adding a faster memory on-board. We are waiting to see how Intel manages to play it out and what we end up seeing on the market when Sapphire Rapids is delivered.

Intel needs a platform refresh to battle the competition, mainly speaking to battle AMD and its Ryzen 5000 series processors. That is why the company is developing 500 series of chipsets covering the low-end (H510), mid-range (B560), and high-end markets (Z590) that pair with the upcoming Rocket Lake-S processor generation. Dubbed 11th generation of Core processors, the 11th generation of Intel Core CPUs are going to be built on Intel's refined 14 nm process. The CPUs are supposed to feature a Cypress Cove core, which is a backport of Golden Cove found in Ice Lake. The 500 series motherboards are the last in the DDR4 generation, launching in the timeframe when DDR5 is supposed to take over in the coming years.

Today, thanks to Weixin, a Chinese media outlet that posted a short story on the WeChat platform, we have information about the launch date of these new chipsets. According to the source, we are allegedly going to see these new chipsets on January 11th, the day that Intel CES 2021 event is supposed to happen. The platform will include a range of motherboards from Intel's partners and is supposed to bring support for the much-needed PCIe 4.0 protocol. The launch date should be taken with a grain of salt, of course, before taking it as a fact.

Team Group, a global leader in computer memory, has rapidly responded to market demand changes during the crucial transition period of next-generation DRAM technology. By integrating the newest technologies to promote its development of DDR5 memory, it has outpaced competitions and developed the first engineering sample of consumer-grade DDR5 memory. With this success, it will welcome the new DDR5 generation with consumers worldwide.

Presently, Team Group is working hard at producing its first batch of DDR5 memory with the tentative specifications of 16 GB, 4800 MHz, and 1.1 V for a single module. The company is cooperating with major motherboard manufacturers, such as ASUS, MSI, ASRock, and GIGABYTE, providing memory and working together with their R&D divisions to perform validation tests. Through the collaboration of R&D teams, Team Group was able to accelerate the development of its DDR5 memory by adjusting the initial parameters. The successful completion of the validation phase will confirm that the frequencies of standard DDR5 products surpass those of overclocked DDR4 products, and will represent another big step forward in the evolution of computer memory.