Xilinx, Inc., the leader in adaptive computing, today introduced the Versal HBM adaptive compute acceleration platform (ACAP), the newest series in the Versal portfolio. The Versal HBM series enables the convergence of fast memory, secure connectivity, and adaptable compute in a single platform. Versal HBM ACAPs integrate the most advanced HBM2E DRAM, providing 820 GB/s of throughput and 32 GB of capacity for 8X more memory bandwidth and 63% lower power than DDR5 implementations. The Versal HBM series is architected to keep up with the higher memory needs of the most compute intensive, memory bound applications for data center, wired networking, test and measurement, and aerospace and defense.

"Many real-time, high-performance applications are critically bottlenecked by memory bandwidth and operate at the edge of their power and thermal limits," said Sumit Shah, senior director, Product Management and Marketing at Xilinx. "The Versal HBM series eliminates those bottlenecks to provide our customers with a solution that delivers significantly higher performance and reduced system power, latency, form factor, and total cost of ownership for data center and network operators."

If you even came across a PC system that had a problem with its Ram, there are high chances that you have used PassMark Software MemTest86 software for testing and revealing DRAM errors. The software uses a chain of algorithms, including SIMD and row hammer tests, to try to test if the memory is in a good shape or it has some problems. PC builders have used the software for years to detect and isolate any potential Ram issues that occurred. Today, makers of MemTest86, PassMark Software, previewed initial support for DDR5 memory in their internal software builds. That means that by the time DDR5 memory hits the consumer market, we will have software for testing any possible defective Ram.

The Intel Core i9-12900K is the companies upcoming flagship 12th Generation Alder Lake-S processor featuring a hybrid design with 8 high-performance cores and 8 high-efficiency cores. The qualification sample for the processor reportedly features a base clock of 3.9 GHz and a boost clock of 5.3 GHz which is less than initial rumors which claimed boost speeds could reach 5.5 GHz. The processor achieved a multi-core score of 11300 points in Cinebench R20 which is 800 points higher than AMD's flagship Ryzen 9 5950X. Intel's 12th Generation Alder Lake-S processors will be manufactured on the 10 nm Enhanced SuperFin node and will include support for PCIe 5.0 and DDR5. Intel is expected to announce the processors in Q3 2021 for a Q4 2021 release which will position them against AMD's upcoming V-Cache technology expected to arrive in early 2022.

As third quarters have typically been peak seasons for the production of various end-products, the sufficiency ratio of DRAM is expected to undergo a further decrease in 3Q21, according to TrendForce's latest investigations. However, DRAM buyers are now carrying a relatively high DRAM inventory due to their amplified purchases of electronic components in 1H21. The QoQ increase in DRAM contract prices are hence expected to slightly narrow from 18-23% in 2Q21 to 3-8% in 3Q21. Looking ahead to 4Q21, TrendForce believes that DRAM supply will continue to rise, thereby leading to either a further narrowing of price hikes or pressure constraining the potential price hike of DRAM products.

From the perspective of demand, the stay-at-home economy has resulted in persistently high demand for notebook computers. Although discrepancies still exist among notebook brands' inventory levels of various components, these brands are still making an aggressive attempt at maximizing their production of notebooks. However, as most of these brands are still carrying about 8-10 weeks' worth of PC DRAM inventory (which is relatively high), PC DRAM purchasing strategies from the buyers' side will therefore remain relatively conservative. From the perspective of supply, due to the rising demand for server DRAM, the production capacity allocated to PC DRAM is still in a severe supply crunch. Hence, DRAM suppliers are firm in their attitudes to raise PC DRAM quotes, and TrendForce expects the price negotiations between PC DRAM buyers and suppliers in 3Q21 to become both lengthier and more difficult as a result, with contract prices likely finalized at the end of July. Even so, what is now certain is that both sides have reached some level of understanding regarding the ongoing price hike of PC DRAM products. TrendForce forecasts a 3-8% increase in PC DRAM contract prices for 3Q21.

Intel is slowly preparing to launch its 4th generation of Xeon Scalable processors, with it being the first arrival of the 10 nm designs to the server market. Codenamed Sapphire Rapids, these processors are expected to bring much-needed IPC and platform improvements so Intel can keep up with AMD's EPYC processors. Today, we are getting some first performance results as well as some information about a specific 20 core, 40 threaded Intel Xeon Sapphire Rapids SKU. In a leaked Geekbench 4 submission, the latest Xeon processor was tested and we get to see even more details about the processor.

Featuring 20 cores and 40 threads, the CPU has a base clock speed of 1.5 GHz. It features as much as 40 MB of L2 cache and 75 MB of L3 cache spread across the die. The system was tested on an Intel reference platform called VulcanCity, with this configuration carrying 32 GB of DDR5 memory. The reported results of the benchmarks that this processor went through are not very impressive. These numbers are easily beaten by AMD Ryzen 9 5950X, however, this is only an engineering sample with low clock speed and it could be possible that Geekbench is not optimized to run on this processor. You can check out some of the performance numbers below, and see the submitted results here.

For gamers who are ready to go to the next level, ZADAK, a leading provider of enthusiast PC gaming components and innovative water cooling solutions under Apacer Technology announces the next step forward in gaming DRAM. The newest member of its high end SPARK lineup is a DDR5 RGB illuminated gaming DRAM module which is available in 16 GB and 32 GB capacities. Gamers who demand t he fastest clock speeds will be able to choose from modules ranging from 4800 MHz all the way up to 7200 MHz.

DDR5 also features another important upgrade: power management is no longer handled by the motherboard, but by a PMIC (power management integrated circuit) on the module itself. While DDR4 modules consume 1.2 V, DDR5 modules only require 1.1 V. It sounds like a small difference, but over hours and days of gaming, it adds up to significant power savings. The PMIC also gives overclockers more options when it comes to tweaking settings. ns when it comes to tweaking settings.

Intel's Lisa Spelman, corporate vice president and general manager of the Xeon and Memory Group at Intel Corporation, has yesterday published a blog post talking about Intel's next-generation server platform codenamed Sapphire Rapids. The SPR platform is Intel's biggest step-up in the server processor space, and it is the exact CPU that will power the Aurora exascale supercomputer. Besides improvements to the CPU microarchitecture, the platform itself is bringing many benefits with it as well. It will use the latest industry protocols like DDR5 and PCIe 5.0. This is making a strong combination designed even for exascale supercomputers to be powered by this processor. However, the availability of this CPU was a bit of a mystery until yesterday. Below, you can see the quote from Ms. Lisa Spelman about the availability of said processors.

Lisa SpelmanDemand for Sapphire Rapids continues to grow as customers learn more about the benefits of the platform. Given the breadth of enhancements in Sapphire Rapids, we are incorporating additional validation time prior to the production release, which will streamline the deployment process for our customers and partners. Based on this, we now expect Sapphire Rapids to be in production in the first quarter of 2022, with ramp beginning in the second quarter of 2022.

Intel today, in its 2021 International Supercomputing Conference presentation, revealed that certain next-generation Xeon "Sapphire Rapids" SKUs come with on-package high-bandwidth memory (HBM). Given the context of its presentation, these could be special SKUs designed for high-density HPC setups, in which the processor package includes certain amount of "PMEM" (package memory), besides the processor's 8-channel DDR5 memory interface.

The size of the HBM PMEM, and its position in the memory hierarchy, were detailed, too. Given its high-density applications, PMEM may not serve as a victim cache for the processor, but rather be capable of serving as main memory, with none of the DDR5 DRAM channels populated with DIMMs. On machines with DIMMs, the PMEM will serve as a victim cache for the processor's on-die last-level cache, accelerating the memory I/O. "The next-generation of Intel Xeon Scalable processors (code-named "Sapphire Rapids) will offer integrated High Bandwidth Memory (HBM), providing a dramatic boost in memory bandwidth and a significant performance improvement for HPC applications that operate memory bandwidth-sensitive workloads. Users can power through workloads using just High Bandwidth Memory or in combination with DDR5," says Intel.

At the 2021 International Supercomputing Conference (ISC) Intel is showcasing how the company is extending its lead in high performance computing (HPC) with a range of technology disclosures, partnerships and customer adoptions. Intel processors are the most widely deployed compute architecture in the world's supercomputers, enabling global medical discoveries and scientific breakthroughs. Intel is announcing advances in its Xeon processor for HPC and AI as well as innovations in memory, software, exascale-class storage, and networking technologies for a range of HPC use cases.

"To maximize HPC performance we must leverage all the computer resources and technology advancements available to us," said Trish Damkroger, vice president and general manager of High Performance Computing at Intel. "Intel is the driving force behind the industry's move toward exascale computing, and the advancements we're delivering with our CPUs, XPUs, oneAPI Toolkits, exascale-class DAOS storage, and high-speed networking are pushing us closer toward that realization."

Marvell today introduced its new OCTEON 10 DPU designed to accelerate and process a broad spectrum of security, networking, and storage workloads required by demanding 5G, cloud, carrier and enterprise datacenter applications. With the increasing shift of workloads to the cloud, complex security requirements and the growing number of edge devices the demand for data centric compute has accelerated. By combining compute with best-in-class hardware accelerators, Marvell's OCTEON 10 DPU offers a significant TCO advantage and features numerous industry firsts. Delivering three times the performance and 50 percent lower power compared to previous generations of OCTEON, the newly announced solution is the first to be designed on a 5 nm process to incorporate Arm Neoverse N2 cores, as well as the first inline artificial intelligence/machine learning (AI/ML) hardware acceleration, the first integrated 1 terabit switch and the first to incorporate vector packet processing (VPP) hardware accelerators.

"To meet and exceed the growing data processing requirements for network, storage, and security workloads, Marvell focused on significant DPU innovations across compute, hardware accelerators, and high speed I/O," said John Sakamoto, vice president of Marvell's Infrastructure Processors Business Unit. "The OCTEON 10 brings compute leadership, supports networking and security workloads exceeding 400G, and incorporates leading edge I/O including DDR5 and PCIe 5.0."

The release notes for the latest version of famous system utility HWiNFO have spilled the beans on an update to Intel's XMP. Currently at version 2.0, XMP (eXtreme Memory Profile) is a technology that allows the system-level BIOS to run DDR memory at speeds higher than those allowed by JEDEC, the governing specifications body for all things memory. It extends the performance profiles usually made available via SPD (Serial Presence Detect). An update to Intel's XMP (XMP 3.0) for DDR5 memory is referred to in the release notes for version 7.05 of the software. Not much more to look at here - it remains to be seen what changes are actually a part of XMP 3.0, and if any increased utility will be added to these profiles. Remember, however, that nor Intel nor AMD (via its A-XMP implementation) enable warranty coverage should XMP be enabled in your system.

Other relevant updates for the application include advanced early support for Zen 4 systems (looking at you, AMD), as well as per-core temperature monitoring for Zen-based CPUs. There are other additions to the supported hardware, which you can find in the screenshot below.

AMD's next generation Ryzen Embedded V3000 system-on-chips aren't simply "Cezanne" dies sitting on BGA packages, but rather based on a brand new silicon, according to Patrick Schur, a reliable source with leaks. The die will be built on the more advanced 6 nm silicon fabrication node, whilst still being based on the current "Zen 3" microarchitecture. There are several things that set it apart from the APU silicon of the current-generation, making it more relevant for the applications the Ryzen Embedded processor family is originally built for.

Built in the FP7r2 BGA package, the V3000 silicon features an 8-core/16-thread CPU based on the "Zen 3" microarchitecture. There are also an integrated GPU based on the RDNA2 graphics architecture, with up to 12 CUs, a dual-channel DDR5 memory interface, a 20-lane PCI-Express 4.0 root complex, with up to 8 lanes put out for PEG; two USB4 ports, and two 10 GbE PHYs. AMD could design at least three SKUs based on this silicon, spanning TDP bands of 15-30 W and 35-54 W.

At the end of 2020, TEAMGROUP reached a cooperation agreement with top DRAM wafer manufacturers and started working on DDR5 technology. Since then, TEAMGROUP has dedicated to the research and development of DDR5 modules, collaborating with various major motherboard manufacturers to ensure that each R&D stage undergoes comprehensive testing and to deliver products of the highest quality that the industry has ever seen. TEAMGROUP is leading the industry today as we announce our official launch of the world's first DDR5 memory module for desktops, the TEAMGROUP ELITE U-DIMM DDR5, which is estimated to be available on major EC platforms for consumers worldwide by the end of June and the beginning of July.

The initial launch of TEAMGROUP ELITE DDR5 memory module will support 16GBx2 of capacity at a frequency of 4800 MHz, with a voltage of 1.1 V CL40-40-40-77, which complies with the standard specifications defined by the JEDEC association. Compared to the maximum 3200 MHz standard frequency in the DDR4 generation, the DDR5 is able to increase the speed to up to 50%. The low 1.1 V voltage is also more energy efficient than its previous generation; to ensure minimum noise interference for the memory module, the power management is transferred from the motherboard onto the memory with an additional power management IC (PMIC) for more effective system load control. The most incredible feature of ELITE DDR5 is doubling the 16 banks of DDR4 to those of 32 in DDR5 to improve the IC structure, providing double access availability. An on-die ECC (error correction code) included in the DRAM IC is also available for self-recovery of the DRAM unit, ensuring that DRAM systems with DDR5 can obtain higher levels of stability.

Innodisk has officially announced the release of its industrial-grade DDR5 DRAM modules. The new standard touts a host of crucial performance improvements and power savings over its predecessor, and anticipation has been high since the official announcement of the standard. Boasting a bucketload of benefits, including the obligatory speed and storage increases, DDR5 will eventually take its place as the memory option of choice.

The JESD79-5 DDR5 SDRAM specification signaled the transition to DDR5, with significant improvements in capacity, speed, voltage, and ECC functions. The DDR5 specification details up to four times as much capacity per IC, raising the maximum achievable per die capacity to 64Gb and bringing the maximum potential capacity for a single DDR5 DIMM to 128 GB.

The latest Status of the Memory Industry report from June 2021 published by Yole Developments shows the memory market continues to grow and is expected to exceed 200 billion USD in 2026. The introduction of DDR5 memory will be extremely quick with shipments expected to exceed that of DDR4 in 2023 and will account for over 90% of bits shipped by 2026. The major DRAM manufacturers have all finalized their mainstream DDR5 designs with shipments from several having already started. The report also predicts an increase in the amount of DRAM used in all product categories which will contribute to strong revenue growth for memory manufacturers.

Tachyum Inc. today announced that it has taken delivery of an IO motherboard for its Prodigy Universal Processor hardware emulator from manufacturing. This provides the company with a complete system prototype integrating CPU, memory, PCI Express, networking and BMC management subsystems when connected to the previously announced field-programmable gate array (FPGA) emulation system board.

The Tachyum Prodigy FPGA DDR-IO Board connects to the Prodigy FPGA CPU Board to provide memory and IO connectivity for the FPGA-based CPU tiles. The fully functional Prodigy emulation system is now ready for further build out, including Linux boot and incorporation of additional test chips. It is available to customers to perform early testing and software development prior to a full four-socket reference design motherboard, which is expected to be available Q4 2021.

Kingston Technology Europe Co LLP, an affiliate of Kingston Technology Company, Inc., today announced the name of its new high-performance, enthusiast and gaming brand: Kingston FURY. Building on the incredible success of the HyperX memory products, Kingston has rebranded its DRAM, flash and SSD gaming line into Kingston FURY, investing resources and knowledge from its core business to create the next generation of performance products.

Kingston FURY continues the evolution of leading-edge, high-performance, enthusiast and gaming memory solutions from the largest independent memory manufacturer in the world, backed by three decades of Kingston engineering, testing, manufacturing and customer service expertise. The company's leadership position in the DRAM industry demonstrates it has the passion, commitment and resources to make Kingston FURY the leading high-performance, enthusiast and gaming memory solution in the market.

XPG, a fast-growing provider of systems, components, and peripherals for Gamers, Esports Pros, and Tech Enthusiasts, today announces that it will launch its new DDR5 gaming memory modules in Q3 2021. The new product series will be known as the CASTER series. The modules will deliever frequencies ranging from 6000 to 7400 MHz and come with capacities of 8, 16, or 32 GB. XPG has been working closely with its motherboard partners, including GIGABYTE, MSI, ASUS, and ASRock, to ensure the highest level of compatibility and ability to realize extreme overclocking performance.

The new DDR5 modules will come in two variants, with and without RGB. Despite this difference, they share a cohesive industrial design. The products' designs convey an understated sense of depth and textural contrast with the use of two surface treatments, one glossy and one matte. For added depth, the matte surface of the modules are beveled for an additional textural element and futuristic look. To communicate the XPG brand, the modules sport diagonal intersecting lines and grooves that form geometric forms and X shapes that play off the XPG brand name and visual identity.

We've known since last week that AMD's upcoming desktop processor socket, AM5, will be a land-grid array (LGA), much like Intel's desktop sockets; and today we have a first-look at what the land-grid will look like, courtesy of ExecutableFix, who first broke news of AM5 being an LGA of 1,718 pins. Below is a render of the AM5 contact pad (the underside of the processor). The 1,718 contacts span across the fiberglass substrate, with no socket island in the middle for ancillaries. All electrical ancillaries are located on the obverse side of the substrate, surrounding the die(s). The substrate area will remain 40 mm x 40 mm, so the processor package will be roughly of the same size as AM4. In comparison, Intel's upcoming LGA1700 package is expected to measure 37.5 mm x 45 mm (a rectangular substrate).

ExecutableFix put out a handful more details about the I/O of this socket. Apparently, AM5 is a pure-DDR5 platform, with no backwards compatibility with DDR4. The socket features a dual-channel DDR5 memory interface. The PCI-Express interface is PCI-Express 4.0, with the socket putting out 28 lanes in total. 16 of these go to the PEG slot(s), four to an M.2 NVMe slot, and possibly the remaining eight as chipset bus. Considering these are Gen 4, the next-generation X670 (X570 successor) chipset could have double the chipset-bus bandwidth compared to Intel Z590. A typical Socket AM5 chip, such as "Rembrandt," could feature a TDP of 120 W, going up to 170 W, according to the source.

A reliable source with AMD and NVIDIA leaks, ExecutableFix has shared some interesting bits of early information on AMD's next-generation Socket AM5. Apparently this will be AMD's first mainstream-desktop socket that does away with pins on the processor package, shifting them to the motherboard, in a Land Grid Array (LGA) format. This won't be AMD's first client LGA, though, as it was the Quad FX platform from 2006, which used a pair of Socket F LGAs. Socket AM5 will have a pin-count of 1,718 pins, 18 more than Intel's upcoming Socket LGA1700, on which its 12th Gen Core "Alder Lake-S" is expected to be based.

AMD will give the I/O of its client desktop platform a major update, with the introduction of DDR5 memory. Socket AM5 processors are expected to feature a dual-channel DDR5 memory interface. With Intel "Alder Lake-S" implementing DDR5, too, you now know why every major memory manufacturer is unveiling their first DDR5 U-DIMM product development. Interestingly, the PCI-Express interface on Socket AM5 will remain PCI-Express 4.0, even though PCI-Express 5.0 is being rumored for "Alder Lake-S." The switch to PCI-Express 5.0 may not be significant from a graphics cards perspective immediately, but paves the way for next-gen M.2 NVMe SSDs with double the transfer-rates of current drives that use PCI-Express 4.0. AMD is developing the new 600-series chipset to do with its next-generation Socket AM5 processors.

GeIL, Golden Emperor International Ltd. - one of the world's leading PC component manufacturers, is proud to announce the next-generation DDR5 RGB high-performance gaming memory, Polaris RGB, is ready for the upcoming DDR5 platform. The GeIL Polaris RGB Gaming Memory will be available in Q4, 2021, with capacities ranging from 16 GB (16 GB x1) up to 128 GB (32 GB x4).

It has been seven years since DDR4 launched into the market, and GeIL has put countless hours into developing the new DDR5 memory modules. And in doing so, GeIL has designed the Polaris RGB to provide RGB illuminated high-performance DDR5 gaming memory and has been working closely with motherboard makers to guarantee the best compatibility and reliability among the latest Intel and AMD motherboards.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced the industry's first integrated power management ICs (PMICs) — S2FPD01, S2FPD02 and S2FPC01, for the fifth-generation double data rate (DDR5) dual in-line memory module (DIMM). One major design improvement to the newest generation DRAM solution involves integrating the PMIC into the memory module — previous generations placed the PMIC on the motherboard — offering increased compatibility and signal integrity, and providing a more reliable and sustained performance.

For improved performance efficiency and load-transient responses, Samsung's new PMICs for DDR5 modules have been equipped with a high-efficiency hybrid gate driver and a proprietary control design (asynchronous-based dual-phase buck control scheme). This scheme allows the DC voltage to step down from high to low with a fast transient response to changes in the output load current and adapts the conversion accordingly to efficiently regulate its output voltage at near-constant levels. The control scheme also features both pulse width and pulse frequency modulation methods, preventing delays and malfunctions when switching modes.

The fifth iteration of DDR technology, called DDR5, is set to arrive later this year. Many makers of DDR4 technology are announcing their plans to switch to the new standard, and CORSAIR is no exception. Known as the maker of high-quality products, CORSAIR has today posted a blog post teasing company's upcoming DDR5 products, and what they will be bringing to the table. For starters, the company has posted data about DDR5 modules that run at 6400 MHz speed, which is assumed to be the speed of the CORSAIR DDR5 modules when they arrive. At such speed, the memory can achieve a bandwidth of 51 GB/s, which is almost double the 26 GB/s that DDR4-3200 MHz memory achieves.

Another point CORSAIR wrote about is the capacity of a single DIMM. With DDR4, the company has made DIMMs that are only up to 32 GB in capacity. However, with DDR5, CORSAIR plans to quadruple that and build a single DDR5 DIMM that has up to 128 GB of memory on it. Another big point was the power required to run the new technology. The DDR4 standard required 1.2 Volts for operation, while the JEDEC specification says that DDR5 needs just 1.1 Volts to run. This will result in a cooler operation of memory modules.

Intel's upcoming Alder Lake-S processors are going to be the company's first attempt at delivering heterogeneous core solutions, combining low-power and high-performance IPs in a single chip. Another important milestone that these processors will reach is DDR5 memory adoption, the first of its kind on consumer platforms. Today, thanks to CapFrameX, a monitoring tool that also hosts a database of benchmark runs, we have a piece of recorded information coming from a test system equipped with an Intel Alder Lake-S processor. The tested system spotted an engineering sample of the Alder Lake-S lineup, clocked at just 2.2 GHz. The core count and core configuration remained unknown.

Alongside the upcoming CPU, the system is composed of NVIDIA's GeForce RTX 3080 GPU and DDR5 memory running at 4800 MHz. There were four sticks present, each having 8 GB capacity. The leaked system was running the DOTA 2 game at an average of 119.98 FPS, which doesn't mean much, given that we don't know which settings were applied and what was the resolution. There is a chart showing the gaming frame rate and frame time, which could be interesting to look at. However, the only new information we have come to know is that the Alder Lake-S is already capable of playing games and the ecosystem support should be very good at launch.

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today unveiled the industry's first memory module supporting the new Compute Express Link (CXL) interconnect standard. Integrated with Samsung's Double Data Rate 5 (DDR5) technology, this CXL-based module will enable server systems to significantly scale memory capacity and bandwidth, accelerating artificial intelligence (AI) and high-performance computing (HPC) workloads in data centers.

The rise of AI and big data has been fueling the trend toward heterogeneous computing, where multiple processors work in parallel to process massive volumes of data. CXL—an open, industry-supported interconnect based on the PCI Express (PCIe) 5.0 interface—enables high-speed, low latency communication between the host processor and devices such as accelerators, memory buffers and smart I/O devices, while expanding memory capacity and bandwidth well beyond what is possible today. Samsung has been collaborating with several data center, server and chipset manufacturers to develop next-generation interface technology since the CXL consortium was formed in 2019.