Thursday, August 19th 2021
Intel's "Alder Lake" Desktop Processor supports DDR4+DDR5, (only few) PCIe Gen 5 and Dynamic Memory Clock
Intel will beat AMD to next-generation I/O, with its 12th Generation Core "Alder Lake-S" desktop processors. The company confirmed that the processor will debut both DDR5 memory and PCI-Express Gen 5.0, which double data-rates over current-gen DDR4 and PCI-Express Gen 4, respectively. "Alder Lake-S" features a dual-channel DDR5 memory interface, with data-rates specced to DDR5-4800 MHz, more with overclocking, reaching enthusiast-grade memory attaining speeds in excess of DDR5-7200. Besides speed, DDR5 is expected to herald a doubling in density, with 16 GB single-rank modules becoming a common density-class, 32 GB single-rank being possible in premium modules; and 64 GB dual-rank modules being possible soon. Leading memory manufacturers have started announcing their first DDR5 products in preparation of "Alder Lake-S" launch in Q4-2021.
The memory controller is now able to dynamically adjust memory frequency and voltage, depending on current workload, power budget and other inputs—a first for the PC! This could even mean automatic "Turbo" overclocking for memory. Intel also mentioned "Enhanced Overclocking Support" but didn't go into further detail what that entails. While DDR5 is definitely the cool new kid on the block, Intel's Alder Lake memory controller keeps support for DDR4, and LPDDR4, while adding LPDDR5-5200 support (important for mobile devices). Just to clarify, there won't be one die support DDR5, and another for DDR4, no, all dies will have support for all four of these memory standards. How that will work out for motherboard designs is unknown at this point.
PCI-Express Gen 5.0 is the other big I/O feature. With a bandwidth of 32 Gbps per lane, double that of PCIe Gen 4, the new PCIe Gen 5 will enable a new breed of NVMe SSDs with sequential transfer rates well above 10 GB/s. The desktop dies will feature x16 PCIe Gen 5, and x4 PCIe Gen 4. The PCIe 5.0 x16 can be split into an x8 (for graphics) and 2x x4 (for storage), but it's not possible to run a PCIe 5.0 x16 graphics card at the same time as a PCIe 5.0 SSD. The PCH features up to 12 downstream PCIe Gen4 lanes, and 16 PCIe Gen3 lanes. In any case, we don't expect even the next generation of GPUs, such as RDNA3 or Ada Lovelace, to saturate PCI-Express 4.0 x16. Interestingly, Intel isn't taking advantage of PCI-Express Gen 5 to introduce a new Thunderbolt standard, with 40 Gbps Thunderbolt 4 being mentioned as one of the platform I/O standards for this processor. This could be a very subtle hint that Intel is still facing trouble putting cutting-edge PCIe standards on its chipset-attached PCIe interface. It remains to be seen if the 600-series chipset goes beyond Gen 3. There could, however, be plenty of CPU-attached PCIe Gen 5 connectivity.
The memory controller is now able to dynamically adjust memory frequency and voltage, depending on current workload, power budget and other inputs—a first for the PC! This could even mean automatic "Turbo" overclocking for memory. Intel also mentioned "Enhanced Overclocking Support" but didn't go into further detail what that entails. While DDR5 is definitely the cool new kid on the block, Intel's Alder Lake memory controller keeps support for DDR4, and LPDDR4, while adding LPDDR5-5200 support (important for mobile devices). Just to clarify, there won't be one die support DDR5, and another for DDR4, no, all dies will have support for all four of these memory standards. How that will work out for motherboard designs is unknown at this point.
24 Comments on Intel's "Alder Lake" Desktop Processor supports DDR4+DDR5, (only few) PCIe Gen 5 and Dynamic Memory Clock
As for this announcement ... I might be getting tired of the never-ending specs race, but is this actually meaningful in any way? Now, I don't generally benchmark beyond testing out new parts and a tad of occasional tuning. So, the experience is what matters. And given that we know that the difference between NVMe and SATA SSDs is near imperceptible, and 3.0 and 4.0 is entirely imperceptible (outside of very niche use cases), what is the actual real-world benefit from PCIe 5.0? DDR5 I can see, at least for iGPU performance and memory bound HPC/datacenter workloads, but PCIe 5.0 for consumers? Nope. Not beyond making motherboards more expensive, likely increasing power consumption, and allowing for the sale of ever more expensive "premium" parts with zero noticeable performance differences compared to previous PCIe generations. GPUs too ... is there a push for moving future mid-range and low-end GPUs to x4 links for space/money/PCB area savings? 'Cause if not, then PCIe 3.0 x16 or 4.0 x8 is sufficient for every GPU out there, and for the people insisting that the >1% performance increase to 4.0 x16 is noticeable, well, that's ubiquitous. PCIe 5.0 won't affect GPU performance for years and years and years.
I guess this would be good for bifurcated SFF builds seeing how you can get more out of a single x16 slot, but that is assuming we get low lane count parts (5.0 x1 SSDs would be interesting). But again that's such a niche use case it's hardly worth mentioning.
Looks like Intel has finally made a platform with sufficient PCIe lanes for everything that possibly could be crammed onto a consumer motherboard.
II expect that, because they packed so many new techs into a single chip , they will be lucky to have review units available before Q1 next year.
However, I agree with you with regards to PCIe 5.0, since at least as far as we're aware, there's nothing in the pipeline that will make sense for consumers that can benefit from it and possibly even less so when it's only available for the GPU slot. As we're only two generations of GPUs in on PCIe 4.0, it'll most likely take another two or three before there's a move to PCIe 5.0, unless Intel is going to jump the gun...
I thought Intel didn't support bifurcation on its consumer platforms? Maybe that has changed since I last looked.
PCI-E Gen4 runs hot and is power hungry, atleast on AMD Plataform.
The PCIe power spec hasn't changed since version 2.1 when it come to the board connectors.
That devices connected to an interface uses more power and runs hotter has nothing to do with the physical interface.
As for bifurcation, I haven't really paid that much attention to Intel's platforms in recent years, but at least back in the Z170 era there were a few OEMs that enabled bifurcation as a BIOS option (IIRC ASRock used to be "generous" in that regard). It's needed for boards with x16+x0/x8+x8 PCIe slot layouts after all, and for 2/4 drive m.2 AICs (unless they have PLX chips, which a few do), but that of course doesn't mean it's necessarily available as a user-selected option.Oh, yeah, servers want all the bandwidth you can throw at them. That's the main driving force for both DDR5 and PCIe 5.0 AFAIK.
We barely have USB 3.2 2x2 (i.e. 20Gbps) support and even the boards that have it, has one or two ports at most.
Again, this is something of a bandwidth issue and the current single port controllers are never going to hit 20Gbps, as they're limited to two PCIe 3.0 lanes, which is 16Gbps of bandwidth. So even here, PCIe 4.0 would bring benefits once the host controller makers move to PCIe 4.0, which might still take a little while.
The rest is mostly niche cases today, like some high-end capture cards that could benefit from PCIe 4.0, by either using fewer PCIe lanes or adding support for more channels and/or higher resolution/bandwidth. However, I don't see most consumers using something like this. In fact, most consumers don't use any of things we're discussing here.
According to the diagram above, it looks like the chipset will get 12 PCIe 4.0 lanes and 16 PCIe 3.0, unless I'm reading that entirely wrong. There has also been leaks/rumours suggesting that some 600-series chipset will have Thunderbolt 4 integrated. and that we'll see DMI 4.0 with the possibility of up to eight lanes connecting with the CPU.
videocardz.com/newz/exclusive-intel-12th-gen-core-alder-lake-s-platform-detailed
I had a look with regards to bifurcation and Intel is slightly more limited than AMD in this instance it seems, but again, unless you want to run four SSDs from a single x16 slot, it's not going to matter and if you try that on an AMD system, I'm not sure how you're going to drive the display.
The reason would rather be that it's using a repurposed die with a bunch of useless mm² that sucks power.
And the X570 chipset can apparently run hot, if you're putting heavy load on a pair of PCIe 4.0 NVMe SSDs in RAID.
It's not directly related to PCIe 4.0 as you mention.
You're right about fast USB ports needing the bandwidth, but (and this might be a controversial opinion): I don't see a reason to add more high speed ports. New standards, like 4.0? Sure, yes, move 3.2g2 ports to 4.0, or add a couple more at the very most. But more than 4 ports in that speed class is just wasteful. Heck, people barely utilize USB 3.0 speeds most of the time, and the number of external 3.2G2x2 devices out there capable of actually utilizing 20Gbps can likely be counted on two hands. Having access to fast I/O is valuable, having tons of it is useless spec fluffing. And it drives up board costs. Heck, with 10-12 USB ports on a board I wouldn't even mind 4 of them being 2.0 - that'd still leave far more fast I/O than 99.99999% of users will ever utilize. 2 fast ports, 4-6 5Gbps ports and a few 2.0 ports is enough for pretty much anyone (front I/O of course adds to this as well).
Of course, Intel apparently still isn't integrating TB into their desktop CPUs or chipsets, so that will still be an optional add-on requiring lanes and complicating board designs (though at least now chipsets have plenty of PCIe to handle that). I was kind of expecting them to add a couple of USB4/TB4 ports given their push for this with TGL, but I guess that's mobile-only.
This still had nothing to do with PCIe 4.0, but you're free to choose to not to understand that part.
You need to learn to differentiate between things.
- that consumer m.2 PCIe 5.0 SSDs will actually meaningfully outperform 3.0 and 4.0 drives in real world workloads within the lifetime of this platform
- that DS, which is designed around the ~2GBps peak drives in the Xboxes will be able to benefit from significantly higher speeds
- that games will be able to make use of this additional bandwidth
So unless all of these come true, this will be one lf those classic highly marketed features that come with zero tangible benefits.
Unless Intel has some miracle way of changing timings on the fly, this is a terrible idea because it will only increase latencies.
I don't see PCIe 5.0 making a difference there at least at the start.
:confused::confused::confused:
The only time I've heard of an X570 board overheating was a crazy dense SFF build where someone crammed a 5950X and RTX 2080Ti into an NFC S4M and cooled them with a single 140mm radiator (yes, apparently that is possible, though it requires a lot of custom fabrication, including a modified server PSU). They had removed the stock chipset heatsink for space savings, replaced it with a small standard chipset heatsink and a slim 40mm fan, but kept having throttling issues due to 100-110°C chipset temps. But that, needless to say, is a rather unusual scenario.